root / hw / ide.c @ 1ffc346f
History | View | Annotate | Download (116.6 kB)
1 | 5391d806 | bellard | /*
|
---|---|---|---|
2 | 38cdea7c | balrog | * QEMU IDE disk and CD/DVD-ROM Emulator
|
3 | 5fafdf24 | ths | *
|
4 | 5391d806 | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | 201a51fc | balrog | * Copyright (c) 2006 Openedhand Ltd.
|
6 | 5fafdf24 | ths | *
|
7 | 5391d806 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | 5391d806 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
9 | 5391d806 | bellard | * in the Software without restriction, including without limitation the rights
|
10 | 5391d806 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | 5391d806 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
12 | 5391d806 | bellard | * furnished to do so, subject to the following conditions:
|
13 | 5391d806 | bellard | *
|
14 | 5391d806 | bellard | * The above copyright notice and this permission notice shall be included in
|
15 | 5391d806 | bellard | * all copies or substantial portions of the Software.
|
16 | 5391d806 | bellard | *
|
17 | 5391d806 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | 5391d806 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | 5391d806 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | 5391d806 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | 5391d806 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | 5391d806 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | 5391d806 | bellard | * THE SOFTWARE.
|
24 | 5391d806 | bellard | */
|
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 87ecb68b | pbrook | #include "scsi-disk.h" |
29 | 87ecb68b | pbrook | #include "pcmcia.h" |
30 | 87ecb68b | pbrook | #include "block.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 9596ebb7 | pbrook | #include "ppc_mac.h" |
34 | 5391d806 | bellard | |
35 | 5391d806 | bellard | /* debug IDE devices */
|
36 | 5391d806 | bellard | //#define DEBUG_IDE
|
37 | 5391d806 | bellard | //#define DEBUG_IDE_ATAPI
|
38 | 8ccad811 | bellard | //#define DEBUG_AIO
|
39 | 8ccad811 | bellard | #define USE_DMA_CDROM
|
40 | 5391d806 | bellard | |
41 | 5391d806 | bellard | /* Bits of HD_STATUS */
|
42 | 5391d806 | bellard | #define ERR_STAT 0x01 |
43 | 5391d806 | bellard | #define INDEX_STAT 0x02 |
44 | 5391d806 | bellard | #define ECC_STAT 0x04 /* Corrected error */ |
45 | 5391d806 | bellard | #define DRQ_STAT 0x08 |
46 | 5391d806 | bellard | #define SEEK_STAT 0x10 |
47 | 5391d806 | bellard | #define SRV_STAT 0x10 |
48 | 5391d806 | bellard | #define WRERR_STAT 0x20 |
49 | 5391d806 | bellard | #define READY_STAT 0x40 |
50 | 5391d806 | bellard | #define BUSY_STAT 0x80 |
51 | 5391d806 | bellard | |
52 | 5391d806 | bellard | /* Bits for HD_ERROR */
|
53 | 5391d806 | bellard | #define MARK_ERR 0x01 /* Bad address mark */ |
54 | 5391d806 | bellard | #define TRK0_ERR 0x02 /* couldn't find track 0 */ |
55 | 5391d806 | bellard | #define ABRT_ERR 0x04 /* Command aborted */ |
56 | 5391d806 | bellard | #define MCR_ERR 0x08 /* media change request */ |
57 | 5391d806 | bellard | #define ID_ERR 0x10 /* ID field not found */ |
58 | 5391d806 | bellard | #define MC_ERR 0x20 /* media changed */ |
59 | 5391d806 | bellard | #define ECC_ERR 0x40 /* Uncorrectable ECC error */ |
60 | 5391d806 | bellard | #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */ |
61 | 5391d806 | bellard | #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */ |
62 | 5391d806 | bellard | |
63 | 5391d806 | bellard | /* Bits of HD_NSECTOR */
|
64 | 5391d806 | bellard | #define CD 0x01 |
65 | 5391d806 | bellard | #define IO 0x02 |
66 | 5391d806 | bellard | #define REL 0x04 |
67 | 5391d806 | bellard | #define TAG_MASK 0xf8 |
68 | 5391d806 | bellard | |
69 | 5391d806 | bellard | #define IDE_CMD_RESET 0x04 |
70 | 5391d806 | bellard | #define IDE_CMD_DISABLE_IRQ 0x02 |
71 | 5391d806 | bellard | |
72 | 5391d806 | bellard | /* ATA/ATAPI Commands pre T13 Spec */
|
73 | 5391d806 | bellard | #define WIN_NOP 0x00 |
74 | 5391d806 | bellard | /*
|
75 | 5391d806 | bellard | * 0x01->0x02 Reserved
|
76 | 5391d806 | bellard | */
|
77 | 5391d806 | bellard | #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */ |
78 | 5391d806 | bellard | /*
|
79 | 5391d806 | bellard | * 0x04->0x07 Reserved
|
80 | 5391d806 | bellard | */
|
81 | 5391d806 | bellard | #define WIN_SRST 0x08 /* ATAPI soft reset command */ |
82 | 5391d806 | bellard | #define WIN_DEVICE_RESET 0x08 |
83 | 5391d806 | bellard | /*
|
84 | 5391d806 | bellard | * 0x09->0x0F Reserved
|
85 | 5391d806 | bellard | */
|
86 | 5391d806 | bellard | #define WIN_RECAL 0x10 |
87 | 5391d806 | bellard | #define WIN_RESTORE WIN_RECAL
|
88 | 5391d806 | bellard | /*
|
89 | 5391d806 | bellard | * 0x10->0x1F Reserved
|
90 | 5391d806 | bellard | */
|
91 | 5391d806 | bellard | #define WIN_READ 0x20 /* 28-Bit */ |
92 | 5391d806 | bellard | #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */ |
93 | 5391d806 | bellard | #define WIN_READ_LONG 0x22 /* 28-Bit */ |
94 | 5391d806 | bellard | #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */ |
95 | 5391d806 | bellard | #define WIN_READ_EXT 0x24 /* 48-Bit */ |
96 | 5391d806 | bellard | #define WIN_READDMA_EXT 0x25 /* 48-Bit */ |
97 | 5391d806 | bellard | #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */ |
98 | 5391d806 | bellard | #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */ |
99 | 5391d806 | bellard | /*
|
100 | 5391d806 | bellard | * 0x28
|
101 | 5391d806 | bellard | */
|
102 | 5391d806 | bellard | #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */ |
103 | 5391d806 | bellard | /*
|
104 | 5391d806 | bellard | * 0x2A->0x2F Reserved
|
105 | 5391d806 | bellard | */
|
106 | 5391d806 | bellard | #define WIN_WRITE 0x30 /* 28-Bit */ |
107 | 5391d806 | bellard | #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */ |
108 | 5391d806 | bellard | #define WIN_WRITE_LONG 0x32 /* 28-Bit */ |
109 | 5391d806 | bellard | #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */ |
110 | 5391d806 | bellard | #define WIN_WRITE_EXT 0x34 /* 48-Bit */ |
111 | 5391d806 | bellard | #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */ |
112 | 5391d806 | bellard | #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */ |
113 | 5391d806 | bellard | #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */ |
114 | 5391d806 | bellard | #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */ |
115 | 5391d806 | bellard | #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */ |
116 | 5391d806 | bellard | /*
|
117 | 5391d806 | bellard | * 0x3A->0x3B Reserved
|
118 | 5391d806 | bellard | */
|
119 | 5391d806 | bellard | #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */ |
120 | 5391d806 | bellard | /*
|
121 | 5391d806 | bellard | * 0x3D->0x3F Reserved
|
122 | 5391d806 | bellard | */
|
123 | 5391d806 | bellard | #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */ |
124 | 5391d806 | bellard | #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */ |
125 | 5391d806 | bellard | #define WIN_VERIFY_EXT 0x42 /* 48-Bit */ |
126 | 5391d806 | bellard | /*
|
127 | 5391d806 | bellard | * 0x43->0x4F Reserved
|
128 | 5391d806 | bellard | */
|
129 | 5391d806 | bellard | #define WIN_FORMAT 0x50 |
130 | 5391d806 | bellard | /*
|
131 | 5391d806 | bellard | * 0x51->0x5F Reserved
|
132 | 5391d806 | bellard | */
|
133 | 5391d806 | bellard | #define WIN_INIT 0x60 |
134 | 5391d806 | bellard | /*
|
135 | 5391d806 | bellard | * 0x61->0x5F Reserved
|
136 | 5391d806 | bellard | */
|
137 | 5391d806 | bellard | #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */ |
138 | 5391d806 | bellard | #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */ |
139 | 5391d806 | bellard | #define WIN_DIAGNOSE 0x90 |
140 | 5391d806 | bellard | #define WIN_SPECIFY 0x91 /* set drive geometry translation */ |
141 | 5391d806 | bellard | #define WIN_DOWNLOAD_MICROCODE 0x92 |
142 | 5391d806 | bellard | #define WIN_STANDBYNOW2 0x94 |
143 | 201a51fc | balrog | #define CFA_IDLEIMMEDIATE 0x95 /* force drive to become "ready" */ |
144 | 5391d806 | bellard | #define WIN_STANDBY2 0x96 |
145 | 5391d806 | bellard | #define WIN_SETIDLE2 0x97 |
146 | 5391d806 | bellard | #define WIN_CHECKPOWERMODE2 0x98 |
147 | 5391d806 | bellard | #define WIN_SLEEPNOW2 0x99 |
148 | 5391d806 | bellard | /*
|
149 | 5391d806 | bellard | * 0x9A VENDOR
|
150 | 5391d806 | bellard | */
|
151 | 5391d806 | bellard | #define WIN_PACKETCMD 0xA0 /* Send a packet command. */ |
152 | 5391d806 | bellard | #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */ |
153 | 5391d806 | bellard | #define WIN_QUEUED_SERVICE 0xA2 |
154 | 5391d806 | bellard | #define WIN_SMART 0xB0 /* self-monitoring and reporting */ |
155 | 201a51fc | balrog | #define CFA_ACCESS_METADATA_STORAGE 0xB8 |
156 | 201a51fc | balrog | #define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */ |
157 | 5391d806 | bellard | #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/ |
158 | 5391d806 | bellard | #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */ |
159 | 5391d806 | bellard | #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */ |
160 | 5391d806 | bellard | #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */ |
161 | 5391d806 | bellard | #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */ |
162 | 5391d806 | bellard | #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */ |
163 | 5391d806 | bellard | #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */ |
164 | 5391d806 | bellard | #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */ |
165 | 5391d806 | bellard | #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */ |
166 | 5391d806 | bellard | #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */ |
167 | 5fafdf24 | ths | #define WIN_GETMEDIASTATUS 0xDA |
168 | 5391d806 | bellard | #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */ |
169 | 5391d806 | bellard | #define WIN_POSTBOOT 0xDC |
170 | 5391d806 | bellard | #define WIN_PREBOOT 0xDD |
171 | 5391d806 | bellard | #define WIN_DOORLOCK 0xDE /* lock door on removable drives */ |
172 | 5391d806 | bellard | #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */ |
173 | 5391d806 | bellard | #define WIN_STANDBYNOW1 0xE0 |
174 | 5391d806 | bellard | #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */ |
175 | 5391d806 | bellard | #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */ |
176 | 5391d806 | bellard | #define WIN_SETIDLE1 0xE3 |
177 | 5391d806 | bellard | #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */ |
178 | 5391d806 | bellard | #define WIN_CHECKPOWERMODE1 0xE5 |
179 | 5391d806 | bellard | #define WIN_SLEEPNOW1 0xE6 |
180 | 5391d806 | bellard | #define WIN_FLUSH_CACHE 0xE7 |
181 | 5391d806 | bellard | #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */ |
182 | 5391d806 | bellard | #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */ |
183 | 5391d806 | bellard | /* SET_FEATURES 0x22 or 0xDD */
|
184 | 5391d806 | bellard | #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */ |
185 | 5391d806 | bellard | #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */ |
186 | 5391d806 | bellard | #define WIN_MEDIAEJECT 0xED |
187 | 5391d806 | bellard | #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */ |
188 | 5391d806 | bellard | #define WIN_SETFEATURES 0xEF /* set special drive features */ |
189 | 5391d806 | bellard | #define EXABYTE_ENABLE_NEST 0xF0 |
190 | 201a51fc | balrog | #define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature */ |
191 | 5391d806 | bellard | #define WIN_SECURITY_SET_PASS 0xF1 |
192 | 5391d806 | bellard | #define WIN_SECURITY_UNLOCK 0xF2 |
193 | 5391d806 | bellard | #define WIN_SECURITY_ERASE_PREPARE 0xF3 |
194 | 5391d806 | bellard | #define WIN_SECURITY_ERASE_UNIT 0xF4 |
195 | 5391d806 | bellard | #define WIN_SECURITY_FREEZE_LOCK 0xF5 |
196 | 201a51fc | balrog | #define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP */ |
197 | 5391d806 | bellard | #define WIN_SECURITY_DISABLE 0xF6 |
198 | 5391d806 | bellard | #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */ |
199 | 5391d806 | bellard | #define WIN_SET_MAX 0xF9 |
200 | 5391d806 | bellard | #define DISABLE_SEAGATE 0xFB |
201 | 5391d806 | bellard | |
202 | 5391d806 | bellard | /* set to 1 set disable mult support */
|
203 | f66723fa | bellard | #define MAX_MULT_SECTORS 16 |
204 | 5391d806 | bellard | |
205 | 1d8cde5b | aurel32 | #define IDE_DMA_BUF_SECTORS 256 |
206 | 1d8cde5b | aurel32 | |
207 | 1d8cde5b | aurel32 | #if (IDE_DMA_BUF_SECTORS < MAX_MULT_SECTORS)
|
208 | 1d8cde5b | aurel32 | #error "IDE_DMA_BUF_SECTORS must be bigger or equal to MAX_MULT_SECTORS" |
209 | 1d8cde5b | aurel32 | #endif
|
210 | 1d8cde5b | aurel32 | |
211 | 5391d806 | bellard | /* ATAPI defines */
|
212 | 5391d806 | bellard | |
213 | 5391d806 | bellard | #define ATAPI_PACKET_SIZE 12 |
214 | 5391d806 | bellard | |
215 | 5391d806 | bellard | /* The generic packet command opcodes for CD/DVD Logical Units,
|
216 | 5391d806 | bellard | * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
|
217 | 5391d806 | bellard | #define GPCMD_BLANK 0xa1 |
218 | 5391d806 | bellard | #define GPCMD_CLOSE_TRACK 0x5b |
219 | 5391d806 | bellard | #define GPCMD_FLUSH_CACHE 0x35 |
220 | 5391d806 | bellard | #define GPCMD_FORMAT_UNIT 0x04 |
221 | 5391d806 | bellard | #define GPCMD_GET_CONFIGURATION 0x46 |
222 | 5391d806 | bellard | #define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a |
223 | 5391d806 | bellard | #define GPCMD_GET_PERFORMANCE 0xac |
224 | 5391d806 | bellard | #define GPCMD_INQUIRY 0x12 |
225 | 5391d806 | bellard | #define GPCMD_LOAD_UNLOAD 0xa6 |
226 | 5391d806 | bellard | #define GPCMD_MECHANISM_STATUS 0xbd |
227 | 5391d806 | bellard | #define GPCMD_MODE_SELECT_10 0x55 |
228 | 5391d806 | bellard | #define GPCMD_MODE_SENSE_10 0x5a |
229 | 5391d806 | bellard | #define GPCMD_PAUSE_RESUME 0x4b |
230 | 5391d806 | bellard | #define GPCMD_PLAY_AUDIO_10 0x45 |
231 | 5391d806 | bellard | #define GPCMD_PLAY_AUDIO_MSF 0x47 |
232 | 5391d806 | bellard | #define GPCMD_PLAY_AUDIO_TI 0x48 |
233 | 5391d806 | bellard | #define GPCMD_PLAY_CD 0xbc |
234 | 5391d806 | bellard | #define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e |
235 | 5391d806 | bellard | #define GPCMD_READ_10 0x28 |
236 | 5391d806 | bellard | #define GPCMD_READ_12 0xa8 |
237 | 5391d806 | bellard | #define GPCMD_READ_CDVD_CAPACITY 0x25 |
238 | 5391d806 | bellard | #define GPCMD_READ_CD 0xbe |
239 | 5391d806 | bellard | #define GPCMD_READ_CD_MSF 0xb9 |
240 | 5391d806 | bellard | #define GPCMD_READ_DISC_INFO 0x51 |
241 | 5391d806 | bellard | #define GPCMD_READ_DVD_STRUCTURE 0xad |
242 | 5391d806 | bellard | #define GPCMD_READ_FORMAT_CAPACITIES 0x23 |
243 | 5391d806 | bellard | #define GPCMD_READ_HEADER 0x44 |
244 | 5391d806 | bellard | #define GPCMD_READ_TRACK_RZONE_INFO 0x52 |
245 | 5391d806 | bellard | #define GPCMD_READ_SUBCHANNEL 0x42 |
246 | 5391d806 | bellard | #define GPCMD_READ_TOC_PMA_ATIP 0x43 |
247 | 5391d806 | bellard | #define GPCMD_REPAIR_RZONE_TRACK 0x58 |
248 | 5391d806 | bellard | #define GPCMD_REPORT_KEY 0xa4 |
249 | 5391d806 | bellard | #define GPCMD_REQUEST_SENSE 0x03 |
250 | 5391d806 | bellard | #define GPCMD_RESERVE_RZONE_TRACK 0x53 |
251 | 5391d806 | bellard | #define GPCMD_SCAN 0xba |
252 | 5391d806 | bellard | #define GPCMD_SEEK 0x2b |
253 | 5391d806 | bellard | #define GPCMD_SEND_DVD_STRUCTURE 0xad |
254 | 5391d806 | bellard | #define GPCMD_SEND_EVENT 0xa2 |
255 | 5391d806 | bellard | #define GPCMD_SEND_KEY 0xa3 |
256 | 5391d806 | bellard | #define GPCMD_SEND_OPC 0x54 |
257 | 5391d806 | bellard | #define GPCMD_SET_READ_AHEAD 0xa7 |
258 | 5391d806 | bellard | #define GPCMD_SET_STREAMING 0xb6 |
259 | 5391d806 | bellard | #define GPCMD_START_STOP_UNIT 0x1b |
260 | 5391d806 | bellard | #define GPCMD_STOP_PLAY_SCAN 0x4e |
261 | 5391d806 | bellard | #define GPCMD_TEST_UNIT_READY 0x00 |
262 | 5391d806 | bellard | #define GPCMD_VERIFY_10 0x2f |
263 | 5391d806 | bellard | #define GPCMD_WRITE_10 0x2a |
264 | 5391d806 | bellard | #define GPCMD_WRITE_AND_VERIFY_10 0x2e |
265 | 5fafdf24 | ths | /* This is listed as optional in ATAPI 2.6, but is (curiously)
|
266 | 5391d806 | bellard | * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
|
267 | 5391d806 | bellard | * Table 377 as an MMC command for SCSi devices though... Most ATAPI
|
268 | 5391d806 | bellard | * drives support it. */
|
269 | 5391d806 | bellard | #define GPCMD_SET_SPEED 0xbb |
270 | 5fafdf24 | ths | /* This seems to be a SCSI specific CD-ROM opcode
|
271 | 5391d806 | bellard | * to play data at track/index */
|
272 | 5391d806 | bellard | #define GPCMD_PLAYAUDIO_TI 0x48 |
273 | 5391d806 | bellard | /*
|
274 | 5391d806 | bellard | * From MS Media Status Notification Support Specification. For
|
275 | 5391d806 | bellard | * older drives only.
|
276 | 5391d806 | bellard | */
|
277 | 5391d806 | bellard | #define GPCMD_GET_MEDIA_STATUS 0xda |
278 | d14049ea | ths | #define GPCMD_MODE_SENSE_6 0x1a |
279 | 5391d806 | bellard | |
280 | 5391d806 | bellard | /* Mode page codes for mode sense/set */
|
281 | 5391d806 | bellard | #define GPMODE_R_W_ERROR_PAGE 0x01 |
282 | 5391d806 | bellard | #define GPMODE_WRITE_PARMS_PAGE 0x05 |
283 | 5391d806 | bellard | #define GPMODE_AUDIO_CTL_PAGE 0x0e |
284 | 5391d806 | bellard | #define GPMODE_POWER_PAGE 0x1a |
285 | 5391d806 | bellard | #define GPMODE_FAULT_FAIL_PAGE 0x1c |
286 | 5391d806 | bellard | #define GPMODE_TO_PROTECT_PAGE 0x1d |
287 | 5391d806 | bellard | #define GPMODE_CAPABILITIES_PAGE 0x2a |
288 | 5391d806 | bellard | #define GPMODE_ALL_PAGES 0x3f |
289 | 5391d806 | bellard | /* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
|
290 | 5391d806 | bellard | * of MODE_SENSE_POWER_PAGE */
|
291 | 5391d806 | bellard | #define GPMODE_CDROM_PAGE 0x0d |
292 | 5391d806 | bellard | |
293 | 38cdea7c | balrog | /*
|
294 | 38cdea7c | balrog | * Based on values from <linux/cdrom.h> but extending CD_MINS
|
295 | 38cdea7c | balrog | * to the maximum common size allowed by the Orange's Book ATIP
|
296 | 38cdea7c | balrog | *
|
297 | 38cdea7c | balrog | * 90 and 99 min CDs are also available but using them as the
|
298 | 38cdea7c | balrog | * upper limit reduces the effectiveness of the heuristic to
|
299 | 38cdea7c | balrog | * detect DVDs burned to less than 25% of their maximum capacity
|
300 | 38cdea7c | balrog | */
|
301 | 38cdea7c | balrog | |
302 | 38cdea7c | balrog | /* Some generally useful CD-ROM information */
|
303 | 38cdea7c | balrog | #define CD_MINS 80 /* max. minutes per CD */ |
304 | 38cdea7c | balrog | #define CD_SECS 60 /* seconds per minute */ |
305 | 38cdea7c | balrog | #define CD_FRAMES 75 /* frames per second */ |
306 | 38cdea7c | balrog | #define CD_FRAMESIZE 2048 /* bytes per frame, "cooked" mode */ |
307 | 38cdea7c | balrog | #define CD_MAX_BYTES (CD_MINS * CD_SECS * CD_FRAMES * CD_FRAMESIZE)
|
308 | 38cdea7c | balrog | #define CD_MAX_SECTORS (CD_MAX_BYTES / 512) |
309 | 38cdea7c | balrog | |
310 | 38cdea7c | balrog | /*
|
311 | 38cdea7c | balrog | * The MMC values are not IDE specific and might need to be moved
|
312 | 38cdea7c | balrog | * to a common header if they are also needed for the SCSI emulation
|
313 | 38cdea7c | balrog | */
|
314 | 38cdea7c | balrog | |
315 | 38cdea7c | balrog | /* Profile list from MMC-6 revision 1 table 91 */
|
316 | 38cdea7c | balrog | #define MMC_PROFILE_NONE 0x0000 |
317 | 38cdea7c | balrog | #define MMC_PROFILE_CD_ROM 0x0008 |
318 | 38cdea7c | balrog | #define MMC_PROFILE_CD_R 0x0009 |
319 | 38cdea7c | balrog | #define MMC_PROFILE_CD_RW 0x000A |
320 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_ROM 0x0010 |
321 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_R_SR 0x0011 |
322 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RAM 0x0012 |
323 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RW_RO 0x0013 |
324 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RW_SR 0x0014 |
325 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_R_DL_SR 0x0015 |
326 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_R_DL_JR 0x0016 |
327 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_RW_DL 0x0017 |
328 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_DDR 0x0018 |
329 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_RW 0x001A |
330 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_R 0x001B |
331 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_RW_DL 0x002A |
332 | 38cdea7c | balrog | #define MMC_PROFILE_DVD_PLUS_R_DL 0x002B |
333 | 38cdea7c | balrog | #define MMC_PROFILE_BD_ROM 0x0040 |
334 | 38cdea7c | balrog | #define MMC_PROFILE_BD_R_SRM 0x0041 |
335 | 38cdea7c | balrog | #define MMC_PROFILE_BD_R_RRM 0x0042 |
336 | 38cdea7c | balrog | #define MMC_PROFILE_BD_RE 0x0043 |
337 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_ROM 0x0050 |
338 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_R 0x0051 |
339 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_RAM 0x0052 |
340 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_RW 0x0053 |
341 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_R_DL 0x0058 |
342 | 38cdea7c | balrog | #define MMC_PROFILE_HDDVD_RW_DL 0x005A |
343 | 38cdea7c | balrog | #define MMC_PROFILE_INVALID 0xFFFF |
344 | 38cdea7c | balrog | |
345 | 5391d806 | bellard | #define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */ |
346 | 5391d806 | bellard | #define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */ |
347 | 5391d806 | bellard | #define ATAPI_INT_REASON_REL 0x04 |
348 | 5391d806 | bellard | #define ATAPI_INT_REASON_TAG 0xf8 |
349 | 5391d806 | bellard | |
350 | 5391d806 | bellard | /* same constants as bochs */
|
351 | 7f777bf3 | bellard | #define ASC_ILLEGAL_OPCODE 0x20 |
352 | 5391d806 | bellard | #define ASC_LOGICAL_BLOCK_OOR 0x21 |
353 | 5391d806 | bellard | #define ASC_INV_FIELD_IN_CMD_PACKET 0x24 |
354 | 5391d806 | bellard | #define ASC_MEDIUM_NOT_PRESENT 0x3a |
355 | 5391d806 | bellard | #define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39 |
356 | 5391d806 | bellard | |
357 | 201a51fc | balrog | #define CFA_NO_ERROR 0x00 |
358 | 201a51fc | balrog | #define CFA_MISC_ERROR 0x09 |
359 | 201a51fc | balrog | #define CFA_INVALID_COMMAND 0x20 |
360 | 201a51fc | balrog | #define CFA_INVALID_ADDRESS 0x21 |
361 | 201a51fc | balrog | #define CFA_ADDRESS_OVERFLOW 0x2f |
362 | 201a51fc | balrog | |
363 | 5391d806 | bellard | #define SENSE_NONE 0 |
364 | 5391d806 | bellard | #define SENSE_NOT_READY 2 |
365 | 5391d806 | bellard | #define SENSE_ILLEGAL_REQUEST 5 |
366 | 5391d806 | bellard | #define SENSE_UNIT_ATTENTION 6 |
367 | 5391d806 | bellard | |
368 | 5391d806 | bellard | struct IDEState;
|
369 | 5391d806 | bellard | |
370 | 5391d806 | bellard | typedef void EndTransferFunc(struct IDEState *); |
371 | 5391d806 | bellard | |
372 | caed8802 | bellard | /* NOTE: IDEState represents in fact one drive */
|
373 | 5391d806 | bellard | typedef struct IDEState { |
374 | 5391d806 | bellard | /* ide config */
|
375 | 5391d806 | bellard | int is_cdrom;
|
376 | 201a51fc | balrog | int is_cf;
|
377 | 5391d806 | bellard | int cylinders, heads, sectors;
|
378 | 5391d806 | bellard | int64_t nb_sectors; |
379 | 5391d806 | bellard | int mult_sectors;
|
380 | 94458802 | bellard | int identify_set;
|
381 | 94458802 | bellard | uint16_t identify_data[256];
|
382 | d537cf6c | pbrook | qemu_irq irq; |
383 | 34e538ae | bellard | PCIDevice *pci_dev; |
384 | 98087450 | bellard | struct BMDMAState *bmdma;
|
385 | aedf5382 | bellard | int drive_serial;
|
386 | 5391d806 | bellard | /* ide regs */
|
387 | 5391d806 | bellard | uint8_t feature; |
388 | 5391d806 | bellard | uint8_t error; |
389 | c2ff060f | bellard | uint32_t nsector; |
390 | 5391d806 | bellard | uint8_t sector; |
391 | 5391d806 | bellard | uint8_t lcyl; |
392 | 5391d806 | bellard | uint8_t hcyl; |
393 | c2ff060f | bellard | /* other part of tf for lba48 support */
|
394 | c2ff060f | bellard | uint8_t hob_feature; |
395 | c2ff060f | bellard | uint8_t hob_nsector; |
396 | c2ff060f | bellard | uint8_t hob_sector; |
397 | c2ff060f | bellard | uint8_t hob_lcyl; |
398 | c2ff060f | bellard | uint8_t hob_hcyl; |
399 | c2ff060f | bellard | |
400 | 5391d806 | bellard | uint8_t select; |
401 | 5391d806 | bellard | uint8_t status; |
402 | c2ff060f | bellard | |
403 | 5391d806 | bellard | /* 0x3f6 command, only meaningful for drive 0 */
|
404 | 5391d806 | bellard | uint8_t cmd; |
405 | c2ff060f | bellard | /* set for lba48 access */
|
406 | c2ff060f | bellard | uint8_t lba48; |
407 | 5391d806 | bellard | /* depends on bit 4 in select, only meaningful for drive 0 */
|
408 | 5fafdf24 | ths | struct IDEState *cur_drive;
|
409 | 5391d806 | bellard | BlockDriverState *bs; |
410 | 5391d806 | bellard | /* ATAPI specific */
|
411 | 5391d806 | bellard | uint8_t sense_key; |
412 | 5391d806 | bellard | uint8_t asc; |
413 | 5391d806 | bellard | int packet_transfer_size;
|
414 | 5391d806 | bellard | int elementary_transfer_size;
|
415 | 5391d806 | bellard | int io_buffer_index;
|
416 | 5391d806 | bellard | int lba;
|
417 | 98087450 | bellard | int cd_sector_size;
|
418 | 98087450 | bellard | int atapi_dma; /* true if dma is requested for the packet cmd */ |
419 | 98087450 | bellard | /* ATA DMA state */
|
420 | 98087450 | bellard | int io_buffer_size;
|
421 | 98087450 | bellard | /* PIO transfer handling */
|
422 | 5391d806 | bellard | int req_nb_sectors; /* number of sectors per interrupt */ |
423 | 5391d806 | bellard | EndTransferFunc *end_transfer_func; |
424 | 5391d806 | bellard | uint8_t *data_ptr; |
425 | 5391d806 | bellard | uint8_t *data_end; |
426 | 33f00271 | balrog | uint8_t *io_buffer; |
427 | 31c2a146 | ths | QEMUTimer *sector_write_timer; /* only used for win2k install hack */
|
428 | e774a278 | bellard | uint32_t irq_count; /* counts IRQs when using win2k install hack */
|
429 | 201a51fc | balrog | /* CF-ATA extended error */
|
430 | 201a51fc | balrog | uint8_t ext_error; |
431 | 201a51fc | balrog | /* CF-ATA metadata storage */
|
432 | 201a51fc | balrog | uint32_t mdata_size; |
433 | 201a51fc | balrog | uint8_t *mdata_storage; |
434 | 201a51fc | balrog | int media_changed;
|
435 | 5391d806 | bellard | } IDEState; |
436 | 5391d806 | bellard | |
437 | 98087450 | bellard | #define BM_STATUS_DMAING 0x01 |
438 | 98087450 | bellard | #define BM_STATUS_ERROR 0x02 |
439 | 98087450 | bellard | #define BM_STATUS_INT 0x04 |
440 | 98087450 | bellard | |
441 | 98087450 | bellard | #define BM_CMD_START 0x01 |
442 | 98087450 | bellard | #define BM_CMD_READ 0x08 |
443 | 98087450 | bellard | |
444 | 5457c8ce | bellard | #define IDE_TYPE_PIIX3 0 |
445 | 5457c8ce | bellard | #define IDE_TYPE_CMD646 1 |
446 | afcc3cdf | ths | #define IDE_TYPE_PIIX4 2 |
447 | 5457c8ce | bellard | |
448 | 5457c8ce | bellard | /* CMD646 specific */
|
449 | 5457c8ce | bellard | #define MRDMODE 0x71 |
450 | 5457c8ce | bellard | #define MRDMODE_INTR_CH0 0x04 |
451 | 5457c8ce | bellard | #define MRDMODE_INTR_CH1 0x08 |
452 | 5457c8ce | bellard | #define MRDMODE_BLK_CH0 0x10 |
453 | 5457c8ce | bellard | #define MRDMODE_BLK_CH1 0x20 |
454 | 5457c8ce | bellard | #define UDIDETCR0 0x73 |
455 | 5457c8ce | bellard | #define UDIDETCR1 0x7B |
456 | 5457c8ce | bellard | |
457 | 98087450 | bellard | typedef struct BMDMAState { |
458 | 98087450 | bellard | uint8_t cmd; |
459 | 98087450 | bellard | uint8_t status; |
460 | 98087450 | bellard | uint32_t addr; |
461 | 3b46e624 | ths | |
462 | 5457c8ce | bellard | struct PCIIDEState *pci_dev;
|
463 | 98087450 | bellard | /* current transfer state */
|
464 | 8ccad811 | bellard | uint32_t cur_addr; |
465 | 8ccad811 | bellard | uint32_t cur_prd_last; |
466 | 8ccad811 | bellard | uint32_t cur_prd_addr; |
467 | 8ccad811 | bellard | uint32_t cur_prd_len; |
468 | 98087450 | bellard | IDEState *ide_if; |
469 | 8ccad811 | bellard | BlockDriverCompletionFunc *dma_cb; |
470 | 8ccad811 | bellard | BlockDriverAIOCB *aiocb; |
471 | 98087450 | bellard | } BMDMAState; |
472 | 98087450 | bellard | |
473 | 98087450 | bellard | typedef struct PCIIDEState { |
474 | 98087450 | bellard | PCIDevice dev; |
475 | 98087450 | bellard | IDEState ide_if[4];
|
476 | 98087450 | bellard | BMDMAState bmdma[2];
|
477 | 5457c8ce | bellard | int type; /* see IDE_TYPE_xxx */ |
478 | 98087450 | bellard | } PCIIDEState; |
479 | 98087450 | bellard | |
480 | 8ccad811 | bellard | static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb); |
481 | 5f12ab4b | ths | static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret); |
482 | 98087450 | bellard | |
483 | 5391d806 | bellard | static void padstr(char *str, const char *src, int len) |
484 | 5391d806 | bellard | { |
485 | 5391d806 | bellard | int i, v;
|
486 | 5391d806 | bellard | for(i = 0; i < len; i++) { |
487 | 5391d806 | bellard | if (*src)
|
488 | 5391d806 | bellard | v = *src++; |
489 | 5391d806 | bellard | else
|
490 | 5391d806 | bellard | v = ' ';
|
491 | 69b34976 | ths | str[i^1] = v;
|
492 | 5391d806 | bellard | } |
493 | 5391d806 | bellard | } |
494 | 5391d806 | bellard | |
495 | bd0d90b2 | bellard | static void padstr8(uint8_t *buf, int buf_size, const char *src) |
496 | bd0d90b2 | bellard | { |
497 | bd0d90b2 | bellard | int i;
|
498 | bd0d90b2 | bellard | for(i = 0; i < buf_size; i++) { |
499 | bd0d90b2 | bellard | if (*src)
|
500 | bd0d90b2 | bellard | buf[i] = *src++; |
501 | bd0d90b2 | bellard | else
|
502 | bd0d90b2 | bellard | buf[i] = ' ';
|
503 | bd0d90b2 | bellard | } |
504 | bd0d90b2 | bellard | } |
505 | bd0d90b2 | bellard | |
506 | 67b915a5 | bellard | static void put_le16(uint16_t *p, unsigned int v) |
507 | 67b915a5 | bellard | { |
508 | 0c4ad8dc | bellard | *p = cpu_to_le16(v); |
509 | 67b915a5 | bellard | } |
510 | 67b915a5 | bellard | |
511 | 5391d806 | bellard | static void ide_identify(IDEState *s) |
512 | 5391d806 | bellard | { |
513 | 5391d806 | bellard | uint16_t *p; |
514 | 5391d806 | bellard | unsigned int oldsize; |
515 | aedf5382 | bellard | char buf[20]; |
516 | 5391d806 | bellard | |
517 | 94458802 | bellard | if (s->identify_set) {
|
518 | 94458802 | bellard | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
|
519 | 94458802 | bellard | return;
|
520 | 94458802 | bellard | } |
521 | 94458802 | bellard | |
522 | 5391d806 | bellard | memset(s->io_buffer, 0, 512); |
523 | 5391d806 | bellard | p = (uint16_t *)s->io_buffer; |
524 | 67b915a5 | bellard | put_le16(p + 0, 0x0040); |
525 | 5fafdf24 | ths | put_le16(p + 1, s->cylinders);
|
526 | 67b915a5 | bellard | put_le16(p + 3, s->heads);
|
527 | 67b915a5 | bellard | put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */ |
528 | 67b915a5 | bellard | put_le16(p + 5, 512); /* XXX: retired, remove ? */ |
529 | 5fafdf24 | ths | put_le16(p + 6, s->sectors);
|
530 | aedf5382 | bellard | snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial); |
531 | 60fe76f3 | ths | padstr((char *)(p + 10), buf, 20); /* serial number */ |
532 | 67b915a5 | bellard | put_le16(p + 20, 3); /* XXX: retired, remove ? */ |
533 | 67b915a5 | bellard | put_le16(p + 21, 512); /* cache size in sectors */ |
534 | 67b915a5 | bellard | put_le16(p + 22, 4); /* ecc bytes */ |
535 | 60fe76f3 | ths | padstr((char *)(p + 23), QEMU_VERSION, 8); /* firmware version */ |
536 | 60fe76f3 | ths | padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */ |
537 | 3b46e624 | ths | #if MAX_MULT_SECTORS > 1 |
538 | 67b915a5 | bellard | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
539 | 5391d806 | bellard | #endif
|
540 | 67b915a5 | bellard | put_le16(p + 48, 1); /* dword I/O */ |
541 | 94458802 | bellard | put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */ |
542 | 67b915a5 | bellard | put_le16(p + 51, 0x200); /* PIO transfer cycle */ |
543 | 67b915a5 | bellard | put_le16(p + 52, 0x200); /* DMA transfer cycle */ |
544 | 94458802 | bellard | put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */ |
545 | 67b915a5 | bellard | put_le16(p + 54, s->cylinders);
|
546 | 67b915a5 | bellard | put_le16(p + 55, s->heads);
|
547 | 67b915a5 | bellard | put_le16(p + 56, s->sectors);
|
548 | 5391d806 | bellard | oldsize = s->cylinders * s->heads * s->sectors; |
549 | 67b915a5 | bellard | put_le16(p + 57, oldsize);
|
550 | 67b915a5 | bellard | put_le16(p + 58, oldsize >> 16); |
551 | 5391d806 | bellard | if (s->mult_sectors)
|
552 | 67b915a5 | bellard | put_le16(p + 59, 0x100 | s->mult_sectors); |
553 | 67b915a5 | bellard | put_le16(p + 60, s->nb_sectors);
|
554 | 67b915a5 | bellard | put_le16(p + 61, s->nb_sectors >> 16); |
555 | 94458802 | bellard | put_le16(p + 63, 0x07); /* mdma0-2 supported */ |
556 | 94458802 | bellard | put_le16(p + 65, 120); |
557 | 94458802 | bellard | put_le16(p + 66, 120); |
558 | 94458802 | bellard | put_le16(p + 67, 120); |
559 | 94458802 | bellard | put_le16(p + 68, 120); |
560 | 94458802 | bellard | put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ |
561 | 94458802 | bellard | put_le16(p + 81, 0x16); /* conforms to ata5 */ |
562 | 67b915a5 | bellard | put_le16(p + 82, (1 << 14)); |
563 | c2ff060f | bellard | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
|
564 | c2ff060f | bellard | put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); |
565 | 67b915a5 | bellard | put_le16(p + 84, (1 << 14)); |
566 | 67b915a5 | bellard | put_le16(p + 85, (1 << 14)); |
567 | c2ff060f | bellard | /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
|
568 | c2ff060f | bellard | put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); |
569 | 67b915a5 | bellard | put_le16(p + 87, (1 << 14)); |
570 | 94458802 | bellard | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
571 | 94458802 | bellard | put_le16(p + 93, 1 | (1 << 14) | 0x2000); |
572 | c2ff060f | bellard | put_le16(p + 100, s->nb_sectors);
|
573 | c2ff060f | bellard | put_le16(p + 101, s->nb_sectors >> 16); |
574 | c2ff060f | bellard | put_le16(p + 102, s->nb_sectors >> 32); |
575 | c2ff060f | bellard | put_le16(p + 103, s->nb_sectors >> 48); |
576 | 94458802 | bellard | |
577 | 94458802 | bellard | memcpy(s->identify_data, p, sizeof(s->identify_data));
|
578 | 94458802 | bellard | s->identify_set = 1;
|
579 | 5391d806 | bellard | } |
580 | 5391d806 | bellard | |
581 | 5391d806 | bellard | static void ide_atapi_identify(IDEState *s) |
582 | 5391d806 | bellard | { |
583 | 5391d806 | bellard | uint16_t *p; |
584 | aedf5382 | bellard | char buf[20]; |
585 | 5391d806 | bellard | |
586 | 94458802 | bellard | if (s->identify_set) {
|
587 | 94458802 | bellard | memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
|
588 | 94458802 | bellard | return;
|
589 | 94458802 | bellard | } |
590 | 94458802 | bellard | |
591 | 5391d806 | bellard | memset(s->io_buffer, 0, 512); |
592 | 5391d806 | bellard | p = (uint16_t *)s->io_buffer; |
593 | 5391d806 | bellard | /* Removable CDROM, 50us response, 12 byte packets */
|
594 | 67b915a5 | bellard | put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0)); |
595 | aedf5382 | bellard | snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial); |
596 | 60fe76f3 | ths | padstr((char *)(p + 10), buf, 20); /* serial number */ |
597 | 67b915a5 | bellard | put_le16(p + 20, 3); /* buffer type */ |
598 | 67b915a5 | bellard | put_le16(p + 21, 512); /* cache size in sectors */ |
599 | 67b915a5 | bellard | put_le16(p + 22, 4); /* ecc bytes */ |
600 | 60fe76f3 | ths | padstr((char *)(p + 23), QEMU_VERSION, 8); /* firmware version */ |
601 | 38cdea7c | balrog | padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */ |
602 | 67b915a5 | bellard | put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */ |
603 | 8ccad811 | bellard | #ifdef USE_DMA_CDROM
|
604 | 8ccad811 | bellard | put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */ |
605 | 8ccad811 | bellard | put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */ |
606 | 8ccad811 | bellard | put_le16(p + 63, 7); /* mdma0-2 supported */ |
607 | 8ccad811 | bellard | put_le16(p + 64, 0x3f); /* PIO modes supported */ |
608 | 8ccad811 | bellard | #else
|
609 | 67b915a5 | bellard | put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */ |
610 | 67b915a5 | bellard | put_le16(p + 53, 3); /* words 64-70, 54-58 valid */ |
611 | 67b915a5 | bellard | put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */ |
612 | 67b915a5 | bellard | put_le16(p + 64, 1); /* PIO modes */ |
613 | 8ccad811 | bellard | #endif
|
614 | 67b915a5 | bellard | put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */ |
615 | 67b915a5 | bellard | put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */ |
616 | 67b915a5 | bellard | put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */ |
617 | 67b915a5 | bellard | put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */ |
618 | 94458802 | bellard | |
619 | 67b915a5 | bellard | put_le16(p + 71, 30); /* in ns */ |
620 | 67b915a5 | bellard | put_le16(p + 72, 30); /* in ns */ |
621 | 5391d806 | bellard | |
622 | 67b915a5 | bellard | put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */ |
623 | 8ccad811 | bellard | #ifdef USE_DMA_CDROM
|
624 | 8ccad811 | bellard | put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */ |
625 | 8ccad811 | bellard | #endif
|
626 | 94458802 | bellard | memcpy(s->identify_data, p, sizeof(s->identify_data));
|
627 | 94458802 | bellard | s->identify_set = 1;
|
628 | 5391d806 | bellard | } |
629 | 5391d806 | bellard | |
630 | 201a51fc | balrog | static void ide_cfata_identify(IDEState *s) |
631 | 201a51fc | balrog | { |
632 | 201a51fc | balrog | uint16_t *p; |
633 | 201a51fc | balrog | uint32_t cur_sec; |
634 | 201a51fc | balrog | char buf[20]; |
635 | 201a51fc | balrog | |
636 | 201a51fc | balrog | p = (uint16_t *) s->identify_data; |
637 | 201a51fc | balrog | if (s->identify_set)
|
638 | 201a51fc | balrog | goto fill_buffer;
|
639 | 201a51fc | balrog | |
640 | 201a51fc | balrog | memset(p, 0, sizeof(s->identify_data)); |
641 | 201a51fc | balrog | |
642 | 201a51fc | balrog | cur_sec = s->cylinders * s->heads * s->sectors; |
643 | 201a51fc | balrog | |
644 | 201a51fc | balrog | put_le16(p + 0, 0x848a); /* CF Storage Card signature */ |
645 | 201a51fc | balrog | put_le16(p + 1, s->cylinders); /* Default cylinders */ |
646 | 201a51fc | balrog | put_le16(p + 3, s->heads); /* Default heads */ |
647 | 201a51fc | balrog | put_le16(p + 6, s->sectors); /* Default sectors per track */ |
648 | 201a51fc | balrog | put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */ |
649 | 201a51fc | balrog | put_le16(p + 8, s->nb_sectors); /* Sectors per card */ |
650 | 201a51fc | balrog | snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial); |
651 | 60fe76f3 | ths | padstr((char *)(p + 10), buf, 20); /* Serial number in ASCII */ |
652 | 201a51fc | balrog | put_le16(p + 22, 0x0004); /* ECC bytes */ |
653 | 60fe76f3 | ths | padstr((char *) (p + 23), QEMU_VERSION, 8); /* Firmware Revision */ |
654 | 60fe76f3 | ths | padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */ |
655 | 201a51fc | balrog | #if MAX_MULT_SECTORS > 1 |
656 | 201a51fc | balrog | put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS); |
657 | 201a51fc | balrog | #else
|
658 | 201a51fc | balrog | put_le16(p + 47, 0x0000); |
659 | 201a51fc | balrog | #endif
|
660 | 201a51fc | balrog | put_le16(p + 49, 0x0f00); /* Capabilities */ |
661 | 201a51fc | balrog | put_le16(p + 51, 0x0002); /* PIO cycle timing mode */ |
662 | 201a51fc | balrog | put_le16(p + 52, 0x0001); /* DMA cycle timing mode */ |
663 | 201a51fc | balrog | put_le16(p + 53, 0x0003); /* Translation params valid */ |
664 | 201a51fc | balrog | put_le16(p + 54, s->cylinders); /* Current cylinders */ |
665 | 201a51fc | balrog | put_le16(p + 55, s->heads); /* Current heads */ |
666 | 201a51fc | balrog | put_le16(p + 56, s->sectors); /* Current sectors */ |
667 | 201a51fc | balrog | put_le16(p + 57, cur_sec); /* Current capacity */ |
668 | 201a51fc | balrog | put_le16(p + 58, cur_sec >> 16); /* Current capacity */ |
669 | 201a51fc | balrog | if (s->mult_sectors) /* Multiple sector setting */ |
670 | 201a51fc | balrog | put_le16(p + 59, 0x100 | s->mult_sectors); |
671 | 201a51fc | balrog | put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */ |
672 | 201a51fc | balrog | put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */ |
673 | 201a51fc | balrog | put_le16(p + 63, 0x0203); /* Multiword DMA capability */ |
674 | 201a51fc | balrog | put_le16(p + 64, 0x0001); /* Flow Control PIO support */ |
675 | 201a51fc | balrog | put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */ |
676 | 201a51fc | balrog | put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */ |
677 | 201a51fc | balrog | put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */ |
678 | 201a51fc | balrog | put_le16(p + 82, 0x400c); /* Command Set supported */ |
679 | 201a51fc | balrog | put_le16(p + 83, 0x7068); /* Command Set supported */ |
680 | 201a51fc | balrog | put_le16(p + 84, 0x4000); /* Features supported */ |
681 | 201a51fc | balrog | put_le16(p + 85, 0x000c); /* Command Set enabled */ |
682 | 201a51fc | balrog | put_le16(p + 86, 0x7044); /* Command Set enabled */ |
683 | 201a51fc | balrog | put_le16(p + 87, 0x4000); /* Features enabled */ |
684 | 201a51fc | balrog | put_le16(p + 91, 0x4060); /* Current APM level */ |
685 | 201a51fc | balrog | put_le16(p + 129, 0x0002); /* Current features option */ |
686 | 201a51fc | balrog | put_le16(p + 130, 0x0005); /* Reassigned sectors */ |
687 | 201a51fc | balrog | put_le16(p + 131, 0x0001); /* Initial power mode */ |
688 | 201a51fc | balrog | put_le16(p + 132, 0x0000); /* User signature */ |
689 | 201a51fc | balrog | put_le16(p + 160, 0x8100); /* Power requirement */ |
690 | 201a51fc | balrog | put_le16(p + 161, 0x8001); /* CF command set */ |
691 | 201a51fc | balrog | |
692 | 201a51fc | balrog | s->identify_set = 1;
|
693 | 201a51fc | balrog | |
694 | 201a51fc | balrog | fill_buffer:
|
695 | 201a51fc | balrog | memcpy(s->io_buffer, p, sizeof(s->identify_data));
|
696 | 201a51fc | balrog | } |
697 | 201a51fc | balrog | |
698 | 5391d806 | bellard | static void ide_set_signature(IDEState *s) |
699 | 5391d806 | bellard | { |
700 | 5391d806 | bellard | s->select &= 0xf0; /* clear head */ |
701 | 5391d806 | bellard | /* put signature */
|
702 | 5391d806 | bellard | s->nsector = 1;
|
703 | 5391d806 | bellard | s->sector = 1;
|
704 | 5391d806 | bellard | if (s->is_cdrom) {
|
705 | 5391d806 | bellard | s->lcyl = 0x14;
|
706 | 5391d806 | bellard | s->hcyl = 0xeb;
|
707 | 5391d806 | bellard | } else if (s->bs) { |
708 | 5391d806 | bellard | s->lcyl = 0;
|
709 | 5391d806 | bellard | s->hcyl = 0;
|
710 | 5391d806 | bellard | } else {
|
711 | 5391d806 | bellard | s->lcyl = 0xff;
|
712 | 5391d806 | bellard | s->hcyl = 0xff;
|
713 | 5391d806 | bellard | } |
714 | 5391d806 | bellard | } |
715 | 5391d806 | bellard | |
716 | 5391d806 | bellard | static inline void ide_abort_command(IDEState *s) |
717 | 5391d806 | bellard | { |
718 | 5391d806 | bellard | s->status = READY_STAT | ERR_STAT; |
719 | 5391d806 | bellard | s->error = ABRT_ERR; |
720 | 5391d806 | bellard | } |
721 | 5391d806 | bellard | |
722 | 5391d806 | bellard | static inline void ide_set_irq(IDEState *s) |
723 | 5391d806 | bellard | { |
724 | 98ff7d30 | bellard | BMDMAState *bm = s->bmdma; |
725 | 5391d806 | bellard | if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
|
726 | 5457c8ce | bellard | if (bm) {
|
727 | 98ff7d30 | bellard | bm->status |= BM_STATUS_INT; |
728 | 5457c8ce | bellard | } |
729 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
730 | 5391d806 | bellard | } |
731 | 5391d806 | bellard | } |
732 | 5391d806 | bellard | |
733 | 5391d806 | bellard | /* prepare data transfer and tell what to do after */
|
734 | 5fafdf24 | ths | static void ide_transfer_start(IDEState *s, uint8_t *buf, int size, |
735 | 5391d806 | bellard | EndTransferFunc *end_transfer_func) |
736 | 5391d806 | bellard | { |
737 | 5391d806 | bellard | s->end_transfer_func = end_transfer_func; |
738 | 5391d806 | bellard | s->data_ptr = buf; |
739 | 5391d806 | bellard | s->data_end = buf + size; |
740 | 7603d156 | ths | if (!(s->status & ERR_STAT))
|
741 | 7603d156 | ths | s->status |= DRQ_STAT; |
742 | 5391d806 | bellard | } |
743 | 5391d806 | bellard | |
744 | 5391d806 | bellard | static void ide_transfer_stop(IDEState *s) |
745 | 5391d806 | bellard | { |
746 | 5391d806 | bellard | s->end_transfer_func = ide_transfer_stop; |
747 | 5391d806 | bellard | s->data_ptr = s->io_buffer; |
748 | 5391d806 | bellard | s->data_end = s->io_buffer; |
749 | 5391d806 | bellard | s->status &= ~DRQ_STAT; |
750 | 5391d806 | bellard | } |
751 | 5391d806 | bellard | |
752 | 5391d806 | bellard | static int64_t ide_get_sector(IDEState *s)
|
753 | 5391d806 | bellard | { |
754 | 5391d806 | bellard | int64_t sector_num; |
755 | 5391d806 | bellard | if (s->select & 0x40) { |
756 | 5391d806 | bellard | /* lba */
|
757 | c2ff060f | bellard | if (!s->lba48) {
|
758 | c2ff060f | bellard | sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | |
759 | c2ff060f | bellard | (s->lcyl << 8) | s->sector;
|
760 | c2ff060f | bellard | } else {
|
761 | c2ff060f | bellard | sector_num = ((int64_t)s->hob_hcyl << 40) |
|
762 | c2ff060f | bellard | ((int64_t) s->hob_lcyl << 32) |
|
763 | c2ff060f | bellard | ((int64_t) s->hob_sector << 24) |
|
764 | c2ff060f | bellard | ((int64_t) s->hcyl << 16) |
|
765 | c2ff060f | bellard | ((int64_t) s->lcyl << 8) | s->sector;
|
766 | c2ff060f | bellard | } |
767 | 5391d806 | bellard | } else {
|
768 | 5391d806 | bellard | sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
|
769 | c2ff060f | bellard | (s->select & 0x0f) * s->sectors + (s->sector - 1); |
770 | 5391d806 | bellard | } |
771 | 5391d806 | bellard | return sector_num;
|
772 | 5391d806 | bellard | } |
773 | 5391d806 | bellard | |
774 | 5391d806 | bellard | static void ide_set_sector(IDEState *s, int64_t sector_num) |
775 | 5391d806 | bellard | { |
776 | 5391d806 | bellard | unsigned int cyl, r; |
777 | 5391d806 | bellard | if (s->select & 0x40) { |
778 | c2ff060f | bellard | if (!s->lba48) {
|
779 | c2ff060f | bellard | s->select = (s->select & 0xf0) | (sector_num >> 24); |
780 | c2ff060f | bellard | s->hcyl = (sector_num >> 16);
|
781 | c2ff060f | bellard | s->lcyl = (sector_num >> 8);
|
782 | c2ff060f | bellard | s->sector = (sector_num); |
783 | c2ff060f | bellard | } else {
|
784 | c2ff060f | bellard | s->sector = sector_num; |
785 | c2ff060f | bellard | s->lcyl = sector_num >> 8;
|
786 | c2ff060f | bellard | s->hcyl = sector_num >> 16;
|
787 | c2ff060f | bellard | s->hob_sector = sector_num >> 24;
|
788 | c2ff060f | bellard | s->hob_lcyl = sector_num >> 32;
|
789 | c2ff060f | bellard | s->hob_hcyl = sector_num >> 40;
|
790 | c2ff060f | bellard | } |
791 | 5391d806 | bellard | } else {
|
792 | 5391d806 | bellard | cyl = sector_num / (s->heads * s->sectors); |
793 | 5391d806 | bellard | r = sector_num % (s->heads * s->sectors); |
794 | 5391d806 | bellard | s->hcyl = cyl >> 8;
|
795 | 5391d806 | bellard | s->lcyl = cyl; |
796 | 1b8eb456 | bellard | s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f); |
797 | 5391d806 | bellard | s->sector = (r % s->sectors) + 1;
|
798 | 5391d806 | bellard | } |
799 | 5391d806 | bellard | } |
800 | 5391d806 | bellard | |
801 | 5391d806 | bellard | static void ide_sector_read(IDEState *s) |
802 | 5391d806 | bellard | { |
803 | 5391d806 | bellard | int64_t sector_num; |
804 | 5391d806 | bellard | int ret, n;
|
805 | 5391d806 | bellard | |
806 | 5391d806 | bellard | s->status = READY_STAT | SEEK_STAT; |
807 | a136e5a8 | bellard | s->error = 0; /* not needed by IDE spec, but needed by Windows */ |
808 | 5391d806 | bellard | sector_num = ide_get_sector(s); |
809 | 5391d806 | bellard | n = s->nsector; |
810 | 5391d806 | bellard | if (n == 0) { |
811 | 5391d806 | bellard | /* no more sector to read from disk */
|
812 | 5391d806 | bellard | ide_transfer_stop(s); |
813 | 5391d806 | bellard | } else {
|
814 | 5391d806 | bellard | #if defined(DEBUG_IDE)
|
815 | 5391d806 | bellard | printf("read sector=%Ld\n", sector_num);
|
816 | 5391d806 | bellard | #endif
|
817 | 5391d806 | bellard | if (n > s->req_nb_sectors)
|
818 | 5391d806 | bellard | n = s->req_nb_sectors; |
819 | 5391d806 | bellard | ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); |
820 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
|
821 | 5391d806 | bellard | ide_set_irq(s); |
822 | 5391d806 | bellard | ide_set_sector(s, sector_num + n); |
823 | 5391d806 | bellard | s->nsector -= n; |
824 | 5391d806 | bellard | } |
825 | 5391d806 | bellard | } |
826 | 5391d806 | bellard | |
827 | 8ccad811 | bellard | /* return 0 if buffer completed */
|
828 | 8ccad811 | bellard | static int dma_buf_rw(BMDMAState *bm, int is_write) |
829 | 98087450 | bellard | { |
830 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
831 | 8ccad811 | bellard | struct {
|
832 | 8ccad811 | bellard | uint32_t addr; |
833 | 8ccad811 | bellard | uint32_t size; |
834 | 8ccad811 | bellard | } prd; |
835 | 8ccad811 | bellard | int l, len;
|
836 | 98087450 | bellard | |
837 | 8ccad811 | bellard | for(;;) {
|
838 | 8ccad811 | bellard | l = s->io_buffer_size - s->io_buffer_index; |
839 | 5fafdf24 | ths | if (l <= 0) |
840 | 8ccad811 | bellard | break;
|
841 | 8ccad811 | bellard | if (bm->cur_prd_len == 0) { |
842 | 8ccad811 | bellard | /* end of table (with a fail safe of one page) */
|
843 | 8ccad811 | bellard | if (bm->cur_prd_last ||
|
844 | 8ccad811 | bellard | (bm->cur_addr - bm->addr) >= 4096)
|
845 | 8ccad811 | bellard | return 0; |
846 | 8ccad811 | bellard | cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
|
847 | 8ccad811 | bellard | bm->cur_addr += 8;
|
848 | 8ccad811 | bellard | prd.addr = le32_to_cpu(prd.addr); |
849 | 8ccad811 | bellard | prd.size = le32_to_cpu(prd.size); |
850 | 8ccad811 | bellard | len = prd.size & 0xfffe;
|
851 | 8ccad811 | bellard | if (len == 0) |
852 | 8ccad811 | bellard | len = 0x10000;
|
853 | 8ccad811 | bellard | bm->cur_prd_len = len; |
854 | 8ccad811 | bellard | bm->cur_prd_addr = prd.addr; |
855 | 8ccad811 | bellard | bm->cur_prd_last = (prd.size & 0x80000000);
|
856 | 8ccad811 | bellard | } |
857 | 8ccad811 | bellard | if (l > bm->cur_prd_len)
|
858 | 8ccad811 | bellard | l = bm->cur_prd_len; |
859 | 8ccad811 | bellard | if (l > 0) { |
860 | 8ccad811 | bellard | if (is_write) {
|
861 | 5fafdf24 | ths | cpu_physical_memory_write(bm->cur_prd_addr, |
862 | 8ccad811 | bellard | s->io_buffer + s->io_buffer_index, l); |
863 | 8ccad811 | bellard | } else {
|
864 | 5fafdf24 | ths | cpu_physical_memory_read(bm->cur_prd_addr, |
865 | 8ccad811 | bellard | s->io_buffer + s->io_buffer_index, l); |
866 | 8ccad811 | bellard | } |
867 | 8ccad811 | bellard | bm->cur_prd_addr += l; |
868 | 8ccad811 | bellard | bm->cur_prd_len -= l; |
869 | 8ccad811 | bellard | s->io_buffer_index += l; |
870 | 98087450 | bellard | } |
871 | 98087450 | bellard | } |
872 | 8ccad811 | bellard | return 1; |
873 | 8ccad811 | bellard | } |
874 | 8ccad811 | bellard | |
875 | 8ccad811 | bellard | /* XXX: handle errors */
|
876 | 8ccad811 | bellard | static void ide_read_dma_cb(void *opaque, int ret) |
877 | 8ccad811 | bellard | { |
878 | 8ccad811 | bellard | BMDMAState *bm = opaque; |
879 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
880 | 8ccad811 | bellard | int n;
|
881 | 8ccad811 | bellard | int64_t sector_num; |
882 | 8ccad811 | bellard | |
883 | 8ccad811 | bellard | n = s->io_buffer_size >> 9;
|
884 | 8ccad811 | bellard | sector_num = ide_get_sector(s); |
885 | 8ccad811 | bellard | if (n > 0) { |
886 | 8ccad811 | bellard | sector_num += n; |
887 | 8ccad811 | bellard | ide_set_sector(s, sector_num); |
888 | 8ccad811 | bellard | s->nsector -= n; |
889 | 8ccad811 | bellard | if (dma_buf_rw(bm, 1) == 0) |
890 | 8ccad811 | bellard | goto eot;
|
891 | 8ccad811 | bellard | } |
892 | 8ccad811 | bellard | |
893 | 8ccad811 | bellard | /* end of transfer ? */
|
894 | 8ccad811 | bellard | if (s->nsector == 0) { |
895 | 98087450 | bellard | s->status = READY_STAT | SEEK_STAT; |
896 | 98087450 | bellard | ide_set_irq(s); |
897 | 8ccad811 | bellard | eot:
|
898 | 8ccad811 | bellard | bm->status &= ~BM_STATUS_DMAING; |
899 | 8ccad811 | bellard | bm->status |= BM_STATUS_INT; |
900 | 8ccad811 | bellard | bm->dma_cb = NULL;
|
901 | 8ccad811 | bellard | bm->ide_if = NULL;
|
902 | 8ccad811 | bellard | bm->aiocb = NULL;
|
903 | 8ccad811 | bellard | return;
|
904 | 98087450 | bellard | } |
905 | 8ccad811 | bellard | |
906 | 8ccad811 | bellard | /* launch next transfer */
|
907 | 8ccad811 | bellard | n = s->nsector; |
908 | 1d8cde5b | aurel32 | if (n > IDE_DMA_BUF_SECTORS)
|
909 | 1d8cde5b | aurel32 | n = IDE_DMA_BUF_SECTORS; |
910 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
911 | 8ccad811 | bellard | s->io_buffer_size = n * 512;
|
912 | 8ccad811 | bellard | #ifdef DEBUG_AIO
|
913 | 8ccad811 | bellard | printf("aio_read: sector_num=%lld n=%d\n", sector_num, n);
|
914 | 8ccad811 | bellard | #endif
|
915 | 5fafdf24 | ths | bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n, |
916 | 8ccad811 | bellard | ide_read_dma_cb, bm); |
917 | 98087450 | bellard | } |
918 | 98087450 | bellard | |
919 | 98087450 | bellard | static void ide_sector_read_dma(IDEState *s) |
920 | 98087450 | bellard | { |
921 | 8ccad811 | bellard | s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
922 | 98087450 | bellard | s->io_buffer_index = 0;
|
923 | 98087450 | bellard | s->io_buffer_size = 0;
|
924 | 98087450 | bellard | ide_dma_start(s, ide_read_dma_cb); |
925 | 98087450 | bellard | } |
926 | 98087450 | bellard | |
927 | a09db21f | bellard | static void ide_sector_write_timer_cb(void *opaque) |
928 | a09db21f | bellard | { |
929 | a09db21f | bellard | IDEState *s = opaque; |
930 | a09db21f | bellard | ide_set_irq(s); |
931 | a09db21f | bellard | } |
932 | a09db21f | bellard | |
933 | 5391d806 | bellard | static void ide_sector_write(IDEState *s) |
934 | 5391d806 | bellard | { |
935 | 5391d806 | bellard | int64_t sector_num; |
936 | 31c2a146 | ths | int ret, n, n1;
|
937 | 5391d806 | bellard | |
938 | 5391d806 | bellard | s->status = READY_STAT | SEEK_STAT; |
939 | 5391d806 | bellard | sector_num = ide_get_sector(s); |
940 | 5391d806 | bellard | #if defined(DEBUG_IDE)
|
941 | 5391d806 | bellard | printf("write sector=%Ld\n", sector_num);
|
942 | 5391d806 | bellard | #endif
|
943 | 5391d806 | bellard | n = s->nsector; |
944 | 5391d806 | bellard | if (n > s->req_nb_sectors)
|
945 | 5391d806 | bellard | n = s->req_nb_sectors; |
946 | 31c2a146 | ths | ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); |
947 | 5391d806 | bellard | s->nsector -= n; |
948 | 5391d806 | bellard | if (s->nsector == 0) { |
949 | 292eef5a | ths | /* no more sectors to write */
|
950 | 5391d806 | bellard | ide_transfer_stop(s); |
951 | 5391d806 | bellard | } else {
|
952 | 5391d806 | bellard | n1 = s->nsector; |
953 | 5391d806 | bellard | if (n1 > s->req_nb_sectors)
|
954 | 5391d806 | bellard | n1 = s->req_nb_sectors; |
955 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
|
956 | 5391d806 | bellard | } |
957 | 5391d806 | bellard | ide_set_sector(s, sector_num + n); |
958 | 3b46e624 | ths | |
959 | 31c2a146 | ths | #ifdef TARGET_I386
|
960 | 31c2a146 | ths | if (win2k_install_hack && ((++s->irq_count % 16) == 0)) { |
961 | 31c2a146 | ths | /* It seems there is a bug in the Windows 2000 installer HDD
|
962 | 31c2a146 | ths | IDE driver which fills the disk with empty logs when the
|
963 | 31c2a146 | ths | IDE write IRQ comes too early. This hack tries to correct
|
964 | 31c2a146 | ths | that at the expense of slower write performances. Use this
|
965 | 31c2a146 | ths | option _only_ to install Windows 2000. You must disable it
|
966 | 31c2a146 | ths | for normal use. */
|
967 | 31c2a146 | ths | qemu_mod_timer(s->sector_write_timer, |
968 | 31c2a146 | ths | qemu_get_clock(vm_clock) + (ticks_per_sec / 1000));
|
969 | 31c2a146 | ths | } else
|
970 | 31c2a146 | ths | #endif
|
971 | 31c2a146 | ths | { |
972 | 31c2a146 | ths | ide_set_irq(s); |
973 | 31c2a146 | ths | } |
974 | 5391d806 | bellard | } |
975 | 5391d806 | bellard | |
976 | 8ccad811 | bellard | /* XXX: handle errors */
|
977 | 8ccad811 | bellard | static void ide_write_dma_cb(void *opaque, int ret) |
978 | 98087450 | bellard | { |
979 | 8ccad811 | bellard | BMDMAState *bm = opaque; |
980 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
981 | 8ccad811 | bellard | int n;
|
982 | 98087450 | bellard | int64_t sector_num; |
983 | 98087450 | bellard | |
984 | 8ccad811 | bellard | n = s->io_buffer_size >> 9;
|
985 | 8ccad811 | bellard | sector_num = ide_get_sector(s); |
986 | 8ccad811 | bellard | if (n > 0) { |
987 | 8ccad811 | bellard | sector_num += n; |
988 | 8ccad811 | bellard | ide_set_sector(s, sector_num); |
989 | 8ccad811 | bellard | s->nsector -= n; |
990 | 98087450 | bellard | } |
991 | 98087450 | bellard | |
992 | 8ccad811 | bellard | /* end of transfer ? */
|
993 | 8ccad811 | bellard | if (s->nsector == 0) { |
994 | 8ccad811 | bellard | s->status = READY_STAT | SEEK_STAT; |
995 | 8ccad811 | bellard | ide_set_irq(s); |
996 | 8ccad811 | bellard | eot:
|
997 | 8ccad811 | bellard | bm->status &= ~BM_STATUS_DMAING; |
998 | 8ccad811 | bellard | bm->status |= BM_STATUS_INT; |
999 | 8ccad811 | bellard | bm->dma_cb = NULL;
|
1000 | 8ccad811 | bellard | bm->ide_if = NULL;
|
1001 | 8ccad811 | bellard | bm->aiocb = NULL;
|
1002 | 8ccad811 | bellard | return;
|
1003 | 8ccad811 | bellard | } |
1004 | 8ccad811 | bellard | |
1005 | 8ccad811 | bellard | /* launch next transfer */
|
1006 | 98087450 | bellard | n = s->nsector; |
1007 | 1d8cde5b | aurel32 | if (n > IDE_DMA_BUF_SECTORS)
|
1008 | 1d8cde5b | aurel32 | n = IDE_DMA_BUF_SECTORS; |
1009 | 98087450 | bellard | s->io_buffer_index = 0;
|
1010 | 98087450 | bellard | s->io_buffer_size = n * 512;
|
1011 | 8ccad811 | bellard | |
1012 | 8ccad811 | bellard | if (dma_buf_rw(bm, 0) == 0) |
1013 | 8ccad811 | bellard | goto eot;
|
1014 | 8ccad811 | bellard | #ifdef DEBUG_AIO
|
1015 | 8ccad811 | bellard | printf("aio_write: sector_num=%lld n=%d\n", sector_num, n);
|
1016 | 8ccad811 | bellard | #endif
|
1017 | 5fafdf24 | ths | bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n, |
1018 | 8ccad811 | bellard | ide_write_dma_cb, bm); |
1019 | 8ccad811 | bellard | } |
1020 | 8ccad811 | bellard | |
1021 | 8ccad811 | bellard | static void ide_sector_write_dma(IDEState *s) |
1022 | 8ccad811 | bellard | { |
1023 | 8ccad811 | bellard | s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT; |
1024 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
1025 | 8ccad811 | bellard | s->io_buffer_size = 0;
|
1026 | 98087450 | bellard | ide_dma_start(s, ide_write_dma_cb); |
1027 | 98087450 | bellard | } |
1028 | 98087450 | bellard | |
1029 | 5391d806 | bellard | static void ide_atapi_cmd_ok(IDEState *s) |
1030 | 5391d806 | bellard | { |
1031 | 5391d806 | bellard | s->error = 0;
|
1032 | 5391d806 | bellard | s->status = READY_STAT; |
1033 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1034 | 5391d806 | bellard | ide_set_irq(s); |
1035 | 5391d806 | bellard | } |
1036 | 5391d806 | bellard | |
1037 | 5391d806 | bellard | static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc) |
1038 | 5391d806 | bellard | { |
1039 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1040 | 5391d806 | bellard | printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
|
1041 | 5391d806 | bellard | #endif
|
1042 | 5391d806 | bellard | s->error = sense_key << 4;
|
1043 | 5391d806 | bellard | s->status = READY_STAT | ERR_STAT; |
1044 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1045 | 5391d806 | bellard | s->sense_key = sense_key; |
1046 | 5391d806 | bellard | s->asc = asc; |
1047 | 5391d806 | bellard | ide_set_irq(s); |
1048 | 5391d806 | bellard | } |
1049 | 5391d806 | bellard | |
1050 | 5391d806 | bellard | static inline void cpu_to_ube16(uint8_t *buf, int val) |
1051 | 5391d806 | bellard | { |
1052 | 5391d806 | bellard | buf[0] = val >> 8; |
1053 | 5391d806 | bellard | buf[1] = val;
|
1054 | 5391d806 | bellard | } |
1055 | 5391d806 | bellard | |
1056 | 5391d806 | bellard | static inline void cpu_to_ube32(uint8_t *buf, unsigned int val) |
1057 | 5391d806 | bellard | { |
1058 | 5391d806 | bellard | buf[0] = val >> 24; |
1059 | 5391d806 | bellard | buf[1] = val >> 16; |
1060 | 5391d806 | bellard | buf[2] = val >> 8; |
1061 | 5391d806 | bellard | buf[3] = val;
|
1062 | 5391d806 | bellard | } |
1063 | 5391d806 | bellard | |
1064 | 5391d806 | bellard | static inline int ube16_to_cpu(const uint8_t *buf) |
1065 | 5391d806 | bellard | { |
1066 | 5391d806 | bellard | return (buf[0] << 8) | buf[1]; |
1067 | 5391d806 | bellard | } |
1068 | 5391d806 | bellard | |
1069 | 5391d806 | bellard | static inline int ube32_to_cpu(const uint8_t *buf) |
1070 | 5391d806 | bellard | { |
1071 | 5391d806 | bellard | return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
1072 | 5391d806 | bellard | } |
1073 | 5391d806 | bellard | |
1074 | 98087450 | bellard | static void lba_to_msf(uint8_t *buf, int lba) |
1075 | 98087450 | bellard | { |
1076 | 98087450 | bellard | lba += 150;
|
1077 | 98087450 | bellard | buf[0] = (lba / 75) / 60; |
1078 | 98087450 | bellard | buf[1] = (lba / 75) % 60; |
1079 | 98087450 | bellard | buf[2] = lba % 75; |
1080 | 98087450 | bellard | } |
1081 | 98087450 | bellard | |
1082 | 8ccad811 | bellard | static void cd_data_to_raw(uint8_t *buf, int lba) |
1083 | 8ccad811 | bellard | { |
1084 | 8ccad811 | bellard | /* sync bytes */
|
1085 | 8ccad811 | bellard | buf[0] = 0x00; |
1086 | 8ccad811 | bellard | memset(buf + 1, 0xff, 10); |
1087 | 8ccad811 | bellard | buf[11] = 0x00; |
1088 | 8ccad811 | bellard | buf += 12;
|
1089 | 8ccad811 | bellard | /* MSF */
|
1090 | 8ccad811 | bellard | lba_to_msf(buf, lba); |
1091 | 8ccad811 | bellard | buf[3] = 0x01; /* mode 1 data */ |
1092 | 8ccad811 | bellard | buf += 4;
|
1093 | 8ccad811 | bellard | /* data */
|
1094 | 8ccad811 | bellard | buf += 2048;
|
1095 | 8ccad811 | bellard | /* XXX: ECC not computed */
|
1096 | 8ccad811 | bellard | memset(buf, 0, 288); |
1097 | 8ccad811 | bellard | } |
1098 | 8ccad811 | bellard | |
1099 | 5fafdf24 | ths | static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf, |
1100 | 98087450 | bellard | int sector_size)
|
1101 | 98087450 | bellard | { |
1102 | 66c6ef76 | bellard | int ret;
|
1103 | 66c6ef76 | bellard | |
1104 | 98087450 | bellard | switch(sector_size) {
|
1105 | 98087450 | bellard | case 2048: |
1106 | 66c6ef76 | bellard | ret = bdrv_read(bs, (int64_t)lba << 2, buf, 4); |
1107 | 98087450 | bellard | break;
|
1108 | 98087450 | bellard | case 2352: |
1109 | 66c6ef76 | bellard | ret = bdrv_read(bs, (int64_t)lba << 2, buf + 16, 4); |
1110 | 66c6ef76 | bellard | if (ret < 0) |
1111 | 66c6ef76 | bellard | return ret;
|
1112 | 8ccad811 | bellard | cd_data_to_raw(buf, lba); |
1113 | 98087450 | bellard | break;
|
1114 | 98087450 | bellard | default:
|
1115 | 66c6ef76 | bellard | ret = -EIO; |
1116 | 98087450 | bellard | break;
|
1117 | 98087450 | bellard | } |
1118 | 66c6ef76 | bellard | return ret;
|
1119 | 66c6ef76 | bellard | } |
1120 | 66c6ef76 | bellard | |
1121 | 66c6ef76 | bellard | static void ide_atapi_io_error(IDEState *s, int ret) |
1122 | 66c6ef76 | bellard | { |
1123 | 66c6ef76 | bellard | /* XXX: handle more errors */
|
1124 | 66c6ef76 | bellard | if (ret == -ENOMEDIUM) {
|
1125 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1126 | 66c6ef76 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1127 | 66c6ef76 | bellard | } else {
|
1128 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1129 | 66c6ef76 | bellard | ASC_LOGICAL_BLOCK_OOR); |
1130 | 66c6ef76 | bellard | } |
1131 | 98087450 | bellard | } |
1132 | 98087450 | bellard | |
1133 | 5391d806 | bellard | /* The whole ATAPI transfer logic is handled in this function */
|
1134 | 5391d806 | bellard | static void ide_atapi_cmd_reply_end(IDEState *s) |
1135 | 5391d806 | bellard | { |
1136 | 66c6ef76 | bellard | int byte_count_limit, size, ret;
|
1137 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1138 | 5fafdf24 | ths | printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
|
1139 | 5391d806 | bellard | s->packet_transfer_size, |
1140 | 5391d806 | bellard | s->elementary_transfer_size, |
1141 | 5391d806 | bellard | s->io_buffer_index); |
1142 | 5391d806 | bellard | #endif
|
1143 | 5391d806 | bellard | if (s->packet_transfer_size <= 0) { |
1144 | 5391d806 | bellard | /* end of transfer */
|
1145 | 5391d806 | bellard | ide_transfer_stop(s); |
1146 | 5391d806 | bellard | s->status = READY_STAT; |
1147 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1148 | 5391d806 | bellard | ide_set_irq(s); |
1149 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1150 | 5391d806 | bellard | printf("status=0x%x\n", s->status);
|
1151 | 5391d806 | bellard | #endif
|
1152 | 5391d806 | bellard | } else {
|
1153 | 5391d806 | bellard | /* see if a new sector must be read */
|
1154 | 98087450 | bellard | if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) { |
1155 | 66c6ef76 | bellard | ret = cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size); |
1156 | 66c6ef76 | bellard | if (ret < 0) { |
1157 | 66c6ef76 | bellard | ide_transfer_stop(s); |
1158 | 66c6ef76 | bellard | ide_atapi_io_error(s, ret); |
1159 | 66c6ef76 | bellard | return;
|
1160 | 66c6ef76 | bellard | } |
1161 | 5391d806 | bellard | s->lba++; |
1162 | 5391d806 | bellard | s->io_buffer_index = 0;
|
1163 | 5391d806 | bellard | } |
1164 | 5391d806 | bellard | if (s->elementary_transfer_size > 0) { |
1165 | 5391d806 | bellard | /* there are some data left to transmit in this elementary
|
1166 | 5391d806 | bellard | transfer */
|
1167 | 98087450 | bellard | size = s->cd_sector_size - s->io_buffer_index; |
1168 | 5391d806 | bellard | if (size > s->elementary_transfer_size)
|
1169 | 5391d806 | bellard | size = s->elementary_transfer_size; |
1170 | 5fafdf24 | ths | ide_transfer_start(s, s->io_buffer + s->io_buffer_index, |
1171 | 5391d806 | bellard | size, ide_atapi_cmd_reply_end); |
1172 | 5391d806 | bellard | s->packet_transfer_size -= size; |
1173 | 5391d806 | bellard | s->elementary_transfer_size -= size; |
1174 | 5391d806 | bellard | s->io_buffer_index += size; |
1175 | 5391d806 | bellard | } else {
|
1176 | 5391d806 | bellard | /* a new transfer is needed */
|
1177 | 5391d806 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
|
1178 | 5391d806 | bellard | byte_count_limit = s->lcyl | (s->hcyl << 8);
|
1179 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1180 | 5391d806 | bellard | printf("byte_count_limit=%d\n", byte_count_limit);
|
1181 | 5391d806 | bellard | #endif
|
1182 | 5391d806 | bellard | if (byte_count_limit == 0xffff) |
1183 | 5391d806 | bellard | byte_count_limit--; |
1184 | 5391d806 | bellard | size = s->packet_transfer_size; |
1185 | 5391d806 | bellard | if (size > byte_count_limit) {
|
1186 | 5391d806 | bellard | /* byte count limit must be even if this case */
|
1187 | 5391d806 | bellard | if (byte_count_limit & 1) |
1188 | 5391d806 | bellard | byte_count_limit--; |
1189 | 5391d806 | bellard | size = byte_count_limit; |
1190 | 5391d806 | bellard | } |
1191 | a136e5a8 | bellard | s->lcyl = size; |
1192 | a136e5a8 | bellard | s->hcyl = size >> 8;
|
1193 | 5391d806 | bellard | s->elementary_transfer_size = size; |
1194 | 5391d806 | bellard | /* we cannot transmit more than one sector at a time */
|
1195 | 5391d806 | bellard | if (s->lba != -1) { |
1196 | 98087450 | bellard | if (size > (s->cd_sector_size - s->io_buffer_index))
|
1197 | 98087450 | bellard | size = (s->cd_sector_size - s->io_buffer_index); |
1198 | 5391d806 | bellard | } |
1199 | 5fafdf24 | ths | ide_transfer_start(s, s->io_buffer + s->io_buffer_index, |
1200 | 5391d806 | bellard | size, ide_atapi_cmd_reply_end); |
1201 | 5391d806 | bellard | s->packet_transfer_size -= size; |
1202 | 5391d806 | bellard | s->elementary_transfer_size -= size; |
1203 | 5391d806 | bellard | s->io_buffer_index += size; |
1204 | 5391d806 | bellard | ide_set_irq(s); |
1205 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1206 | 5391d806 | bellard | printf("status=0x%x\n", s->status);
|
1207 | 5391d806 | bellard | #endif
|
1208 | 5391d806 | bellard | } |
1209 | 5391d806 | bellard | } |
1210 | 5391d806 | bellard | } |
1211 | 5391d806 | bellard | |
1212 | 5391d806 | bellard | /* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
|
1213 | 5391d806 | bellard | static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size) |
1214 | 5391d806 | bellard | { |
1215 | 5391d806 | bellard | if (size > max_size)
|
1216 | 5391d806 | bellard | size = max_size; |
1217 | 5391d806 | bellard | s->lba = -1; /* no sector read */ |
1218 | 5391d806 | bellard | s->packet_transfer_size = size; |
1219 | 5f12ab4b | ths | s->io_buffer_size = size; /* dma: send the reply data as one chunk */
|
1220 | 5391d806 | bellard | s->elementary_transfer_size = 0;
|
1221 | 5391d806 | bellard | s->io_buffer_index = 0;
|
1222 | 5391d806 | bellard | |
1223 | 5f12ab4b | ths | if (s->atapi_dma) {
|
1224 | 5f12ab4b | ths | s->status = READY_STAT | DRQ_STAT; |
1225 | 5f12ab4b | ths | ide_dma_start(s, ide_atapi_cmd_read_dma_cb); |
1226 | 5f12ab4b | ths | } else {
|
1227 | 5f12ab4b | ths | s->status = READY_STAT; |
1228 | 5f12ab4b | ths | ide_atapi_cmd_reply_end(s); |
1229 | 5f12ab4b | ths | } |
1230 | 5391d806 | bellard | } |
1231 | 5391d806 | bellard | |
1232 | 5391d806 | bellard | /* start a CD-CDROM read command */
|
1233 | 98087450 | bellard | static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors, |
1234 | 98087450 | bellard | int sector_size)
|
1235 | 5391d806 | bellard | { |
1236 | 5391d806 | bellard | s->lba = lba; |
1237 | 98087450 | bellard | s->packet_transfer_size = nb_sectors * sector_size; |
1238 | 5391d806 | bellard | s->elementary_transfer_size = 0;
|
1239 | 98087450 | bellard | s->io_buffer_index = sector_size; |
1240 | 98087450 | bellard | s->cd_sector_size = sector_size; |
1241 | 5391d806 | bellard | |
1242 | 5391d806 | bellard | s->status = READY_STAT; |
1243 | 5391d806 | bellard | ide_atapi_cmd_reply_end(s); |
1244 | 5391d806 | bellard | } |
1245 | 5391d806 | bellard | |
1246 | 98087450 | bellard | /* ATAPI DMA support */
|
1247 | 8ccad811 | bellard | |
1248 | 8ccad811 | bellard | /* XXX: handle read errors */
|
1249 | 8ccad811 | bellard | static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret) |
1250 | 98087450 | bellard | { |
1251 | 8ccad811 | bellard | BMDMAState *bm = opaque; |
1252 | 8ccad811 | bellard | IDEState *s = bm->ide_if; |
1253 | 8ccad811 | bellard | int data_offset, n;
|
1254 | 8ccad811 | bellard | |
1255 | 66c6ef76 | bellard | if (ret < 0) { |
1256 | 66c6ef76 | bellard | ide_atapi_io_error(s, ret); |
1257 | 66c6ef76 | bellard | goto eot;
|
1258 | 66c6ef76 | bellard | } |
1259 | 66c6ef76 | bellard | |
1260 | 8ccad811 | bellard | if (s->io_buffer_size > 0) { |
1261 | 5f12ab4b | ths | /*
|
1262 | 5f12ab4b | ths | * For a cdrom read sector command (s->lba != -1),
|
1263 | 5f12ab4b | ths | * adjust the lba for the next s->io_buffer_size chunk
|
1264 | 5f12ab4b | ths | * and dma the current chunk.
|
1265 | 5f12ab4b | ths | * For a command != read (s->lba == -1), just transfer
|
1266 | 5f12ab4b | ths | * the reply data.
|
1267 | 5f12ab4b | ths | */
|
1268 | 5f12ab4b | ths | if (s->lba != -1) { |
1269 | 5f12ab4b | ths | if (s->cd_sector_size == 2352) { |
1270 | 5f12ab4b | ths | n = 1;
|
1271 | 5f12ab4b | ths | cd_data_to_raw(s->io_buffer, s->lba); |
1272 | 5f12ab4b | ths | } else {
|
1273 | 5f12ab4b | ths | n = s->io_buffer_size >> 11;
|
1274 | 5f12ab4b | ths | } |
1275 | 5f12ab4b | ths | s->lba += n; |
1276 | 5f12ab4b | ths | } |
1277 | 8ccad811 | bellard | s->packet_transfer_size -= s->io_buffer_size; |
1278 | 8ccad811 | bellard | if (dma_buf_rw(bm, 1) == 0) |
1279 | 8ccad811 | bellard | goto eot;
|
1280 | 98087450 | bellard | } |
1281 | 8ccad811 | bellard | |
1282 | 98087450 | bellard | if (s->packet_transfer_size <= 0) { |
1283 | 98087450 | bellard | s->status = READY_STAT; |
1284 | 98087450 | bellard | s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
1285 | 98087450 | bellard | ide_set_irq(s); |
1286 | 8ccad811 | bellard | eot:
|
1287 | 8ccad811 | bellard | bm->status &= ~BM_STATUS_DMAING; |
1288 | 8ccad811 | bellard | bm->status |= BM_STATUS_INT; |
1289 | 8ccad811 | bellard | bm->dma_cb = NULL;
|
1290 | 8ccad811 | bellard | bm->ide_if = NULL;
|
1291 | 8ccad811 | bellard | bm->aiocb = NULL;
|
1292 | 8ccad811 | bellard | return;
|
1293 | 8ccad811 | bellard | } |
1294 | 3b46e624 | ths | |
1295 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
1296 | 8ccad811 | bellard | if (s->cd_sector_size == 2352) { |
1297 | 8ccad811 | bellard | n = 1;
|
1298 | 8ccad811 | bellard | s->io_buffer_size = s->cd_sector_size; |
1299 | 8ccad811 | bellard | data_offset = 16;
|
1300 | 8ccad811 | bellard | } else {
|
1301 | 8ccad811 | bellard | n = s->packet_transfer_size >> 11;
|
1302 | 1d8cde5b | aurel32 | if (n > (IDE_DMA_BUF_SECTORS / 4)) |
1303 | 1d8cde5b | aurel32 | n = (IDE_DMA_BUF_SECTORS / 4);
|
1304 | 8ccad811 | bellard | s->io_buffer_size = n * 2048;
|
1305 | 8ccad811 | bellard | data_offset = 0;
|
1306 | 98087450 | bellard | } |
1307 | 8ccad811 | bellard | #ifdef DEBUG_AIO
|
1308 | 8ccad811 | bellard | printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
|
1309 | 8ccad811 | bellard | #endif
|
1310 | 5fafdf24 | ths | bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2,
|
1311 | 5fafdf24 | ths | s->io_buffer + data_offset, n * 4,
|
1312 | 8ccad811 | bellard | ide_atapi_cmd_read_dma_cb, bm); |
1313 | 66c6ef76 | bellard | if (!bm->aiocb) {
|
1314 | 66c6ef76 | bellard | /* Note: media not present is the most likely case */
|
1315 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1316 | 66c6ef76 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1317 | 66c6ef76 | bellard | goto eot;
|
1318 | 66c6ef76 | bellard | } |
1319 | 98087450 | bellard | } |
1320 | 98087450 | bellard | |
1321 | 98087450 | bellard | /* start a CD-CDROM read command with DMA */
|
1322 | 98087450 | bellard | /* XXX: test if DMA is available */
|
1323 | 98087450 | bellard | static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors, |
1324 | 98087450 | bellard | int sector_size)
|
1325 | 98087450 | bellard | { |
1326 | 98087450 | bellard | s->lba = lba; |
1327 | 98087450 | bellard | s->packet_transfer_size = nb_sectors * sector_size; |
1328 | 8ccad811 | bellard | s->io_buffer_index = 0;
|
1329 | 8ccad811 | bellard | s->io_buffer_size = 0;
|
1330 | 98087450 | bellard | s->cd_sector_size = sector_size; |
1331 | 98087450 | bellard | |
1332 | 8ccad811 | bellard | /* XXX: check if BUSY_STAT should be set */
|
1333 | 8ccad811 | bellard | s->status = READY_STAT | DRQ_STAT | BUSY_STAT; |
1334 | 98087450 | bellard | ide_dma_start(s, ide_atapi_cmd_read_dma_cb); |
1335 | 98087450 | bellard | } |
1336 | 98087450 | bellard | |
1337 | 5fafdf24 | ths | static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors, |
1338 | 98087450 | bellard | int sector_size)
|
1339 | 98087450 | bellard | { |
1340 | 98087450 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1341 | 5f12ab4b | ths | printf("read %s: LBA=%d nb_sectors=%d\n", s->atapi_dma ? "dma" : "pio", |
1342 | 5f12ab4b | ths | lba, nb_sectors); |
1343 | 98087450 | bellard | #endif
|
1344 | 98087450 | bellard | if (s->atapi_dma) {
|
1345 | 98087450 | bellard | ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size); |
1346 | 98087450 | bellard | } else {
|
1347 | 98087450 | bellard | ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size); |
1348 | 98087450 | bellard | } |
1349 | 98087450 | bellard | } |
1350 | 98087450 | bellard | |
1351 | 38cdea7c | balrog | static inline uint8_t ide_atapi_set_profile(uint8_t *buf, uint8_t *index, |
1352 | 38cdea7c | balrog | uint16_t profile) |
1353 | 38cdea7c | balrog | { |
1354 | 38cdea7c | balrog | uint8_t *buf_profile = buf + 12; /* start of profiles */ |
1355 | 38cdea7c | balrog | |
1356 | 38cdea7c | balrog | buf_profile += ((*index) * 4); /* start of indexed profile */ |
1357 | 38cdea7c | balrog | cpu_to_ube16 (buf_profile, profile); |
1358 | 38cdea7c | balrog | buf_profile[2] = ((buf_profile[0] == buf[6]) && (buf_profile[1] == buf[7])); |
1359 | 38cdea7c | balrog | |
1360 | 38cdea7c | balrog | /* each profile adds 4 bytes to the response */
|
1361 | 38cdea7c | balrog | (*index)++; |
1362 | 38cdea7c | balrog | buf[11] += 4; /* Additional Length */ |
1363 | 38cdea7c | balrog | |
1364 | 38cdea7c | balrog | return 4; |
1365 | 38cdea7c | balrog | } |
1366 | 38cdea7c | balrog | |
1367 | 5391d806 | bellard | static void ide_atapi_cmd(IDEState *s) |
1368 | 5391d806 | bellard | { |
1369 | 5391d806 | bellard | const uint8_t *packet;
|
1370 | 5391d806 | bellard | uint8_t *buf; |
1371 | 5391d806 | bellard | int max_len;
|
1372 | 5391d806 | bellard | |
1373 | 5391d806 | bellard | packet = s->io_buffer; |
1374 | 5391d806 | bellard | buf = s->io_buffer; |
1375 | 5391d806 | bellard | #ifdef DEBUG_IDE_ATAPI
|
1376 | 5391d806 | bellard | { |
1377 | 5391d806 | bellard | int i;
|
1378 | 5391d806 | bellard | printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8)); |
1379 | 5391d806 | bellard | for(i = 0; i < ATAPI_PACKET_SIZE; i++) { |
1380 | 5391d806 | bellard | printf(" %02x", packet[i]);
|
1381 | 5391d806 | bellard | } |
1382 | 5391d806 | bellard | printf("\n");
|
1383 | 5391d806 | bellard | } |
1384 | 5391d806 | bellard | #endif
|
1385 | 5391d806 | bellard | switch(s->io_buffer[0]) { |
1386 | 5391d806 | bellard | case GPCMD_TEST_UNIT_READY:
|
1387 | caed8802 | bellard | if (bdrv_is_inserted(s->bs)) {
|
1388 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1389 | 5391d806 | bellard | } else {
|
1390 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1391 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1392 | 5391d806 | bellard | } |
1393 | 5391d806 | bellard | break;
|
1394 | d14049ea | ths | case GPCMD_MODE_SENSE_6:
|
1395 | 5391d806 | bellard | case GPCMD_MODE_SENSE_10:
|
1396 | 5391d806 | bellard | { |
1397 | 5391d806 | bellard | int action, code;
|
1398 | d14049ea | ths | if (packet[0] == GPCMD_MODE_SENSE_10) |
1399 | d14049ea | ths | max_len = ube16_to_cpu(packet + 7);
|
1400 | d14049ea | ths | else
|
1401 | d14049ea | ths | max_len = packet[4];
|
1402 | 5391d806 | bellard | action = packet[2] >> 6; |
1403 | 5391d806 | bellard | code = packet[2] & 0x3f; |
1404 | 5391d806 | bellard | switch(action) {
|
1405 | 5391d806 | bellard | case 0: /* current values */ |
1406 | 5391d806 | bellard | switch(code) {
|
1407 | 5391d806 | bellard | case 0x01: /* error recovery */ |
1408 | 5391d806 | bellard | cpu_to_ube16(&buf[0], 16 + 6); |
1409 | 5391d806 | bellard | buf[2] = 0x70; |
1410 | 5391d806 | bellard | buf[3] = 0; |
1411 | 5391d806 | bellard | buf[4] = 0; |
1412 | 5391d806 | bellard | buf[5] = 0; |
1413 | 5391d806 | bellard | buf[6] = 0; |
1414 | 5391d806 | bellard | buf[7] = 0; |
1415 | 5391d806 | bellard | |
1416 | 5391d806 | bellard | buf[8] = 0x01; |
1417 | 5391d806 | bellard | buf[9] = 0x06; |
1418 | 5391d806 | bellard | buf[10] = 0x00; |
1419 | 5391d806 | bellard | buf[11] = 0x05; |
1420 | 5391d806 | bellard | buf[12] = 0x00; |
1421 | 5391d806 | bellard | buf[13] = 0x00; |
1422 | 5391d806 | bellard | buf[14] = 0x00; |
1423 | 5391d806 | bellard | buf[15] = 0x00; |
1424 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 16, max_len);
|
1425 | 5391d806 | bellard | break;
|
1426 | 5391d806 | bellard | case 0x2a: |
1427 | 5391d806 | bellard | cpu_to_ube16(&buf[0], 28 + 6); |
1428 | 5391d806 | bellard | buf[2] = 0x70; |
1429 | 5391d806 | bellard | buf[3] = 0; |
1430 | 5391d806 | bellard | buf[4] = 0; |
1431 | 5391d806 | bellard | buf[5] = 0; |
1432 | 5391d806 | bellard | buf[6] = 0; |
1433 | 5391d806 | bellard | buf[7] = 0; |
1434 | 5391d806 | bellard | |
1435 | 5391d806 | bellard | buf[8] = 0x2a; |
1436 | 5391d806 | bellard | buf[9] = 0x12; |
1437 | 0d4a05a1 | ths | buf[10] = 0x00; |
1438 | 5391d806 | bellard | buf[11] = 0x00; |
1439 | 3b46e624 | ths | |
1440 | 5391d806 | bellard | buf[12] = 0x70; |
1441 | 5391d806 | bellard | buf[13] = 3 << 5; |
1442 | 5391d806 | bellard | buf[14] = (1 << 0) | (1 << 3) | (1 << 5); |
1443 | caed8802 | bellard | if (bdrv_is_locked(s->bs))
|
1444 | 5391d806 | bellard | buf[6] |= 1 << 1; |
1445 | 5391d806 | bellard | buf[15] = 0x00; |
1446 | 5391d806 | bellard | cpu_to_ube16(&buf[16], 706); |
1447 | 5391d806 | bellard | buf[18] = 0; |
1448 | 5391d806 | bellard | buf[19] = 2; |
1449 | 5391d806 | bellard | cpu_to_ube16(&buf[20], 512); |
1450 | 5391d806 | bellard | cpu_to_ube16(&buf[22], 706); |
1451 | 5391d806 | bellard | buf[24] = 0; |
1452 | 5391d806 | bellard | buf[25] = 0; |
1453 | 5391d806 | bellard | buf[26] = 0; |
1454 | 5391d806 | bellard | buf[27] = 0; |
1455 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 28, max_len);
|
1456 | 5391d806 | bellard | break;
|
1457 | 5391d806 | bellard | default:
|
1458 | 5391d806 | bellard | goto error_cmd;
|
1459 | 5391d806 | bellard | } |
1460 | 5391d806 | bellard | break;
|
1461 | 5391d806 | bellard | case 1: /* changeable values */ |
1462 | 5391d806 | bellard | goto error_cmd;
|
1463 | 5391d806 | bellard | case 2: /* default values */ |
1464 | 5391d806 | bellard | goto error_cmd;
|
1465 | 5391d806 | bellard | default:
|
1466 | 5391d806 | bellard | case 3: /* saved values */ |
1467 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1468 | 5391d806 | bellard | ASC_SAVING_PARAMETERS_NOT_SUPPORTED); |
1469 | 5391d806 | bellard | break;
|
1470 | 5391d806 | bellard | } |
1471 | 5391d806 | bellard | } |
1472 | 5391d806 | bellard | break;
|
1473 | 5391d806 | bellard | case GPCMD_REQUEST_SENSE:
|
1474 | 5391d806 | bellard | max_len = packet[4];
|
1475 | 5391d806 | bellard | memset(buf, 0, 18); |
1476 | 5391d806 | bellard | buf[0] = 0x70 | (1 << 7); |
1477 | 5391d806 | bellard | buf[2] = s->sense_key;
|
1478 | 5391d806 | bellard | buf[7] = 10; |
1479 | 5391d806 | bellard | buf[12] = s->asc;
|
1480 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 18, max_len);
|
1481 | 5391d806 | bellard | break;
|
1482 | 5391d806 | bellard | case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
|
1483 | caed8802 | bellard | if (bdrv_is_inserted(s->bs)) {
|
1484 | caed8802 | bellard | bdrv_set_locked(s->bs, packet[4] & 1); |
1485 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1486 | 5391d806 | bellard | } else {
|
1487 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1488 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1489 | 5391d806 | bellard | } |
1490 | 5391d806 | bellard | break;
|
1491 | 5391d806 | bellard | case GPCMD_READ_10:
|
1492 | 5391d806 | bellard | case GPCMD_READ_12:
|
1493 | 5391d806 | bellard | { |
1494 | 5391d806 | bellard | int nb_sectors, lba;
|
1495 | 5391d806 | bellard | |
1496 | 5391d806 | bellard | if (packet[0] == GPCMD_READ_10) |
1497 | 5391d806 | bellard | nb_sectors = ube16_to_cpu(packet + 7);
|
1498 | 5391d806 | bellard | else
|
1499 | 5391d806 | bellard | nb_sectors = ube32_to_cpu(packet + 6);
|
1500 | 5391d806 | bellard | lba = ube32_to_cpu(packet + 2);
|
1501 | 5391d806 | bellard | if (nb_sectors == 0) { |
1502 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1503 | 5391d806 | bellard | break;
|
1504 | 5391d806 | bellard | } |
1505 | 98087450 | bellard | ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
|
1506 | 98087450 | bellard | } |
1507 | 98087450 | bellard | break;
|
1508 | 98087450 | bellard | case GPCMD_READ_CD:
|
1509 | 98087450 | bellard | { |
1510 | 98087450 | bellard | int nb_sectors, lba, transfer_request;
|
1511 | 98087450 | bellard | |
1512 | 98087450 | bellard | nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8]; |
1513 | 98087450 | bellard | lba = ube32_to_cpu(packet + 2);
|
1514 | 98087450 | bellard | if (nb_sectors == 0) { |
1515 | 98087450 | bellard | ide_atapi_cmd_ok(s); |
1516 | 98087450 | bellard | break;
|
1517 | 98087450 | bellard | } |
1518 | 98087450 | bellard | transfer_request = packet[9];
|
1519 | 98087450 | bellard | switch(transfer_request & 0xf8) { |
1520 | 98087450 | bellard | case 0x00: |
1521 | 98087450 | bellard | /* nothing */
|
1522 | 98087450 | bellard | ide_atapi_cmd_ok(s); |
1523 | 98087450 | bellard | break;
|
1524 | 98087450 | bellard | case 0x10: |
1525 | 98087450 | bellard | /* normal read */
|
1526 | 98087450 | bellard | ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
|
1527 | 98087450 | bellard | break;
|
1528 | 98087450 | bellard | case 0xf8: |
1529 | 98087450 | bellard | /* read all data */
|
1530 | 98087450 | bellard | ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
|
1531 | 98087450 | bellard | break;
|
1532 | 98087450 | bellard | default:
|
1533 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1534 | 98087450 | bellard | ASC_INV_FIELD_IN_CMD_PACKET); |
1535 | 98087450 | bellard | break;
|
1536 | 98087450 | bellard | } |
1537 | 5391d806 | bellard | } |
1538 | 5391d806 | bellard | break;
|
1539 | 5391d806 | bellard | case GPCMD_SEEK:
|
1540 | 5391d806 | bellard | { |
1541 | 96b8f136 | ths | unsigned int lba; |
1542 | 96b8f136 | ths | uint64_t total_sectors; |
1543 | 66c6ef76 | bellard | |
1544 | 66c6ef76 | bellard | bdrv_get_geometry(s->bs, &total_sectors); |
1545 | 66c6ef76 | bellard | total_sectors >>= 2;
|
1546 | 96b8f136 | ths | if (total_sectors == 0) { |
1547 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1548 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1549 | 5391d806 | bellard | break;
|
1550 | 5391d806 | bellard | } |
1551 | 5391d806 | bellard | lba = ube32_to_cpu(packet + 2);
|
1552 | 66c6ef76 | bellard | if (lba >= total_sectors) {
|
1553 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1554 | 5391d806 | bellard | ASC_LOGICAL_BLOCK_OOR); |
1555 | 5391d806 | bellard | break;
|
1556 | 5391d806 | bellard | } |
1557 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1558 | 5391d806 | bellard | } |
1559 | 5391d806 | bellard | break;
|
1560 | 5391d806 | bellard | case GPCMD_START_STOP_UNIT:
|
1561 | 5391d806 | bellard | { |
1562 | 5391d806 | bellard | int start, eject;
|
1563 | 5391d806 | bellard | start = packet[4] & 1; |
1564 | 5391d806 | bellard | eject = (packet[4] >> 1) & 1; |
1565 | 3b46e624 | ths | |
1566 | caed8802 | bellard | if (eject && !start) {
|
1567 | caed8802 | bellard | /* eject the disk */
|
1568 | 66c6ef76 | bellard | bdrv_eject(s->bs, 1);
|
1569 | 66c6ef76 | bellard | } else if (eject && start) { |
1570 | 66c6ef76 | bellard | /* close the tray */
|
1571 | 66c6ef76 | bellard | bdrv_eject(s->bs, 0);
|
1572 | caed8802 | bellard | } |
1573 | 5391d806 | bellard | ide_atapi_cmd_ok(s); |
1574 | 5391d806 | bellard | } |
1575 | 5391d806 | bellard | break;
|
1576 | 5391d806 | bellard | case GPCMD_MECHANISM_STATUS:
|
1577 | 5391d806 | bellard | { |
1578 | 5391d806 | bellard | max_len = ube16_to_cpu(packet + 8);
|
1579 | 5391d806 | bellard | cpu_to_ube16(buf, 0);
|
1580 | 5391d806 | bellard | /* no current LBA */
|
1581 | 5391d806 | bellard | buf[2] = 0; |
1582 | 5391d806 | bellard | buf[3] = 0; |
1583 | 5391d806 | bellard | buf[4] = 0; |
1584 | 5391d806 | bellard | buf[5] = 1; |
1585 | 5391d806 | bellard | cpu_to_ube16(buf + 6, 0); |
1586 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 8, max_len);
|
1587 | 5391d806 | bellard | } |
1588 | 5391d806 | bellard | break;
|
1589 | 5391d806 | bellard | case GPCMD_READ_TOC_PMA_ATIP:
|
1590 | 5391d806 | bellard | { |
1591 | 5391d806 | bellard | int format, msf, start_track, len;
|
1592 | 96b8f136 | ths | uint64_t total_sectors; |
1593 | 5391d806 | bellard | |
1594 | 66c6ef76 | bellard | bdrv_get_geometry(s->bs, &total_sectors); |
1595 | 66c6ef76 | bellard | total_sectors >>= 2;
|
1596 | 96b8f136 | ths | if (total_sectors == 0) { |
1597 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1598 | 5391d806 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1599 | 5391d806 | bellard | break;
|
1600 | 5391d806 | bellard | } |
1601 | 5391d806 | bellard | max_len = ube16_to_cpu(packet + 7);
|
1602 | 5391d806 | bellard | format = packet[9] >> 6; |
1603 | 5391d806 | bellard | msf = (packet[1] >> 1) & 1; |
1604 | 5391d806 | bellard | start_track = packet[6];
|
1605 | 5391d806 | bellard | switch(format) {
|
1606 | 5391d806 | bellard | case 0: |
1607 | 66c6ef76 | bellard | len = cdrom_read_toc(total_sectors, buf, msf, start_track); |
1608 | 5391d806 | bellard | if (len < 0) |
1609 | 5391d806 | bellard | goto error_cmd;
|
1610 | 5391d806 | bellard | ide_atapi_cmd_reply(s, len, max_len); |
1611 | 5391d806 | bellard | break;
|
1612 | 5391d806 | bellard | case 1: |
1613 | 5391d806 | bellard | /* multi session : only a single session defined */
|
1614 | 5391d806 | bellard | memset(buf, 0, 12); |
1615 | 5391d806 | bellard | buf[1] = 0x0a; |
1616 | 5391d806 | bellard | buf[2] = 0x01; |
1617 | 5391d806 | bellard | buf[3] = 0x01; |
1618 | 5391d806 | bellard | ide_atapi_cmd_reply(s, 12, max_len);
|
1619 | 5391d806 | bellard | break;
|
1620 | 98087450 | bellard | case 2: |
1621 | 66c6ef76 | bellard | len = cdrom_read_toc_raw(total_sectors, buf, msf, start_track); |
1622 | 98087450 | bellard | if (len < 0) |
1623 | 98087450 | bellard | goto error_cmd;
|
1624 | 98087450 | bellard | ide_atapi_cmd_reply(s, len, max_len); |
1625 | 98087450 | bellard | break;
|
1626 | 5391d806 | bellard | default:
|
1627 | 7f777bf3 | bellard | error_cmd:
|
1628 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1629 | 7f777bf3 | bellard | ASC_INV_FIELD_IN_CMD_PACKET); |
1630 | 7f777bf3 | bellard | break;
|
1631 | 5391d806 | bellard | } |
1632 | 5391d806 | bellard | } |
1633 | 5391d806 | bellard | break;
|
1634 | 5391d806 | bellard | case GPCMD_READ_CDVD_CAPACITY:
|
1635 | 66c6ef76 | bellard | { |
1636 | 96b8f136 | ths | uint64_t total_sectors; |
1637 | 66c6ef76 | bellard | |
1638 | 66c6ef76 | bellard | bdrv_get_geometry(s->bs, &total_sectors); |
1639 | 66c6ef76 | bellard | total_sectors >>= 2;
|
1640 | 96b8f136 | ths | if (total_sectors == 0) { |
1641 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1642 | 66c6ef76 | bellard | ASC_MEDIUM_NOT_PRESENT); |
1643 | 66c6ef76 | bellard | break;
|
1644 | 66c6ef76 | bellard | } |
1645 | 66c6ef76 | bellard | /* NOTE: it is really the number of sectors minus 1 */
|
1646 | 66c6ef76 | bellard | cpu_to_ube32(buf, total_sectors - 1);
|
1647 | 66c6ef76 | bellard | cpu_to_ube32(buf + 4, 2048); |
1648 | 66c6ef76 | bellard | ide_atapi_cmd_reply(s, 8, 8); |
1649 | 5391d806 | bellard | } |
1650 | 5391d806 | bellard | break;
|
1651 | d14049ea | ths | case GPCMD_READ_DVD_STRUCTURE:
|
1652 | d14049ea | ths | { |
1653 | d14049ea | ths | int media = packet[1]; |
1654 | d14049ea | ths | int layer = packet[6]; |
1655 | d14049ea | ths | int format = packet[2]; |
1656 | 96b8f136 | ths | uint64_t total_sectors; |
1657 | d14049ea | ths | |
1658 | d14049ea | ths | if (media != 0 || layer != 0) |
1659 | d14049ea | ths | { |
1660 | d14049ea | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1661 | d14049ea | ths | ASC_INV_FIELD_IN_CMD_PACKET); |
1662 | d14049ea | ths | } |
1663 | d14049ea | ths | |
1664 | d14049ea | ths | switch (format) {
|
1665 | d14049ea | ths | case 0: |
1666 | d14049ea | ths | bdrv_get_geometry(s->bs, &total_sectors); |
1667 | d14049ea | ths | total_sectors >>= 2;
|
1668 | 96b8f136 | ths | if (total_sectors == 0) { |
1669 | 96b8f136 | ths | ide_atapi_cmd_error(s, SENSE_NOT_READY, |
1670 | 96b8f136 | ths | ASC_MEDIUM_NOT_PRESENT); |
1671 | 96b8f136 | ths | break;
|
1672 | 96b8f136 | ths | } |
1673 | d14049ea | ths | |
1674 | d14049ea | ths | memset(buf, 0, 2052); |
1675 | d14049ea | ths | |
1676 | d14049ea | ths | buf[4] = 1; // DVD-ROM, part version 1 |
1677 | d14049ea | ths | buf[5] = 0xf; // 120mm disc, maximum rate unspecified |
1678 | d14049ea | ths | buf[6] = 0; // one layer, embossed data |
1679 | d14049ea | ths | buf[7] = 0; |
1680 | d14049ea | ths | |
1681 | d14049ea | ths | cpu_to_ube32(buf + 8, 0); |
1682 | d14049ea | ths | cpu_to_ube32(buf + 12, total_sectors - 1); |
1683 | d14049ea | ths | cpu_to_ube32(buf + 16, total_sectors - 1); |
1684 | d14049ea | ths | |
1685 | d14049ea | ths | cpu_to_be16wu((uint16_t *)buf, 2048 + 4); |
1686 | d14049ea | ths | |
1687 | d14049ea | ths | ide_atapi_cmd_reply(s, 2048 + 3, 2048 + 4); |
1688 | d14049ea | ths | break;
|
1689 | d14049ea | ths | |
1690 | d14049ea | ths | default:
|
1691 | d14049ea | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1692 | d14049ea | ths | ASC_INV_FIELD_IN_CMD_PACKET); |
1693 | d14049ea | ths | break;
|
1694 | d14049ea | ths | } |
1695 | d14049ea | ths | } |
1696 | d14049ea | ths | break;
|
1697 | d14049ea | ths | case GPCMD_SET_SPEED:
|
1698 | d14049ea | ths | ide_atapi_cmd_ok(s); |
1699 | d14049ea | ths | break;
|
1700 | bd0d90b2 | bellard | case GPCMD_INQUIRY:
|
1701 | bd0d90b2 | bellard | max_len = packet[4];
|
1702 | bd0d90b2 | bellard | buf[0] = 0x05; /* CD-ROM */ |
1703 | bd0d90b2 | bellard | buf[1] = 0x80; /* removable */ |
1704 | bd0d90b2 | bellard | buf[2] = 0x00; /* ISO */ |
1705 | bd0d90b2 | bellard | buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */ |
1706 | aa1f17c1 | ths | buf[4] = 31; /* additional length */ |
1707 | bd0d90b2 | bellard | buf[5] = 0; /* reserved */ |
1708 | bd0d90b2 | bellard | buf[6] = 0; /* reserved */ |
1709 | bd0d90b2 | bellard | buf[7] = 0; /* reserved */ |
1710 | bd0d90b2 | bellard | padstr8(buf + 8, 8, "QEMU"); |
1711 | 38cdea7c | balrog | padstr8(buf + 16, 16, "QEMU DVD-ROM"); |
1712 | bd0d90b2 | bellard | padstr8(buf + 32, 4, QEMU_VERSION); |
1713 | bd0d90b2 | bellard | ide_atapi_cmd_reply(s, 36, max_len);
|
1714 | bd0d90b2 | bellard | break;
|
1715 | d14049ea | ths | case GPCMD_GET_CONFIGURATION:
|
1716 | d14049ea | ths | { |
1717 | 38cdea7c | balrog | uint32_t len; |
1718 | d14049ea | ths | |
1719 | d14049ea | ths | /* only feature 0 is supported */
|
1720 | d14049ea | ths | if (packet[2] != 0 || packet[3] != 0) { |
1721 | d14049ea | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1722 | d14049ea | ths | ASC_INV_FIELD_IN_CMD_PACKET); |
1723 | d14049ea | ths | break;
|
1724 | d14049ea | ths | } |
1725 | 38cdea7c | balrog | |
1726 | 38cdea7c | balrog | /* XXX: could result in alignment problems in some architectures */
|
1727 | 38cdea7c | balrog | max_len = ube16_to_cpu(packet + 7);
|
1728 | 38cdea7c | balrog | /*
|
1729 | 38cdea7c | balrog | * XXX: avoid overflow for io_buffer if max_len is bigger than the
|
1730 | 38cdea7c | balrog | * size of that buffer (dimensioned to max number of sectors
|
1731 | 38cdea7c | balrog | * to transfer at once)
|
1732 | 38cdea7c | balrog | *
|
1733 | 38cdea7c | balrog | * Only a problem if the feature/profiles grow exponentially.
|
1734 | 38cdea7c | balrog | */
|
1735 | 38cdea7c | balrog | if (max_len > 512) /* XXX: assume 1 sector */ |
1736 | 38cdea7c | balrog | max_len = 512;
|
1737 | 38cdea7c | balrog | |
1738 | 38cdea7c | balrog | memset(buf, 0, max_len);
|
1739 | 38cdea7c | balrog | /*
|
1740 | 38cdea7c | balrog | * the number of sectors from the media tells us which profile
|
1741 | 38cdea7c | balrog | * to use as current. 0 means there is no media
|
1742 | 38cdea7c | balrog | *
|
1743 | 38cdea7c | balrog | * XXX: fails to detect correctly DVDs with less data burned
|
1744 | 38cdea7c | balrog | * than what a CD can hold
|
1745 | 38cdea7c | balrog | */
|
1746 | 38cdea7c | balrog | if ((s -> nb_sectors)) {
|
1747 | 38cdea7c | balrog | if ((s -> nb_sectors > CD_MAX_SECTORS))
|
1748 | 38cdea7c | balrog | cpu_to_ube16(buf + 6, MMC_PROFILE_DVD_ROM);
|
1749 | 38cdea7c | balrog | else
|
1750 | 38cdea7c | balrog | cpu_to_ube16(buf + 6, MMC_PROFILE_CD_ROM);
|
1751 | 38cdea7c | balrog | } |
1752 | 38cdea7c | balrog | |
1753 | 38cdea7c | balrog | len = 8; /* header completed */ |
1754 | 38cdea7c | balrog | if (max_len > len) {
|
1755 | 38cdea7c | balrog | uint8_t index = 0;
|
1756 | 38cdea7c | balrog | |
1757 | 38cdea7c | balrog | buf[10] = 0x02 | 0x01; /* persistent and current */ |
1758 | 38cdea7c | balrog | len += 4; /* header */ |
1759 | 38cdea7c | balrog | len += ide_atapi_set_profile(buf, &index, MMC_PROFILE_DVD_ROM); |
1760 | 38cdea7c | balrog | len += ide_atapi_set_profile(buf, &index, MMC_PROFILE_CD_ROM); |
1761 | 38cdea7c | balrog | } |
1762 | 38cdea7c | balrog | cpu_to_ube32(buf, len - 4); /* data length */ |
1763 | 38cdea7c | balrog | |
1764 | 38cdea7c | balrog | ide_atapi_cmd_reply(s, len, max_len); |
1765 | d14049ea | ths | break;
|
1766 | d14049ea | ths | } |
1767 | 5391d806 | bellard | default:
|
1768 | 5fafdf24 | ths | ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, |
1769 | 7f777bf3 | bellard | ASC_ILLEGAL_OPCODE); |
1770 | 5391d806 | bellard | break;
|
1771 | 5391d806 | bellard | } |
1772 | 5391d806 | bellard | } |
1773 | 5391d806 | bellard | |
1774 | 201a51fc | balrog | static void ide_cfata_metadata_inquiry(IDEState *s) |
1775 | 201a51fc | balrog | { |
1776 | 201a51fc | balrog | uint16_t *p; |
1777 | 201a51fc | balrog | uint32_t spd; |
1778 | 201a51fc | balrog | |
1779 | 201a51fc | balrog | p = (uint16_t *) s->io_buffer; |
1780 | 201a51fc | balrog | memset(p, 0, 0x200); |
1781 | 201a51fc | balrog | spd = ((s->mdata_size - 1) >> 9) + 1; |
1782 | 201a51fc | balrog | |
1783 | 201a51fc | balrog | put_le16(p + 0, 0x0001); /* Data format revision */ |
1784 | 201a51fc | balrog | put_le16(p + 1, 0x0000); /* Media property: silicon */ |
1785 | 201a51fc | balrog | put_le16(p + 2, s->media_changed); /* Media status */ |
1786 | 201a51fc | balrog | put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */ |
1787 | 201a51fc | balrog | put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */ |
1788 | 201a51fc | balrog | put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */ |
1789 | 201a51fc | balrog | put_le16(p + 6, spd >> 16); /* Sectors per device (high) */ |
1790 | 201a51fc | balrog | } |
1791 | 201a51fc | balrog | |
1792 | 201a51fc | balrog | static void ide_cfata_metadata_read(IDEState *s) |
1793 | 201a51fc | balrog | { |
1794 | 201a51fc | balrog | uint16_t *p; |
1795 | 201a51fc | balrog | |
1796 | 201a51fc | balrog | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { |
1797 | 201a51fc | balrog | s->status = ERR_STAT; |
1798 | 201a51fc | balrog | s->error = ABRT_ERR; |
1799 | 201a51fc | balrog | return;
|
1800 | 201a51fc | balrog | } |
1801 | 201a51fc | balrog | |
1802 | 201a51fc | balrog | p = (uint16_t *) s->io_buffer; |
1803 | 201a51fc | balrog | memset(p, 0, 0x200); |
1804 | 201a51fc | balrog | |
1805 | 201a51fc | balrog | put_le16(p + 0, s->media_changed); /* Media status */ |
1806 | 201a51fc | balrog | memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), |
1807 | 201a51fc | balrog | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), |
1808 | 201a51fc | balrog | s->nsector << 9), 0x200 - 2)); |
1809 | 201a51fc | balrog | } |
1810 | 201a51fc | balrog | |
1811 | 201a51fc | balrog | static void ide_cfata_metadata_write(IDEState *s) |
1812 | 201a51fc | balrog | { |
1813 | 201a51fc | balrog | if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) { |
1814 | 201a51fc | balrog | s->status = ERR_STAT; |
1815 | 201a51fc | balrog | s->error = ABRT_ERR; |
1816 | 201a51fc | balrog | return;
|
1817 | 201a51fc | balrog | } |
1818 | 201a51fc | balrog | |
1819 | 201a51fc | balrog | s->media_changed = 0;
|
1820 | 201a51fc | balrog | |
1821 | 201a51fc | balrog | memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9), |
1822 | 201a51fc | balrog | s->io_buffer + 2,
|
1823 | 201a51fc | balrog | MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9), |
1824 | 201a51fc | balrog | s->nsector << 9), 0x200 - 2)); |
1825 | 201a51fc | balrog | } |
1826 | 201a51fc | balrog | |
1827 | bd491d6a | ths | /* called when the inserted state of the media has changed */
|
1828 | bd491d6a | ths | static void cdrom_change_cb(void *opaque) |
1829 | bd491d6a | ths | { |
1830 | bd491d6a | ths | IDEState *s = opaque; |
1831 | 96b8f136 | ths | uint64_t nb_sectors; |
1832 | bd491d6a | ths | |
1833 | bd491d6a | ths | /* XXX: send interrupt too */
|
1834 | bd491d6a | ths | bdrv_get_geometry(s->bs, &nb_sectors); |
1835 | bd491d6a | ths | s->nb_sectors = nb_sectors; |
1836 | bd491d6a | ths | } |
1837 | bd491d6a | ths | |
1838 | c2ff060f | bellard | static void ide_cmd_lba48_transform(IDEState *s, int lba48) |
1839 | c2ff060f | bellard | { |
1840 | c2ff060f | bellard | s->lba48 = lba48; |
1841 | c2ff060f | bellard | |
1842 | c2ff060f | bellard | /* handle the 'magic' 0 nsector count conversion here. to avoid
|
1843 | c2ff060f | bellard | * fiddling with the rest of the read logic, we just store the
|
1844 | c2ff060f | bellard | * full sector count in ->nsector and ignore ->hob_nsector from now
|
1845 | c2ff060f | bellard | */
|
1846 | c2ff060f | bellard | if (!s->lba48) {
|
1847 | c2ff060f | bellard | if (!s->nsector)
|
1848 | c2ff060f | bellard | s->nsector = 256;
|
1849 | c2ff060f | bellard | } else {
|
1850 | c2ff060f | bellard | if (!s->nsector && !s->hob_nsector)
|
1851 | c2ff060f | bellard | s->nsector = 65536;
|
1852 | c2ff060f | bellard | else {
|
1853 | c2ff060f | bellard | int lo = s->nsector;
|
1854 | c2ff060f | bellard | int hi = s->hob_nsector;
|
1855 | c2ff060f | bellard | |
1856 | c2ff060f | bellard | s->nsector = (hi << 8) | lo;
|
1857 | c2ff060f | bellard | } |
1858 | c2ff060f | bellard | } |
1859 | c2ff060f | bellard | } |
1860 | c2ff060f | bellard | |
1861 | c2ff060f | bellard | static void ide_clear_hob(IDEState *ide_if) |
1862 | c2ff060f | bellard | { |
1863 | c2ff060f | bellard | /* any write clears HOB high bit of device control register */
|
1864 | c2ff060f | bellard | ide_if[0].select &= ~(1 << 7); |
1865 | c2ff060f | bellard | ide_if[1].select &= ~(1 << 7); |
1866 | c2ff060f | bellard | } |
1867 | c2ff060f | bellard | |
1868 | caed8802 | bellard | static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
1869 | caed8802 | bellard | { |
1870 | caed8802 | bellard | IDEState *ide_if = opaque; |
1871 | c45c3d00 | bellard | IDEState *s; |
1872 | 5391d806 | bellard | int unit, n;
|
1873 | c2ff060f | bellard | int lba48 = 0; |
1874 | 5391d806 | bellard | |
1875 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
1876 | 5391d806 | bellard | printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
|
1877 | 5391d806 | bellard | #endif
|
1878 | c2ff060f | bellard | |
1879 | 5391d806 | bellard | addr &= 7;
|
1880 | 5391d806 | bellard | switch(addr) {
|
1881 | 5391d806 | bellard | case 0: |
1882 | 5391d806 | bellard | break;
|
1883 | 5391d806 | bellard | case 1: |
1884 | c2ff060f | bellard | ide_clear_hob(ide_if); |
1885 | c45c3d00 | bellard | /* NOTE: data is written to the two drives */
|
1886 | c2ff060f | bellard | ide_if[0].hob_feature = ide_if[0].feature; |
1887 | c2ff060f | bellard | ide_if[1].hob_feature = ide_if[1].feature; |
1888 | c45c3d00 | bellard | ide_if[0].feature = val;
|
1889 | c45c3d00 | bellard | ide_if[1].feature = val;
|
1890 | 5391d806 | bellard | break;
|
1891 | 5391d806 | bellard | case 2: |
1892 | c2ff060f | bellard | ide_clear_hob(ide_if); |
1893 | c2ff060f | bellard | ide_if[0].hob_nsector = ide_if[0].nsector; |
1894 | c2ff060f | bellard | ide_if[1].hob_nsector = ide_if[1].nsector; |
1895 | c45c3d00 | bellard | ide_if[0].nsector = val;
|
1896 | c45c3d00 | bellard | ide_if[1].nsector = val;
|
1897 | 5391d806 | bellard | break;
|
1898 | 5391d806 | bellard | case 3: |
1899 | c2ff060f | bellard | ide_clear_hob(ide_if); |
1900 | c2ff060f | bellard | ide_if[0].hob_sector = ide_if[0].sector; |
1901 | c2ff060f | bellard | ide_if[1].hob_sector = ide_if[1].sector; |
1902 | c45c3d00 | bellard | ide_if[0].sector = val;
|
1903 | c45c3d00 | bellard | ide_if[1].sector = val;
|
1904 | 5391d806 | bellard | break;
|
1905 | 5391d806 | bellard | case 4: |
1906 | c2ff060f | bellard | ide_clear_hob(ide_if); |
1907 | c2ff060f | bellard | ide_if[0].hob_lcyl = ide_if[0].lcyl; |
1908 | c2ff060f | bellard | ide_if[1].hob_lcyl = ide_if[1].lcyl; |
1909 | c45c3d00 | bellard | ide_if[0].lcyl = val;
|
1910 | c45c3d00 | bellard | ide_if[1].lcyl = val;
|
1911 | 5391d806 | bellard | break;
|
1912 | 5391d806 | bellard | case 5: |
1913 | c2ff060f | bellard | ide_clear_hob(ide_if); |
1914 | c2ff060f | bellard | ide_if[0].hob_hcyl = ide_if[0].hcyl; |
1915 | c2ff060f | bellard | ide_if[1].hob_hcyl = ide_if[1].hcyl; |
1916 | c45c3d00 | bellard | ide_if[0].hcyl = val;
|
1917 | c45c3d00 | bellard | ide_if[1].hcyl = val;
|
1918 | 5391d806 | bellard | break;
|
1919 | 5391d806 | bellard | case 6: |
1920 | c2ff060f | bellard | /* FIXME: HOB readback uses bit 7 */
|
1921 | 7ae98627 | bellard | ide_if[0].select = (val & ~0x10) | 0xa0; |
1922 | 7ae98627 | bellard | ide_if[1].select = (val | 0x10) | 0xa0; |
1923 | 5391d806 | bellard | /* select drive */
|
1924 | 5391d806 | bellard | unit = (val >> 4) & 1; |
1925 | 5391d806 | bellard | s = ide_if + unit; |
1926 | 5391d806 | bellard | ide_if->cur_drive = s; |
1927 | 5391d806 | bellard | break;
|
1928 | 5391d806 | bellard | default:
|
1929 | 5391d806 | bellard | case 7: |
1930 | 5391d806 | bellard | /* command */
|
1931 | 5391d806 | bellard | #if defined(DEBUG_IDE)
|
1932 | 5391d806 | bellard | printf("ide: CMD=%02x\n", val);
|
1933 | 5391d806 | bellard | #endif
|
1934 | c45c3d00 | bellard | s = ide_if->cur_drive; |
1935 | 66201e2d | bellard | /* ignore commands to non existant slave */
|
1936 | 5fafdf24 | ths | if (s != ide_if && !s->bs)
|
1937 | 66201e2d | bellard | break;
|
1938 | c2ff060f | bellard | |
1939 | 5391d806 | bellard | switch(val) {
|
1940 | 5391d806 | bellard | case WIN_IDENTIFY:
|
1941 | 5391d806 | bellard | if (s->bs && !s->is_cdrom) {
|
1942 | 201a51fc | balrog | if (!s->is_cf)
|
1943 | 201a51fc | balrog | ide_identify(s); |
1944 | 201a51fc | balrog | else
|
1945 | 201a51fc | balrog | ide_cfata_identify(s); |
1946 | 2a282056 | bellard | s->status = READY_STAT | SEEK_STAT; |
1947 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
1948 | 5391d806 | bellard | } else {
|
1949 | 5391d806 | bellard | if (s->is_cdrom) {
|
1950 | 5391d806 | bellard | ide_set_signature(s); |
1951 | 5391d806 | bellard | } |
1952 | 5391d806 | bellard | ide_abort_command(s); |
1953 | 5391d806 | bellard | } |
1954 | 5391d806 | bellard | ide_set_irq(s); |
1955 | 5391d806 | bellard | break;
|
1956 | 5391d806 | bellard | case WIN_SPECIFY:
|
1957 | 5391d806 | bellard | case WIN_RECAL:
|
1958 | a136e5a8 | bellard | s->error = 0;
|
1959 | 769bec72 | bellard | s->status = READY_STAT | SEEK_STAT; |
1960 | 5391d806 | bellard | ide_set_irq(s); |
1961 | 5391d806 | bellard | break;
|
1962 | 5391d806 | bellard | case WIN_SETMULT:
|
1963 | 201a51fc | balrog | if (s->is_cf && s->nsector == 0) { |
1964 | 201a51fc | balrog | /* Disable Read and Write Multiple */
|
1965 | 201a51fc | balrog | s->mult_sectors = 0;
|
1966 | 201a51fc | balrog | s->status = READY_STAT; |
1967 | 201a51fc | balrog | } else if ((s->nsector & 0xff) != 0 && |
1968 | 39dfc926 | ths | ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
|
1969 | 39dfc926 | ths | (s->nsector & (s->nsector - 1)) != 0)) { |
1970 | 5391d806 | bellard | ide_abort_command(s); |
1971 | 5391d806 | bellard | } else {
|
1972 | 292eef5a | ths | s->mult_sectors = s->nsector & 0xff;
|
1973 | 5391d806 | bellard | s->status = READY_STAT; |
1974 | 5391d806 | bellard | } |
1975 | 5391d806 | bellard | ide_set_irq(s); |
1976 | 5391d806 | bellard | break;
|
1977 | c2ff060f | bellard | case WIN_VERIFY_EXT:
|
1978 | c2ff060f | bellard | lba48 = 1;
|
1979 | 4ce900b4 | bellard | case WIN_VERIFY:
|
1980 | 4ce900b4 | bellard | case WIN_VERIFY_ONCE:
|
1981 | 4ce900b4 | bellard | /* do sector number check ? */
|
1982 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
1983 | 4ce900b4 | bellard | s->status = READY_STAT; |
1984 | 4ce900b4 | bellard | ide_set_irq(s); |
1985 | 4ce900b4 | bellard | break;
|
1986 | c2ff060f | bellard | case WIN_READ_EXT:
|
1987 | c2ff060f | bellard | lba48 = 1;
|
1988 | 5391d806 | bellard | case WIN_READ:
|
1989 | 5391d806 | bellard | case WIN_READ_ONCE:
|
1990 | 5fafdf24 | ths | if (!s->bs)
|
1991 | 6b136f9e | bellard | goto abort_cmd;
|
1992 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
1993 | 5391d806 | bellard | s->req_nb_sectors = 1;
|
1994 | 5391d806 | bellard | ide_sector_read(s); |
1995 | 5391d806 | bellard | break;
|
1996 | c2ff060f | bellard | case WIN_WRITE_EXT:
|
1997 | c2ff060f | bellard | lba48 = 1;
|
1998 | 5391d806 | bellard | case WIN_WRITE:
|
1999 | 5391d806 | bellard | case WIN_WRITE_ONCE:
|
2000 | 201a51fc | balrog | case CFA_WRITE_SECT_WO_ERASE:
|
2001 | 201a51fc | balrog | case WIN_WRITE_VERIFY:
|
2002 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2003 | a136e5a8 | bellard | s->error = 0;
|
2004 | f66723fa | bellard | s->status = SEEK_STAT | READY_STAT; |
2005 | 5391d806 | bellard | s->req_nb_sectors = 1;
|
2006 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
|
2007 | 201a51fc | balrog | s->media_changed = 1;
|
2008 | 5391d806 | bellard | break;
|
2009 | c2ff060f | bellard | case WIN_MULTREAD_EXT:
|
2010 | c2ff060f | bellard | lba48 = 1;
|
2011 | 5391d806 | bellard | case WIN_MULTREAD:
|
2012 | 5391d806 | bellard | if (!s->mult_sectors)
|
2013 | 5391d806 | bellard | goto abort_cmd;
|
2014 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2015 | 5391d806 | bellard | s->req_nb_sectors = s->mult_sectors; |
2016 | 5391d806 | bellard | ide_sector_read(s); |
2017 | 5391d806 | bellard | break;
|
2018 | c2ff060f | bellard | case WIN_MULTWRITE_EXT:
|
2019 | c2ff060f | bellard | lba48 = 1;
|
2020 | 5391d806 | bellard | case WIN_MULTWRITE:
|
2021 | 201a51fc | balrog | case CFA_WRITE_MULTI_WO_ERASE:
|
2022 | 5391d806 | bellard | if (!s->mult_sectors)
|
2023 | 5391d806 | bellard | goto abort_cmd;
|
2024 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2025 | a136e5a8 | bellard | s->error = 0;
|
2026 | f66723fa | bellard | s->status = SEEK_STAT | READY_STAT; |
2027 | 5391d806 | bellard | s->req_nb_sectors = s->mult_sectors; |
2028 | 5391d806 | bellard | n = s->nsector; |
2029 | 5391d806 | bellard | if (n > s->req_nb_sectors)
|
2030 | 5391d806 | bellard | n = s->req_nb_sectors; |
2031 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
|
2032 | 201a51fc | balrog | s->media_changed = 1;
|
2033 | 5391d806 | bellard | break;
|
2034 | c2ff060f | bellard | case WIN_READDMA_EXT:
|
2035 | c2ff060f | bellard | lba48 = 1;
|
2036 | 98087450 | bellard | case WIN_READDMA:
|
2037 | 98087450 | bellard | case WIN_READDMA_ONCE:
|
2038 | 5fafdf24 | ths | if (!s->bs)
|
2039 | 98087450 | bellard | goto abort_cmd;
|
2040 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2041 | 98087450 | bellard | ide_sector_read_dma(s); |
2042 | 98087450 | bellard | break;
|
2043 | c2ff060f | bellard | case WIN_WRITEDMA_EXT:
|
2044 | c2ff060f | bellard | lba48 = 1;
|
2045 | 98087450 | bellard | case WIN_WRITEDMA:
|
2046 | 98087450 | bellard | case WIN_WRITEDMA_ONCE:
|
2047 | 5fafdf24 | ths | if (!s->bs)
|
2048 | 98087450 | bellard | goto abort_cmd;
|
2049 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2050 | 98087450 | bellard | ide_sector_write_dma(s); |
2051 | 201a51fc | balrog | s->media_changed = 1;
|
2052 | 98087450 | bellard | break;
|
2053 | c2ff060f | bellard | case WIN_READ_NATIVE_MAX_EXT:
|
2054 | c2ff060f | bellard | lba48 = 1;
|
2055 | 5391d806 | bellard | case WIN_READ_NATIVE_MAX:
|
2056 | c2ff060f | bellard | ide_cmd_lba48_transform(s, lba48); |
2057 | 5391d806 | bellard | ide_set_sector(s, s->nb_sectors - 1);
|
2058 | 5391d806 | bellard | s->status = READY_STAT; |
2059 | 5391d806 | bellard | ide_set_irq(s); |
2060 | 5391d806 | bellard | break;
|
2061 | a136e5a8 | bellard | case WIN_CHECKPOWERMODE1:
|
2062 | 201a51fc | balrog | case WIN_CHECKPOWERMODE2:
|
2063 | a136e5a8 | bellard | s->nsector = 0xff; /* device active or idle */ |
2064 | a136e5a8 | bellard | s->status = READY_STAT; |
2065 | a136e5a8 | bellard | ide_set_irq(s); |
2066 | a136e5a8 | bellard | break;
|
2067 | 34e538ae | bellard | case WIN_SETFEATURES:
|
2068 | 34e538ae | bellard | if (!s->bs)
|
2069 | 34e538ae | bellard | goto abort_cmd;
|
2070 | 34e538ae | bellard | /* XXX: valid for CDROM ? */
|
2071 | 34e538ae | bellard | switch(s->feature) {
|
2072 | e1f63470 | ths | case 0xcc: /* reverting to power-on defaults enable */ |
2073 | e1f63470 | ths | case 0x66: /* reverting to power-on defaults disable */ |
2074 | 34e538ae | bellard | case 0x02: /* write cache enable */ |
2075 | 34e538ae | bellard | case 0x82: /* write cache disable */ |
2076 | 34e538ae | bellard | case 0xaa: /* read look-ahead enable */ |
2077 | 34e538ae | bellard | case 0x55: /* read look-ahead disable */ |
2078 | 201a51fc | balrog | case 0x05: /* set advanced power management mode */ |
2079 | 201a51fc | balrog | case 0x85: /* disable advanced power management mode */ |
2080 | 201a51fc | balrog | case 0x69: /* NOP */ |
2081 | 201a51fc | balrog | case 0x67: /* NOP */ |
2082 | 201a51fc | balrog | case 0x96: /* NOP */ |
2083 | 201a51fc | balrog | case 0x9a: /* NOP */ |
2084 | c3e88d8c | ths | case 0x42: /* enable Automatic Acoustic Mode */ |
2085 | c3e88d8c | ths | case 0xc2: /* disable Automatic Acoustic Mode */ |
2086 | e0fe67aa | bellard | s->status = READY_STAT | SEEK_STAT; |
2087 | 34e538ae | bellard | ide_set_irq(s); |
2088 | 34e538ae | bellard | break;
|
2089 | 94458802 | bellard | case 0x03: { /* set transfer mode */ |
2090 | 94458802 | bellard | uint8_t val = s->nsector & 0x07;
|
2091 | 94458802 | bellard | |
2092 | 94458802 | bellard | switch (s->nsector >> 3) { |
2093 | 94458802 | bellard | case 0x00: /* pio default */ |
2094 | 94458802 | bellard | case 0x01: /* pio mode */ |
2095 | 94458802 | bellard | put_le16(s->identify_data + 63,0x07); |
2096 | 94458802 | bellard | put_le16(s->identify_data + 88,0x3f); |
2097 | 94458802 | bellard | break;
|
2098 | 94458802 | bellard | case 0x04: /* mdma mode */ |
2099 | 94458802 | bellard | put_le16(s->identify_data + 63,0x07 | (1 << (val + 8))); |
2100 | 94458802 | bellard | put_le16(s->identify_data + 88,0x3f); |
2101 | 94458802 | bellard | break;
|
2102 | 94458802 | bellard | case 0x08: /* udma mode */ |
2103 | 94458802 | bellard | put_le16(s->identify_data + 63,0x07); |
2104 | 94458802 | bellard | put_le16(s->identify_data + 88,0x3f | (1 << (val + 8))); |
2105 | 94458802 | bellard | break;
|
2106 | 94458802 | bellard | default:
|
2107 | 94458802 | bellard | goto abort_cmd;
|
2108 | 94458802 | bellard | } |
2109 | 94458802 | bellard | s->status = READY_STAT | SEEK_STAT; |
2110 | 94458802 | bellard | ide_set_irq(s); |
2111 | 94458802 | bellard | break;
|
2112 | 94458802 | bellard | } |
2113 | 34e538ae | bellard | default:
|
2114 | 34e538ae | bellard | goto abort_cmd;
|
2115 | 34e538ae | bellard | } |
2116 | 34e538ae | bellard | break;
|
2117 | c2ff060f | bellard | case WIN_FLUSH_CACHE:
|
2118 | c2ff060f | bellard | case WIN_FLUSH_CACHE_EXT:
|
2119 | 7a6cba61 | pbrook | if (s->bs)
|
2120 | 7a6cba61 | pbrook | bdrv_flush(s->bs); |
2121 | 7a6cba61 | pbrook | s->status = READY_STAT; |
2122 | 7a6cba61 | pbrook | ide_set_irq(s); |
2123 | 7a6cba61 | pbrook | break;
|
2124 | c3e88d8c | ths | case WIN_STANDBY:
|
2125 | c3e88d8c | ths | case WIN_STANDBY2:
|
2126 | c3e88d8c | ths | case WIN_STANDBYNOW1:
|
2127 | 201a51fc | balrog | case WIN_STANDBYNOW2:
|
2128 | c451ee71 | bellard | case WIN_IDLEIMMEDIATE:
|
2129 | 201a51fc | balrog | case CFA_IDLEIMMEDIATE:
|
2130 | 201a51fc | balrog | case WIN_SETIDLE1:
|
2131 | 201a51fc | balrog | case WIN_SETIDLE2:
|
2132 | c3e88d8c | ths | case WIN_SLEEPNOW1:
|
2133 | c3e88d8c | ths | case WIN_SLEEPNOW2:
|
2134 | c3e88d8c | ths | s->status = READY_STAT; |
2135 | a7dfe172 | bellard | ide_set_irq(s); |
2136 | a7dfe172 | bellard | break;
|
2137 | 5391d806 | bellard | /* ATAPI commands */
|
2138 | 5391d806 | bellard | case WIN_PIDENTIFY:
|
2139 | 5391d806 | bellard | if (s->is_cdrom) {
|
2140 | 5391d806 | bellard | ide_atapi_identify(s); |
2141 | 1298fe63 | bellard | s->status = READY_STAT | SEEK_STAT; |
2142 | 5391d806 | bellard | ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
|
2143 | 5391d806 | bellard | } else {
|
2144 | 5391d806 | bellard | ide_abort_command(s); |
2145 | 5391d806 | bellard | } |
2146 | 5391d806 | bellard | ide_set_irq(s); |
2147 | 5391d806 | bellard | break;
|
2148 | c451ee71 | bellard | case WIN_DIAGNOSE:
|
2149 | c451ee71 | bellard | ide_set_signature(s); |
2150 | 38453b93 | balrog | s->status = READY_STAT; |
2151 | c451ee71 | bellard | s->error = 0x01;
|
2152 | f5fdd0a8 | balrog | ide_set_irq(s); |
2153 | c451ee71 | bellard | break;
|
2154 | 5391d806 | bellard | case WIN_SRST:
|
2155 | 5391d806 | bellard | if (!s->is_cdrom)
|
2156 | 5391d806 | bellard | goto abort_cmd;
|
2157 | 5391d806 | bellard | ide_set_signature(s); |
2158 | 6b136f9e | bellard | s->status = 0x00; /* NOTE: READY is _not_ set */ |
2159 | 5391d806 | bellard | s->error = 0x01;
|
2160 | 5391d806 | bellard | break;
|
2161 | 5391d806 | bellard | case WIN_PACKETCMD:
|
2162 | 5391d806 | bellard | if (!s->is_cdrom)
|
2163 | 5391d806 | bellard | goto abort_cmd;
|
2164 | 98087450 | bellard | /* overlapping commands not supported */
|
2165 | 98087450 | bellard | if (s->feature & 0x02) |
2166 | 5391d806 | bellard | goto abort_cmd;
|
2167 | 7603d156 | ths | s->status = READY_STAT; |
2168 | 98087450 | bellard | s->atapi_dma = s->feature & 1;
|
2169 | 5391d806 | bellard | s->nsector = 1;
|
2170 | 5fafdf24 | ths | ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, |
2171 | 5391d806 | bellard | ide_atapi_cmd); |
2172 | 5391d806 | bellard | break;
|
2173 | 201a51fc | balrog | /* CF-ATA commands */
|
2174 | 201a51fc | balrog | case CFA_REQ_EXT_ERROR_CODE:
|
2175 | 201a51fc | balrog | if (!s->is_cf)
|
2176 | 201a51fc | balrog | goto abort_cmd;
|
2177 | 201a51fc | balrog | s->error = 0x09; /* miscellaneous error */ |
2178 | 201a51fc | balrog | s->status = READY_STAT; |
2179 | 201a51fc | balrog | ide_set_irq(s); |
2180 | 201a51fc | balrog | break;
|
2181 | 201a51fc | balrog | case CFA_ERASE_SECTORS:
|
2182 | 201a51fc | balrog | case CFA_WEAR_LEVEL:
|
2183 | 201a51fc | balrog | if (!s->is_cf)
|
2184 | 201a51fc | balrog | goto abort_cmd;
|
2185 | 201a51fc | balrog | if (val == CFA_WEAR_LEVEL)
|
2186 | 201a51fc | balrog | s->nsector = 0;
|
2187 | 201a51fc | balrog | if (val == CFA_ERASE_SECTORS)
|
2188 | 201a51fc | balrog | s->media_changed = 1;
|
2189 | 201a51fc | balrog | s->error = 0x00;
|
2190 | 201a51fc | balrog | s->status = READY_STAT; |
2191 | 201a51fc | balrog | ide_set_irq(s); |
2192 | 201a51fc | balrog | break;
|
2193 | 201a51fc | balrog | case CFA_TRANSLATE_SECTOR:
|
2194 | 201a51fc | balrog | if (!s->is_cf)
|
2195 | 201a51fc | balrog | goto abort_cmd;
|
2196 | 201a51fc | balrog | s->error = 0x00;
|
2197 | 201a51fc | balrog | s->status = READY_STAT; |
2198 | 201a51fc | balrog | memset(s->io_buffer, 0, 0x200); |
2199 | 201a51fc | balrog | s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */ |
2200 | 201a51fc | balrog | s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */ |
2201 | 201a51fc | balrog | s->io_buffer[0x02] = s->select; /* Head */ |
2202 | 201a51fc | balrog | s->io_buffer[0x03] = s->sector; /* Sector */ |
2203 | 201a51fc | balrog | s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */ |
2204 | 201a51fc | balrog | s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */ |
2205 | 201a51fc | balrog | s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */ |
2206 | 201a51fc | balrog | s->io_buffer[0x13] = 0x00; /* Erase flag */ |
2207 | 201a51fc | balrog | s->io_buffer[0x18] = 0x00; /* Hot count */ |
2208 | 201a51fc | balrog | s->io_buffer[0x19] = 0x00; /* Hot count */ |
2209 | 201a51fc | balrog | s->io_buffer[0x1a] = 0x01; /* Hot count */ |
2210 | 201a51fc | balrog | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
2211 | 201a51fc | balrog | ide_set_irq(s); |
2212 | 201a51fc | balrog | break;
|
2213 | 201a51fc | balrog | case CFA_ACCESS_METADATA_STORAGE:
|
2214 | 201a51fc | balrog | if (!s->is_cf)
|
2215 | 201a51fc | balrog | goto abort_cmd;
|
2216 | 201a51fc | balrog | switch (s->feature) {
|
2217 | 201a51fc | balrog | case 0x02: /* Inquiry Metadata Storage */ |
2218 | 201a51fc | balrog | ide_cfata_metadata_inquiry(s); |
2219 | 201a51fc | balrog | break;
|
2220 | 201a51fc | balrog | case 0x03: /* Read Metadata Storage */ |
2221 | 201a51fc | balrog | ide_cfata_metadata_read(s); |
2222 | 201a51fc | balrog | break;
|
2223 | 201a51fc | balrog | case 0x04: /* Write Metadata Storage */ |
2224 | 201a51fc | balrog | ide_cfata_metadata_write(s); |
2225 | 201a51fc | balrog | break;
|
2226 | 201a51fc | balrog | default:
|
2227 | 201a51fc | balrog | goto abort_cmd;
|
2228 | 201a51fc | balrog | } |
2229 | 201a51fc | balrog | ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
|
2230 | 201a51fc | balrog | s->status = 0x00; /* NOTE: READY is _not_ set */ |
2231 | 201a51fc | balrog | ide_set_irq(s); |
2232 | 201a51fc | balrog | break;
|
2233 | 201a51fc | balrog | case IBM_SENSE_CONDITION:
|
2234 | 201a51fc | balrog | if (!s->is_cf)
|
2235 | 201a51fc | balrog | goto abort_cmd;
|
2236 | 201a51fc | balrog | switch (s->feature) {
|
2237 | 201a51fc | balrog | case 0x01: /* sense temperature in device */ |
2238 | 201a51fc | balrog | s->nsector = 0x50; /* +20 C */ |
2239 | 201a51fc | balrog | break;
|
2240 | 201a51fc | balrog | default:
|
2241 | 201a51fc | balrog | goto abort_cmd;
|
2242 | 201a51fc | balrog | } |
2243 | 201a51fc | balrog | s->status = READY_STAT; |
2244 | 201a51fc | balrog | ide_set_irq(s); |
2245 | 201a51fc | balrog | break;
|
2246 | 5391d806 | bellard | default:
|
2247 | 5391d806 | bellard | abort_cmd:
|
2248 | 5391d806 | bellard | ide_abort_command(s); |
2249 | 5391d806 | bellard | ide_set_irq(s); |
2250 | 5391d806 | bellard | break;
|
2251 | 5391d806 | bellard | } |
2252 | 5391d806 | bellard | } |
2253 | 5391d806 | bellard | } |
2254 | 5391d806 | bellard | |
2255 | caed8802 | bellard | static uint32_t ide_ioport_read(void *opaque, uint32_t addr1) |
2256 | 5391d806 | bellard | { |
2257 | 7ae98627 | bellard | IDEState *ide_if = opaque; |
2258 | 7ae98627 | bellard | IDEState *s = ide_if->cur_drive; |
2259 | 5391d806 | bellard | uint32_t addr; |
2260 | c2ff060f | bellard | int ret, hob;
|
2261 | 5391d806 | bellard | |
2262 | 5391d806 | bellard | addr = addr1 & 7;
|
2263 | c2ff060f | bellard | /* FIXME: HOB readback uses bit 7, but it's always set right now */
|
2264 | c2ff060f | bellard | //hob = s->select & (1 << 7);
|
2265 | c2ff060f | bellard | hob = 0;
|
2266 | 5391d806 | bellard | switch(addr) {
|
2267 | 5391d806 | bellard | case 0: |
2268 | 5391d806 | bellard | ret = 0xff;
|
2269 | 5391d806 | bellard | break;
|
2270 | 5391d806 | bellard | case 1: |
2271 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2272 | c45c3d00 | bellard | ret = 0;
|
2273 | c2ff060f | bellard | else if (!hob) |
2274 | c45c3d00 | bellard | ret = s->error; |
2275 | c2ff060f | bellard | else
|
2276 | c2ff060f | bellard | ret = s->hob_feature; |
2277 | 5391d806 | bellard | break;
|
2278 | 5391d806 | bellard | case 2: |
2279 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2280 | c45c3d00 | bellard | ret = 0;
|
2281 | c2ff060f | bellard | else if (!hob) |
2282 | c45c3d00 | bellard | ret = s->nsector & 0xff;
|
2283 | c2ff060f | bellard | else
|
2284 | c2ff060f | bellard | ret = s->hob_nsector; |
2285 | 5391d806 | bellard | break;
|
2286 | 5391d806 | bellard | case 3: |
2287 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2288 | c45c3d00 | bellard | ret = 0;
|
2289 | c2ff060f | bellard | else if (!hob) |
2290 | c45c3d00 | bellard | ret = s->sector; |
2291 | c2ff060f | bellard | else
|
2292 | c2ff060f | bellard | ret = s->hob_sector; |
2293 | 5391d806 | bellard | break;
|
2294 | 5391d806 | bellard | case 4: |
2295 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2296 | c45c3d00 | bellard | ret = 0;
|
2297 | c2ff060f | bellard | else if (!hob) |
2298 | c45c3d00 | bellard | ret = s->lcyl; |
2299 | c2ff060f | bellard | else
|
2300 | c2ff060f | bellard | ret = s->hob_lcyl; |
2301 | 5391d806 | bellard | break;
|
2302 | 5391d806 | bellard | case 5: |
2303 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2304 | c45c3d00 | bellard | ret = 0;
|
2305 | c2ff060f | bellard | else if (!hob) |
2306 | c45c3d00 | bellard | ret = s->hcyl; |
2307 | c2ff060f | bellard | else
|
2308 | c2ff060f | bellard | ret = s->hob_hcyl; |
2309 | 5391d806 | bellard | break;
|
2310 | 5391d806 | bellard | case 6: |
2311 | 7ae98627 | bellard | if (!ide_if[0].bs && !ide_if[1].bs) |
2312 | c45c3d00 | bellard | ret = 0;
|
2313 | c45c3d00 | bellard | else
|
2314 | 7ae98627 | bellard | ret = s->select; |
2315 | 5391d806 | bellard | break;
|
2316 | 5391d806 | bellard | default:
|
2317 | 5391d806 | bellard | case 7: |
2318 | 66201e2d | bellard | if ((!ide_if[0].bs && !ide_if[1].bs) || |
2319 | 66201e2d | bellard | (s != ide_if && !s->bs)) |
2320 | c45c3d00 | bellard | ret = 0;
|
2321 | c45c3d00 | bellard | else
|
2322 | c45c3d00 | bellard | ret = s->status; |
2323 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
2324 | 5391d806 | bellard | break;
|
2325 | 5391d806 | bellard | } |
2326 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
2327 | 5391d806 | bellard | printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
|
2328 | 5391d806 | bellard | #endif
|
2329 | 5391d806 | bellard | return ret;
|
2330 | 5391d806 | bellard | } |
2331 | 5391d806 | bellard | |
2332 | caed8802 | bellard | static uint32_t ide_status_read(void *opaque, uint32_t addr) |
2333 | 5391d806 | bellard | { |
2334 | 7ae98627 | bellard | IDEState *ide_if = opaque; |
2335 | 7ae98627 | bellard | IDEState *s = ide_if->cur_drive; |
2336 | 5391d806 | bellard | int ret;
|
2337 | 7ae98627 | bellard | |
2338 | 66201e2d | bellard | if ((!ide_if[0].bs && !ide_if[1].bs) || |
2339 | 66201e2d | bellard | (s != ide_if && !s->bs)) |
2340 | 7ae98627 | bellard | ret = 0;
|
2341 | 7ae98627 | bellard | else
|
2342 | 7ae98627 | bellard | ret = s->status; |
2343 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
2344 | 5391d806 | bellard | printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
|
2345 | 5391d806 | bellard | #endif
|
2346 | 5391d806 | bellard | return ret;
|
2347 | 5391d806 | bellard | } |
2348 | 5391d806 | bellard | |
2349 | caed8802 | bellard | static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) |
2350 | 5391d806 | bellard | { |
2351 | caed8802 | bellard | IDEState *ide_if = opaque; |
2352 | 5391d806 | bellard | IDEState *s; |
2353 | 5391d806 | bellard | int i;
|
2354 | 5391d806 | bellard | |
2355 | 5391d806 | bellard | #ifdef DEBUG_IDE
|
2356 | 5391d806 | bellard | printf("ide: write control addr=0x%x val=%02x\n", addr, val);
|
2357 | 5391d806 | bellard | #endif
|
2358 | 5391d806 | bellard | /* common for both drives */
|
2359 | 5391d806 | bellard | if (!(ide_if[0].cmd & IDE_CMD_RESET) && |
2360 | 5391d806 | bellard | (val & IDE_CMD_RESET)) { |
2361 | 5391d806 | bellard | /* reset low to high */
|
2362 | 5391d806 | bellard | for(i = 0;i < 2; i++) { |
2363 | 5391d806 | bellard | s = &ide_if[i]; |
2364 | 5391d806 | bellard | s->status = BUSY_STAT | SEEK_STAT; |
2365 | 5391d806 | bellard | s->error = 0x01;
|
2366 | 5391d806 | bellard | } |
2367 | 5391d806 | bellard | } else if ((ide_if[0].cmd & IDE_CMD_RESET) && |
2368 | 5391d806 | bellard | !(val & IDE_CMD_RESET)) { |
2369 | 5391d806 | bellard | /* high to low */
|
2370 | 5391d806 | bellard | for(i = 0;i < 2; i++) { |
2371 | 5391d806 | bellard | s = &ide_if[i]; |
2372 | 6b136f9e | bellard | if (s->is_cdrom)
|
2373 | 6b136f9e | bellard | s->status = 0x00; /* NOTE: READY is _not_ set */ |
2374 | 6b136f9e | bellard | else
|
2375 | 56bf1d37 | bellard | s->status = READY_STAT | SEEK_STAT; |
2376 | 5391d806 | bellard | ide_set_signature(s); |
2377 | 5391d806 | bellard | } |
2378 | 5391d806 | bellard | } |
2379 | 5391d806 | bellard | |
2380 | 5391d806 | bellard | ide_if[0].cmd = val;
|
2381 | 5391d806 | bellard | ide_if[1].cmd = val;
|
2382 | 5391d806 | bellard | } |
2383 | 5391d806 | bellard | |
2384 | caed8802 | bellard | static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val) |
2385 | 5391d806 | bellard | { |
2386 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2387 | 5391d806 | bellard | uint8_t *p; |
2388 | 5391d806 | bellard | |
2389 | 5391d806 | bellard | p = s->data_ptr; |
2390 | 0c4ad8dc | bellard | *(uint16_t *)p = le16_to_cpu(val); |
2391 | 5391d806 | bellard | p += 2;
|
2392 | 5391d806 | bellard | s->data_ptr = p; |
2393 | 5391d806 | bellard | if (p >= s->data_end)
|
2394 | 5391d806 | bellard | s->end_transfer_func(s); |
2395 | 5391d806 | bellard | } |
2396 | 5391d806 | bellard | |
2397 | caed8802 | bellard | static uint32_t ide_data_readw(void *opaque, uint32_t addr) |
2398 | 5391d806 | bellard | { |
2399 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2400 | 5391d806 | bellard | uint8_t *p; |
2401 | 5391d806 | bellard | int ret;
|
2402 | 5391d806 | bellard | p = s->data_ptr; |
2403 | 0c4ad8dc | bellard | ret = cpu_to_le16(*(uint16_t *)p); |
2404 | 5391d806 | bellard | p += 2;
|
2405 | 5391d806 | bellard | s->data_ptr = p; |
2406 | 5391d806 | bellard | if (p >= s->data_end)
|
2407 | 5391d806 | bellard | s->end_transfer_func(s); |
2408 | 5391d806 | bellard | return ret;
|
2409 | 5391d806 | bellard | } |
2410 | 5391d806 | bellard | |
2411 | caed8802 | bellard | static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val) |
2412 | 5391d806 | bellard | { |
2413 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2414 | 5391d806 | bellard | uint8_t *p; |
2415 | 5391d806 | bellard | |
2416 | 5391d806 | bellard | p = s->data_ptr; |
2417 | 0c4ad8dc | bellard | *(uint32_t *)p = le32_to_cpu(val); |
2418 | 5391d806 | bellard | p += 4;
|
2419 | 5391d806 | bellard | s->data_ptr = p; |
2420 | 5391d806 | bellard | if (p >= s->data_end)
|
2421 | 5391d806 | bellard | s->end_transfer_func(s); |
2422 | 5391d806 | bellard | } |
2423 | 5391d806 | bellard | |
2424 | caed8802 | bellard | static uint32_t ide_data_readl(void *opaque, uint32_t addr) |
2425 | 5391d806 | bellard | { |
2426 | caed8802 | bellard | IDEState *s = ((IDEState *)opaque)->cur_drive; |
2427 | 5391d806 | bellard | uint8_t *p; |
2428 | 5391d806 | bellard | int ret;
|
2429 | 3b46e624 | ths | |
2430 | 5391d806 | bellard | p = s->data_ptr; |
2431 | 0c4ad8dc | bellard | ret = cpu_to_le32(*(uint32_t *)p); |
2432 | 5391d806 | bellard | p += 4;
|
2433 | 5391d806 | bellard | s->data_ptr = p; |
2434 | 5391d806 | bellard | if (p >= s->data_end)
|
2435 | 5391d806 | bellard | s->end_transfer_func(s); |
2436 | 5391d806 | bellard | return ret;
|
2437 | 5391d806 | bellard | } |
2438 | 5391d806 | bellard | |
2439 | a7dfe172 | bellard | static void ide_dummy_transfer_stop(IDEState *s) |
2440 | a7dfe172 | bellard | { |
2441 | a7dfe172 | bellard | s->data_ptr = s->io_buffer; |
2442 | a7dfe172 | bellard | s->data_end = s->io_buffer; |
2443 | a7dfe172 | bellard | s->io_buffer[0] = 0xff; |
2444 | a7dfe172 | bellard | s->io_buffer[1] = 0xff; |
2445 | a7dfe172 | bellard | s->io_buffer[2] = 0xff; |
2446 | a7dfe172 | bellard | s->io_buffer[3] = 0xff; |
2447 | a7dfe172 | bellard | } |
2448 | a7dfe172 | bellard | |
2449 | 5391d806 | bellard | static void ide_reset(IDEState *s) |
2450 | 5391d806 | bellard | { |
2451 | 201a51fc | balrog | if (s->is_cf)
|
2452 | 201a51fc | balrog | s->mult_sectors = 0;
|
2453 | 201a51fc | balrog | else
|
2454 | 201a51fc | balrog | s->mult_sectors = MAX_MULT_SECTORS; |
2455 | 5391d806 | bellard | s->cur_drive = s; |
2456 | 5391d806 | bellard | s->select = 0xa0;
|
2457 | 5391d806 | bellard | s->status = READY_STAT; |
2458 | 5391d806 | bellard | ide_set_signature(s); |
2459 | a7dfe172 | bellard | /* init the transfer handler so that 0xffff is returned on data
|
2460 | a7dfe172 | bellard | accesses */
|
2461 | a7dfe172 | bellard | s->end_transfer_func = ide_dummy_transfer_stop; |
2462 | a7dfe172 | bellard | ide_dummy_transfer_stop(s); |
2463 | 201a51fc | balrog | s->media_changed = 0;
|
2464 | 5391d806 | bellard | } |
2465 | 5391d806 | bellard | |
2466 | 5391d806 | bellard | struct partition {
|
2467 | 5391d806 | bellard | uint8_t boot_ind; /* 0x80 - active */
|
2468 | 5391d806 | bellard | uint8_t head; /* starting head */
|
2469 | 5391d806 | bellard | uint8_t sector; /* starting sector */
|
2470 | 5391d806 | bellard | uint8_t cyl; /* starting cylinder */
|
2471 | 5391d806 | bellard | uint8_t sys_ind; /* What partition type */
|
2472 | 5391d806 | bellard | uint8_t end_head; /* end head */
|
2473 | 5391d806 | bellard | uint8_t end_sector; /* end sector */
|
2474 | 5391d806 | bellard | uint8_t end_cyl; /* end cylinder */
|
2475 | 5391d806 | bellard | uint32_t start_sect; /* starting sector counting from 0 */
|
2476 | 5391d806 | bellard | uint32_t nr_sects; /* nr of sectors in partition */
|
2477 | 5391d806 | bellard | } __attribute__((packed)); |
2478 | 5391d806 | bellard | |
2479 | bf1b938f | bellard | /* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
|
2480 | 5fafdf24 | ths | static int guess_disk_lchs(IDEState *s, |
2481 | bf1b938f | bellard | int *pcylinders, int *pheads, int *psectors) |
2482 | 5391d806 | bellard | { |
2483 | c717d8bf | balrog | uint8_t *buf = s->io_buffer; |
2484 | 46d4767d | bellard | int ret, i, heads, sectors, cylinders;
|
2485 | 5391d806 | bellard | struct partition *p;
|
2486 | 5391d806 | bellard | uint32_t nr_sects; |
2487 | 5391d806 | bellard | |
2488 | 5391d806 | bellard | ret = bdrv_read(s->bs, 0, buf, 1); |
2489 | 33f00271 | balrog | if (ret < 0) { |
2490 | bf1b938f | bellard | return -1; |
2491 | 33f00271 | balrog | } |
2492 | 5391d806 | bellard | /* test msdos magic */
|
2493 | 33f00271 | balrog | if (buf[510] != 0x55 || buf[511] != 0xaa) { |
2494 | bf1b938f | bellard | return -1; |
2495 | 33f00271 | balrog | } |
2496 | 5391d806 | bellard | for(i = 0; i < 4; i++) { |
2497 | 5391d806 | bellard | p = ((struct partition *)(buf + 0x1be)) + i; |
2498 | 0c4ad8dc | bellard | nr_sects = le32_to_cpu(p->nr_sects); |
2499 | 5391d806 | bellard | if (nr_sects && p->end_head) {
|
2500 | 5391d806 | bellard | /* We make the assumption that the partition terminates on
|
2501 | 5391d806 | bellard | a cylinder boundary */
|
2502 | 46d4767d | bellard | heads = p->end_head + 1;
|
2503 | 46d4767d | bellard | sectors = p->end_sector & 63;
|
2504 | 46d4767d | bellard | if (sectors == 0) |
2505 | 46d4767d | bellard | continue;
|
2506 | 46d4767d | bellard | cylinders = s->nb_sectors / (heads * sectors); |
2507 | 46d4767d | bellard | if (cylinders < 1 || cylinders > 16383) |
2508 | 46d4767d | bellard | continue;
|
2509 | bf1b938f | bellard | *pheads = heads; |
2510 | bf1b938f | bellard | *psectors = sectors; |
2511 | bf1b938f | bellard | *pcylinders = cylinders; |
2512 | 5391d806 | bellard | #if 0
|
2513 | 5fafdf24 | ths | printf("guessed geometry: LCHS=%d %d %d\n",
|
2514 | bf1b938f | bellard | cylinders, heads, sectors);
|
2515 | 5391d806 | bellard | #endif
|
2516 | bf1b938f | bellard | return 0; |
2517 | 5391d806 | bellard | } |
2518 | 5391d806 | bellard | } |
2519 | bf1b938f | bellard | return -1; |
2520 | 5391d806 | bellard | } |
2521 | 5391d806 | bellard | |
2522 | 5457c8ce | bellard | static void ide_init2(IDEState *ide_state, |
2523 | 5457c8ce | bellard | BlockDriverState *hd0, BlockDriverState *hd1, |
2524 | d537cf6c | pbrook | qemu_irq irq) |
2525 | 5391d806 | bellard | { |
2526 | 69b91039 | bellard | IDEState *s; |
2527 | aedf5382 | bellard | static int drive_serial = 1; |
2528 | 4dbb0f50 | ths | int i, cylinders, heads, secs, translation, lba_detected = 0; |
2529 | 96b8f136 | ths | uint64_t nb_sectors; |
2530 | 5391d806 | bellard | |
2531 | caed8802 | bellard | for(i = 0; i < 2; i++) { |
2532 | caed8802 | bellard | s = ide_state + i; |
2533 | 1d8cde5b | aurel32 | s->io_buffer = qemu_memalign(512, IDE_DMA_BUF_SECTORS*512 + 4); |
2534 | caed8802 | bellard | if (i == 0) |
2535 | caed8802 | bellard | s->bs = hd0; |
2536 | caed8802 | bellard | else
|
2537 | caed8802 | bellard | s->bs = hd1; |
2538 | 5391d806 | bellard | if (s->bs) {
|
2539 | 5391d806 | bellard | bdrv_get_geometry(s->bs, &nb_sectors); |
2540 | 5391d806 | bellard | s->nb_sectors = nb_sectors; |
2541 | caed8802 | bellard | /* if a geometry hint is available, use it */
|
2542 | caed8802 | bellard | bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs); |
2543 | 4dbb0f50 | ths | translation = bdrv_get_translation_hint(s->bs); |
2544 | caed8802 | bellard | if (cylinders != 0) { |
2545 | 5391d806 | bellard | s->cylinders = cylinders; |
2546 | caed8802 | bellard | s->heads = heads; |
2547 | caed8802 | bellard | s->sectors = secs; |
2548 | caed8802 | bellard | } else {
|
2549 | bf1b938f | bellard | if (guess_disk_lchs(s, &cylinders, &heads, &secs) == 0) { |
2550 | bf1b938f | bellard | if (heads > 16) { |
2551 | bf1b938f | bellard | /* if heads > 16, it means that a BIOS LBA
|
2552 | bf1b938f | bellard | translation was active, so the default
|
2553 | bf1b938f | bellard | hardware geometry is OK */
|
2554 | 4dbb0f50 | ths | lba_detected = 1;
|
2555 | bf1b938f | bellard | goto default_geometry;
|
2556 | bf1b938f | bellard | } else {
|
2557 | bf1b938f | bellard | s->cylinders = cylinders; |
2558 | bf1b938f | bellard | s->heads = heads; |
2559 | bf1b938f | bellard | s->sectors = secs; |
2560 | bf1b938f | bellard | /* disable any translation to be in sync with
|
2561 | bf1b938f | bellard | the logical geometry */
|
2562 | bf1b938f | bellard | if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
2563 | bf1b938f | bellard | bdrv_set_translation_hint(s->bs, |
2564 | bf1b938f | bellard | BIOS_ATA_TRANSLATION_NONE); |
2565 | bf1b938f | bellard | } |
2566 | bf1b938f | bellard | } |
2567 | bf1b938f | bellard | } else {
|
2568 | bf1b938f | bellard | default_geometry:
|
2569 | 46d4767d | bellard | /* if no geometry, use a standard physical disk geometry */
|
2570 | caed8802 | bellard | cylinders = nb_sectors / (16 * 63); |
2571 | caed8802 | bellard | if (cylinders > 16383) |
2572 | caed8802 | bellard | cylinders = 16383;
|
2573 | caed8802 | bellard | else if (cylinders < 2) |
2574 | caed8802 | bellard | cylinders = 2;
|
2575 | caed8802 | bellard | s->cylinders = cylinders; |
2576 | caed8802 | bellard | s->heads = 16;
|
2577 | caed8802 | bellard | s->sectors = 63;
|
2578 | 4dbb0f50 | ths | if ((lba_detected == 1) && (translation == BIOS_ATA_TRANSLATION_AUTO)) { |
2579 | 4dbb0f50 | ths | if ((s->cylinders * s->heads) <= 131072) { |
2580 | 4dbb0f50 | ths | bdrv_set_translation_hint(s->bs, |
2581 | 4dbb0f50 | ths | BIOS_ATA_TRANSLATION_LARGE); |
2582 | 4dbb0f50 | ths | } else {
|
2583 | 4dbb0f50 | ths | bdrv_set_translation_hint(s->bs, |
2584 | 4dbb0f50 | ths | BIOS_ATA_TRANSLATION_LBA); |
2585 | 4dbb0f50 | ths | } |
2586 | 4dbb0f50 | ths | } |
2587 | caed8802 | bellard | } |
2588 | 769bec72 | bellard | bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors); |
2589 | caed8802 | bellard | } |
2590 | caed8802 | bellard | if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
|
2591 | caed8802 | bellard | s->is_cdrom = 1;
|
2592 | bd491d6a | ths | bdrv_set_change_cb(s->bs, cdrom_change_cb, s); |
2593 | 5391d806 | bellard | } |
2594 | 5391d806 | bellard | } |
2595 | aedf5382 | bellard | s->drive_serial = drive_serial++; |
2596 | caed8802 | bellard | s->irq = irq; |
2597 | 5fafdf24 | ths | s->sector_write_timer = qemu_new_timer(vm_clock, |
2598 | a09db21f | bellard | ide_sector_write_timer_cb, s); |
2599 | 5391d806 | bellard | ide_reset(s); |
2600 | 5391d806 | bellard | } |
2601 | 69b91039 | bellard | } |
2602 | 69b91039 | bellard | |
2603 | 34e538ae | bellard | static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2) |
2604 | 69b91039 | bellard | { |
2605 | caed8802 | bellard | register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state); |
2606 | caed8802 | bellard | register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state); |
2607 | caed8802 | bellard | if (iobase2) {
|
2608 | caed8802 | bellard | register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state); |
2609 | caed8802 | bellard | register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state); |
2610 | 5391d806 | bellard | } |
2611 | 3b46e624 | ths | |
2612 | caed8802 | bellard | /* data ports */
|
2613 | caed8802 | bellard | register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state); |
2614 | caed8802 | bellard | register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state); |
2615 | caed8802 | bellard | register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state); |
2616 | caed8802 | bellard | register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state); |
2617 | 5391d806 | bellard | } |
2618 | 69b91039 | bellard | |
2619 | aa941b94 | balrog | /* save per IDE drive data */
|
2620 | aa941b94 | balrog | static void ide_save(QEMUFile* f, IDEState *s) |
2621 | aa941b94 | balrog | { |
2622 | bee8d684 | ths | qemu_put_be32(f, s->mult_sectors); |
2623 | bee8d684 | ths | qemu_put_be32(f, s->identify_set); |
2624 | aa941b94 | balrog | if (s->identify_set) {
|
2625 | aa941b94 | balrog | qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512); |
2626 | aa941b94 | balrog | } |
2627 | aa941b94 | balrog | qemu_put_8s(f, &s->feature); |
2628 | aa941b94 | balrog | qemu_put_8s(f, &s->error); |
2629 | aa941b94 | balrog | qemu_put_be32s(f, &s->nsector); |
2630 | aa941b94 | balrog | qemu_put_8s(f, &s->sector); |
2631 | aa941b94 | balrog | qemu_put_8s(f, &s->lcyl); |
2632 | aa941b94 | balrog | qemu_put_8s(f, &s->hcyl); |
2633 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_feature); |
2634 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_nsector); |
2635 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_sector); |
2636 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_lcyl); |
2637 | aa941b94 | balrog | qemu_put_8s(f, &s->hob_hcyl); |
2638 | aa941b94 | balrog | qemu_put_8s(f, &s->select); |
2639 | aa941b94 | balrog | qemu_put_8s(f, &s->status); |
2640 | aa941b94 | balrog | qemu_put_8s(f, &s->lba48); |
2641 | aa941b94 | balrog | |
2642 | aa941b94 | balrog | qemu_put_8s(f, &s->sense_key); |
2643 | aa941b94 | balrog | qemu_put_8s(f, &s->asc); |
2644 | aa941b94 | balrog | /* XXX: if a transfer is pending, we do not save it yet */
|
2645 | aa941b94 | balrog | } |
2646 | aa941b94 | balrog | |
2647 | aa941b94 | balrog | /* load per IDE drive data */
|
2648 | aa941b94 | balrog | static void ide_load(QEMUFile* f, IDEState *s) |
2649 | aa941b94 | balrog | { |
2650 | bee8d684 | ths | s->mult_sectors=qemu_get_be32(f); |
2651 | bee8d684 | ths | s->identify_set=qemu_get_be32(f); |
2652 | aa941b94 | balrog | if (s->identify_set) {
|
2653 | aa941b94 | balrog | qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
|
2654 | aa941b94 | balrog | } |
2655 | aa941b94 | balrog | qemu_get_8s(f, &s->feature); |
2656 | aa941b94 | balrog | qemu_get_8s(f, &s->error); |
2657 | aa941b94 | balrog | qemu_get_be32s(f, &s->nsector); |
2658 | aa941b94 | balrog | qemu_get_8s(f, &s->sector); |
2659 | aa941b94 | balrog | qemu_get_8s(f, &s->lcyl); |
2660 | aa941b94 | balrog | qemu_get_8s(f, &s->hcyl); |
2661 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_feature); |
2662 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_nsector); |
2663 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_sector); |
2664 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_lcyl); |
2665 | aa941b94 | balrog | qemu_get_8s(f, &s->hob_hcyl); |
2666 | aa941b94 | balrog | qemu_get_8s(f, &s->select); |
2667 | aa941b94 | balrog | qemu_get_8s(f, &s->status); |
2668 | aa941b94 | balrog | qemu_get_8s(f, &s->lba48); |
2669 | aa941b94 | balrog | |
2670 | aa941b94 | balrog | qemu_get_8s(f, &s->sense_key); |
2671 | aa941b94 | balrog | qemu_get_8s(f, &s->asc); |
2672 | aa941b94 | balrog | /* XXX: if a transfer is pending, we do not save it yet */
|
2673 | aa941b94 | balrog | } |
2674 | aa941b94 | balrog | |
2675 | 69b91039 | bellard | /***********************************************************/
|
2676 | 34e538ae | bellard | /* ISA IDE definitions */
|
2677 | 34e538ae | bellard | |
2678 | d537cf6c | pbrook | void isa_ide_init(int iobase, int iobase2, qemu_irq irq, |
2679 | 34e538ae | bellard | BlockDriverState *hd0, BlockDriverState *hd1) |
2680 | 34e538ae | bellard | { |
2681 | 34e538ae | bellard | IDEState *ide_state; |
2682 | 34e538ae | bellard | |
2683 | 34e538ae | bellard | ide_state = qemu_mallocz(sizeof(IDEState) * 2); |
2684 | 34e538ae | bellard | if (!ide_state)
|
2685 | 34e538ae | bellard | return;
|
2686 | 3b46e624 | ths | |
2687 | d537cf6c | pbrook | ide_init2(ide_state, hd0, hd1, irq); |
2688 | 34e538ae | bellard | ide_init_ioport(ide_state, iobase, iobase2); |
2689 | 34e538ae | bellard | } |
2690 | 34e538ae | bellard | |
2691 | 34e538ae | bellard | /***********************************************************/
|
2692 | 69b91039 | bellard | /* PCI IDE definitions */
|
2693 | 69b91039 | bellard | |
2694 | 5457c8ce | bellard | static void cmd646_update_irq(PCIIDEState *d); |
2695 | 5457c8ce | bellard | |
2696 | 5fafdf24 | ths | static void ide_map(PCIDevice *pci_dev, int region_num, |
2697 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type)
|
2698 | 69b91039 | bellard | { |
2699 | 69b91039 | bellard | PCIIDEState *d = (PCIIDEState *)pci_dev; |
2700 | 69b91039 | bellard | IDEState *ide_state; |
2701 | 69b91039 | bellard | |
2702 | 69b91039 | bellard | if (region_num <= 3) { |
2703 | 69b91039 | bellard | ide_state = &d->ide_if[(region_num >> 1) * 2]; |
2704 | 69b91039 | bellard | if (region_num & 1) { |
2705 | 69b91039 | bellard | register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state); |
2706 | 69b91039 | bellard | register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state); |
2707 | 69b91039 | bellard | } else {
|
2708 | 69b91039 | bellard | register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state); |
2709 | 69b91039 | bellard | register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state); |
2710 | 69b91039 | bellard | |
2711 | 69b91039 | bellard | /* data ports */
|
2712 | 69b91039 | bellard | register_ioport_write(addr, 2, 2, ide_data_writew, ide_state); |
2713 | 69b91039 | bellard | register_ioport_read(addr, 2, 2, ide_data_readw, ide_state); |
2714 | 69b91039 | bellard | register_ioport_write(addr, 4, 4, ide_data_writel, ide_state); |
2715 | 69b91039 | bellard | register_ioport_read(addr, 4, 4, ide_data_readl, ide_state); |
2716 | 69b91039 | bellard | } |
2717 | 69b91039 | bellard | } |
2718 | 69b91039 | bellard | } |
2719 | 69b91039 | bellard | |
2720 | 8ccad811 | bellard | static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb) |
2721 | 98087450 | bellard | { |
2722 | 98087450 | bellard | BMDMAState *bm = s->bmdma; |
2723 | 98087450 | bellard | if(!bm)
|
2724 | 98087450 | bellard | return;
|
2725 | 98087450 | bellard | bm->ide_if = s; |
2726 | 98087450 | bellard | bm->dma_cb = dma_cb; |
2727 | 8ccad811 | bellard | bm->cur_prd_last = 0;
|
2728 | 8ccad811 | bellard | bm->cur_prd_addr = 0;
|
2729 | 8ccad811 | bellard | bm->cur_prd_len = 0;
|
2730 | 98087450 | bellard | if (bm->status & BM_STATUS_DMAING) {
|
2731 | 8ccad811 | bellard | bm->dma_cb(bm, 0);
|
2732 | 98087450 | bellard | } |
2733 | 98087450 | bellard | } |
2734 | 98087450 | bellard | |
2735 | 98087450 | bellard | static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) |
2736 | 98087450 | bellard | { |
2737 | 98087450 | bellard | BMDMAState *bm = opaque; |
2738 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2739 | 98087450 | bellard | printf("%s: 0x%08x\n", __func__, val);
|
2740 | 98087450 | bellard | #endif
|
2741 | 98087450 | bellard | if (!(val & BM_CMD_START)) {
|
2742 | 98087450 | bellard | /* XXX: do it better */
|
2743 | 8ccad811 | bellard | if (bm->status & BM_STATUS_DMAING) {
|
2744 | 8ccad811 | bellard | bm->status &= ~BM_STATUS_DMAING; |
2745 | 8ccad811 | bellard | /* cancel DMA request */
|
2746 | 8ccad811 | bellard | bm->ide_if = NULL;
|
2747 | 8ccad811 | bellard | bm->dma_cb = NULL;
|
2748 | 8ccad811 | bellard | if (bm->aiocb) {
|
2749 | 8ccad811 | bellard | #ifdef DEBUG_AIO
|
2750 | 8ccad811 | bellard | printf("aio_cancel\n");
|
2751 | 8ccad811 | bellard | #endif
|
2752 | 8ccad811 | bellard | bdrv_aio_cancel(bm->aiocb); |
2753 | 8ccad811 | bellard | bm->aiocb = NULL;
|
2754 | 8ccad811 | bellard | } |
2755 | 8ccad811 | bellard | } |
2756 | 98087450 | bellard | bm->cmd = val & 0x09;
|
2757 | 98087450 | bellard | } else {
|
2758 | 8ccad811 | bellard | if (!(bm->status & BM_STATUS_DMAING)) {
|
2759 | 8ccad811 | bellard | bm->status |= BM_STATUS_DMAING; |
2760 | 8ccad811 | bellard | /* start dma transfer if possible */
|
2761 | 8ccad811 | bellard | if (bm->dma_cb)
|
2762 | 8ccad811 | bellard | bm->dma_cb(bm, 0);
|
2763 | 8ccad811 | bellard | } |
2764 | 98087450 | bellard | bm->cmd = val & 0x09;
|
2765 | 98087450 | bellard | } |
2766 | 98087450 | bellard | } |
2767 | 98087450 | bellard | |
2768 | 5457c8ce | bellard | static uint32_t bmdma_readb(void *opaque, uint32_t addr) |
2769 | 98087450 | bellard | { |
2770 | 98087450 | bellard | BMDMAState *bm = opaque; |
2771 | 5457c8ce | bellard | PCIIDEState *pci_dev; |
2772 | 98087450 | bellard | uint32_t val; |
2773 | 3b46e624 | ths | |
2774 | 5457c8ce | bellard | switch(addr & 3) { |
2775 | 5fafdf24 | ths | case 0: |
2776 | 5457c8ce | bellard | val = bm->cmd; |
2777 | 5457c8ce | bellard | break;
|
2778 | 5457c8ce | bellard | case 1: |
2779 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2780 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2781 | 5457c8ce | bellard | val = pci_dev->dev.config[MRDMODE]; |
2782 | 5457c8ce | bellard | } else {
|
2783 | 5457c8ce | bellard | val = 0xff;
|
2784 | 5457c8ce | bellard | } |
2785 | 5457c8ce | bellard | break;
|
2786 | 5457c8ce | bellard | case 2: |
2787 | 5457c8ce | bellard | val = bm->status; |
2788 | 5457c8ce | bellard | break;
|
2789 | 5457c8ce | bellard | case 3: |
2790 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2791 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2792 | 5457c8ce | bellard | if (bm == &pci_dev->bmdma[0]) |
2793 | 5457c8ce | bellard | val = pci_dev->dev.config[UDIDETCR0]; |
2794 | 5457c8ce | bellard | else
|
2795 | 5457c8ce | bellard | val = pci_dev->dev.config[UDIDETCR1]; |
2796 | 5457c8ce | bellard | } else {
|
2797 | 5457c8ce | bellard | val = 0xff;
|
2798 | 5457c8ce | bellard | } |
2799 | 5457c8ce | bellard | break;
|
2800 | 5457c8ce | bellard | default:
|
2801 | 5457c8ce | bellard | val = 0xff;
|
2802 | 5457c8ce | bellard | break;
|
2803 | 5457c8ce | bellard | } |
2804 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2805 | 5457c8ce | bellard | printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
|
2806 | 98087450 | bellard | #endif
|
2807 | 98087450 | bellard | return val;
|
2808 | 98087450 | bellard | } |
2809 | 98087450 | bellard | |
2810 | 5457c8ce | bellard | static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) |
2811 | 98087450 | bellard | { |
2812 | 98087450 | bellard | BMDMAState *bm = opaque; |
2813 | 5457c8ce | bellard | PCIIDEState *pci_dev; |
2814 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2815 | 5457c8ce | bellard | printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
|
2816 | 98087450 | bellard | #endif
|
2817 | 5457c8ce | bellard | switch(addr & 3) { |
2818 | 5457c8ce | bellard | case 1: |
2819 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2820 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2821 | 5fafdf24 | ths | pci_dev->dev.config[MRDMODE] = |
2822 | 5457c8ce | bellard | (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); |
2823 | 5457c8ce | bellard | cmd646_update_irq(pci_dev); |
2824 | 5457c8ce | bellard | } |
2825 | 5457c8ce | bellard | break;
|
2826 | 5457c8ce | bellard | case 2: |
2827 | 5457c8ce | bellard | bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); |
2828 | 5457c8ce | bellard | break;
|
2829 | 5457c8ce | bellard | case 3: |
2830 | 5457c8ce | bellard | pci_dev = bm->pci_dev; |
2831 | 5457c8ce | bellard | if (pci_dev->type == IDE_TYPE_CMD646) {
|
2832 | 5457c8ce | bellard | if (bm == &pci_dev->bmdma[0]) |
2833 | 5457c8ce | bellard | pci_dev->dev.config[UDIDETCR0] = val; |
2834 | 5457c8ce | bellard | else
|
2835 | 5457c8ce | bellard | pci_dev->dev.config[UDIDETCR1] = val; |
2836 | 5457c8ce | bellard | } |
2837 | 5457c8ce | bellard | break;
|
2838 | 5457c8ce | bellard | } |
2839 | 98087450 | bellard | } |
2840 | 98087450 | bellard | |
2841 | 5b9a1293 | aurel32 | static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) |
2842 | 5b9a1293 | aurel32 | { |
2843 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
2844 | 5b9a1293 | aurel32 | uint32_t val; |
2845 | 5b9a1293 | aurel32 | val = (bm->addr >> ((addr & 3) * 8)) & 0xff; |
2846 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
2847 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
2848 | 5b9a1293 | aurel32 | #endif
|
2849 | 5b9a1293 | aurel32 | return val;
|
2850 | 5b9a1293 | aurel32 | } |
2851 | 5b9a1293 | aurel32 | |
2852 | 5b9a1293 | aurel32 | static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val) |
2853 | 5b9a1293 | aurel32 | { |
2854 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
2855 | 5b9a1293 | aurel32 | int shift = (addr & 3) * 8; |
2856 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
2857 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
2858 | 5b9a1293 | aurel32 | #endif
|
2859 | 5b9a1293 | aurel32 | bm->addr &= ~(0xFF << shift);
|
2860 | 5b9a1293 | aurel32 | bm->addr |= ((val & 0xFF) << shift) & ~3; |
2861 | 5b9a1293 | aurel32 | bm->cur_addr = bm->addr; |
2862 | 5b9a1293 | aurel32 | } |
2863 | 5b9a1293 | aurel32 | |
2864 | 5b9a1293 | aurel32 | static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr) |
2865 | 5b9a1293 | aurel32 | { |
2866 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
2867 | 5b9a1293 | aurel32 | uint32_t val; |
2868 | 5b9a1293 | aurel32 | val = (bm->addr >> ((addr & 3) * 8)) & 0xffff; |
2869 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
2870 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
2871 | 5b9a1293 | aurel32 | #endif
|
2872 | 5b9a1293 | aurel32 | return val;
|
2873 | 5b9a1293 | aurel32 | } |
2874 | 5b9a1293 | aurel32 | |
2875 | 5b9a1293 | aurel32 | static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val) |
2876 | 5b9a1293 | aurel32 | { |
2877 | 5b9a1293 | aurel32 | BMDMAState *bm = opaque; |
2878 | 5b9a1293 | aurel32 | int shift = (addr & 3) * 8; |
2879 | 5b9a1293 | aurel32 | #ifdef DEBUG_IDE
|
2880 | 5b9a1293 | aurel32 | printf("%s: 0x%08x\n", __func__, val);
|
2881 | 5b9a1293 | aurel32 | #endif
|
2882 | 5b9a1293 | aurel32 | bm->addr &= ~(0xFFFF << shift);
|
2883 | 5b9a1293 | aurel32 | bm->addr |= ((val & 0xFFFF) << shift) & ~3; |
2884 | 5b9a1293 | aurel32 | bm->cur_addr = bm->addr; |
2885 | 5b9a1293 | aurel32 | } |
2886 | 5b9a1293 | aurel32 | |
2887 | 98087450 | bellard | static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr) |
2888 | 98087450 | bellard | { |
2889 | 98087450 | bellard | BMDMAState *bm = opaque; |
2890 | 98087450 | bellard | uint32_t val; |
2891 | 98087450 | bellard | val = bm->addr; |
2892 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2893 | 98087450 | bellard | printf("%s: 0x%08x\n", __func__, val);
|
2894 | 98087450 | bellard | #endif
|
2895 | 98087450 | bellard | return val;
|
2896 | 98087450 | bellard | } |
2897 | 98087450 | bellard | |
2898 | 98087450 | bellard | static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val) |
2899 | 98087450 | bellard | { |
2900 | 98087450 | bellard | BMDMAState *bm = opaque; |
2901 | 98087450 | bellard | #ifdef DEBUG_IDE
|
2902 | 98087450 | bellard | printf("%s: 0x%08x\n", __func__, val);
|
2903 | 98087450 | bellard | #endif
|
2904 | 98087450 | bellard | bm->addr = val & ~3;
|
2905 | 30c4bbac | ths | bm->cur_addr = bm->addr; |
2906 | 98087450 | bellard | } |
2907 | 98087450 | bellard | |
2908 | 5fafdf24 | ths | static void bmdma_map(PCIDevice *pci_dev, int region_num, |
2909 | 98087450 | bellard | uint32_t addr, uint32_t size, int type)
|
2910 | 98087450 | bellard | { |
2911 | 98087450 | bellard | PCIIDEState *d = (PCIIDEState *)pci_dev; |
2912 | 98087450 | bellard | int i;
|
2913 | 98087450 | bellard | |
2914 | 98087450 | bellard | for(i = 0;i < 2; i++) { |
2915 | 98087450 | bellard | BMDMAState *bm = &d->bmdma[i]; |
2916 | 98087450 | bellard | d->ide_if[2 * i].bmdma = bm;
|
2917 | 98087450 | bellard | d->ide_if[2 * i + 1].bmdma = bm; |
2918 | 5457c8ce | bellard | bm->pci_dev = (PCIIDEState *)pci_dev; |
2919 | 5457c8ce | bellard | |
2920 | 98087450 | bellard | register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); |
2921 | 98087450 | bellard | |
2922 | 5457c8ce | bellard | register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); |
2923 | 5457c8ce | bellard | register_ioport_read(addr, 4, 1, bmdma_readb, bm); |
2924 | 98087450 | bellard | |
2925 | 5b9a1293 | aurel32 | register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); |
2926 | 5b9a1293 | aurel32 | register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); |
2927 | 5b9a1293 | aurel32 | register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); |
2928 | 5b9a1293 | aurel32 | register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); |
2929 | 98087450 | bellard | register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); |
2930 | 98087450 | bellard | register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); |
2931 | 98087450 | bellard | addr += 8;
|
2932 | 98087450 | bellard | } |
2933 | 98087450 | bellard | } |
2934 | 98087450 | bellard | |
2935 | 5457c8ce | bellard | /* XXX: call it also when the MRDMODE is changed from the PCI config
|
2936 | 5457c8ce | bellard | registers */
|
2937 | 5457c8ce | bellard | static void cmd646_update_irq(PCIIDEState *d) |
2938 | 5457c8ce | bellard | { |
2939 | 5457c8ce | bellard | int pci_level;
|
2940 | 5457c8ce | bellard | pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && |
2941 | 5457c8ce | bellard | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || |
2942 | 5457c8ce | bellard | ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && |
2943 | 5457c8ce | bellard | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); |
2944 | d537cf6c | pbrook | qemu_set_irq(d->dev.irq[0], pci_level);
|
2945 | 5457c8ce | bellard | } |
2946 | 5457c8ce | bellard | |
2947 | 5457c8ce | bellard | /* the PCI irq level is the logical OR of the two channels */
|
2948 | 5457c8ce | bellard | static void cmd646_set_irq(void *opaque, int channel, int level) |
2949 | 5457c8ce | bellard | { |
2950 | 5457c8ce | bellard | PCIIDEState *d = opaque; |
2951 | 5457c8ce | bellard | int irq_mask;
|
2952 | 5457c8ce | bellard | |
2953 | 5457c8ce | bellard | irq_mask = MRDMODE_INTR_CH0 << channel; |
2954 | 5457c8ce | bellard | if (level)
|
2955 | 5457c8ce | bellard | d->dev.config[MRDMODE] |= irq_mask; |
2956 | 5457c8ce | bellard | else
|
2957 | 5457c8ce | bellard | d->dev.config[MRDMODE] &= ~irq_mask; |
2958 | 5457c8ce | bellard | cmd646_update_irq(d); |
2959 | 5457c8ce | bellard | } |
2960 | 5457c8ce | bellard | |
2961 | 5457c8ce | bellard | /* CMD646 PCI IDE controller */
|
2962 | 5457c8ce | bellard | void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
|
2963 | 5457c8ce | bellard | int secondary_ide_enabled)
|
2964 | 69b91039 | bellard | { |
2965 | 69b91039 | bellard | PCIIDEState *d; |
2966 | 69b91039 | bellard | uint8_t *pci_conf; |
2967 | 34e538ae | bellard | int i;
|
2968 | d537cf6c | pbrook | qemu_irq *irq; |
2969 | 34e538ae | bellard | |
2970 | 5fafdf24 | ths | d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
|
2971 | 5457c8ce | bellard | sizeof(PCIIDEState),
|
2972 | 5fafdf24 | ths | -1,
|
2973 | 73c11f63 | bellard | NULL, NULL); |
2974 | 5457c8ce | bellard | d->type = IDE_TYPE_CMD646; |
2975 | 69b91039 | bellard | pci_conf = d->dev.config; |
2976 | 5457c8ce | bellard | pci_conf[0x00] = 0x95; // CMD646 |
2977 | 5457c8ce | bellard | pci_conf[0x01] = 0x10; |
2978 | 5457c8ce | bellard | pci_conf[0x02] = 0x46; |
2979 | 5457c8ce | bellard | pci_conf[0x03] = 0x06; |
2980 | 5457c8ce | bellard | |
2981 | 5457c8ce | bellard | pci_conf[0x08] = 0x07; // IDE controller revision |
2982 | 5fafdf24 | ths | pci_conf[0x09] = 0x8f; |
2983 | 5457c8ce | bellard | |
2984 | 69b91039 | bellard | pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
2985 | 69b91039 | bellard | pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
2986 | 5457c8ce | bellard | pci_conf[0x0e] = 0x00; // header_type |
2987 | 3b46e624 | ths | |
2988 | 5457c8ce | bellard | if (secondary_ide_enabled) {
|
2989 | 5457c8ce | bellard | /* XXX: if not enabled, really disable the seconday IDE controller */
|
2990 | 5457c8ce | bellard | pci_conf[0x51] = 0x80; /* enable IDE1 */ |
2991 | 5457c8ce | bellard | } |
2992 | 69b91039 | bellard | |
2993 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 0, 0x8, |
2994 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
2995 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 1, 0x4, |
2996 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
2997 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 2, 0x8, |
2998 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
2999 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 3, 0x4, |
3000 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ide_map); |
3001 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 4, 0x10, |
3002 | 98087450 | bellard | PCI_ADDRESS_SPACE_IO, bmdma_map); |
3003 | 69b91039 | bellard | |
3004 | 34e538ae | bellard | pci_conf[0x3d] = 0x01; // interrupt on pin 1 |
3005 | 3b46e624 | ths | |
3006 | 34e538ae | bellard | for(i = 0; i < 4; i++) |
3007 | 34e538ae | bellard | d->ide_if[i].pci_dev = (PCIDevice *)d; |
3008 | d537cf6c | pbrook | |
3009 | d537cf6c | pbrook | irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
|
3010 | d537cf6c | pbrook | ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]); |
3011 | d537cf6c | pbrook | ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]); |
3012 | 34e538ae | bellard | } |
3013 | 34e538ae | bellard | |
3014 | c3d78997 | bellard | static void pci_ide_save(QEMUFile* f, void *opaque) |
3015 | c3d78997 | bellard | { |
3016 | c3d78997 | bellard | PCIIDEState *d = opaque; |
3017 | c3d78997 | bellard | int i;
|
3018 | c3d78997 | bellard | |
3019 | c3d78997 | bellard | pci_device_save(&d->dev, f); |
3020 | c3d78997 | bellard | |
3021 | c3d78997 | bellard | for(i = 0; i < 2; i++) { |
3022 | c3d78997 | bellard | BMDMAState *bm = &d->bmdma[i]; |
3023 | c3d78997 | bellard | qemu_put_8s(f, &bm->cmd); |
3024 | c3d78997 | bellard | qemu_put_8s(f, &bm->status); |
3025 | c3d78997 | bellard | qemu_put_be32s(f, &bm->addr); |
3026 | c3d78997 | bellard | /* XXX: if a transfer is pending, we do not save it yet */
|
3027 | c3d78997 | bellard | } |
3028 | c3d78997 | bellard | |
3029 | c3d78997 | bellard | /* per IDE interface data */
|
3030 | c3d78997 | bellard | for(i = 0; i < 2; i++) { |
3031 | c3d78997 | bellard | IDEState *s = &d->ide_if[i * 2];
|
3032 | c3d78997 | bellard | uint8_t drive1_selected; |
3033 | c3d78997 | bellard | qemu_put_8s(f, &s->cmd); |
3034 | c3d78997 | bellard | drive1_selected = (s->cur_drive != s); |
3035 | c3d78997 | bellard | qemu_put_8s(f, &drive1_selected); |
3036 | c3d78997 | bellard | } |
3037 | c3d78997 | bellard | |
3038 | c3d78997 | bellard | /* per IDE drive data */
|
3039 | c3d78997 | bellard | for(i = 0; i < 4; i++) { |
3040 | aa941b94 | balrog | ide_save(f, &d->ide_if[i]); |
3041 | c3d78997 | bellard | } |
3042 | c3d78997 | bellard | } |
3043 | c3d78997 | bellard | |
3044 | c3d78997 | bellard | static int pci_ide_load(QEMUFile* f, void *opaque, int version_id) |
3045 | c3d78997 | bellard | { |
3046 | c3d78997 | bellard | PCIIDEState *d = opaque; |
3047 | c3d78997 | bellard | int ret, i;
|
3048 | c3d78997 | bellard | |
3049 | c3d78997 | bellard | if (version_id != 1) |
3050 | c3d78997 | bellard | return -EINVAL;
|
3051 | c3d78997 | bellard | ret = pci_device_load(&d->dev, f); |
3052 | c3d78997 | bellard | if (ret < 0) |
3053 | c3d78997 | bellard | return ret;
|
3054 | c3d78997 | bellard | |
3055 | c3d78997 | bellard | for(i = 0; i < 2; i++) { |
3056 | c3d78997 | bellard | BMDMAState *bm = &d->bmdma[i]; |
3057 | c3d78997 | bellard | qemu_get_8s(f, &bm->cmd); |
3058 | c3d78997 | bellard | qemu_get_8s(f, &bm->status); |
3059 | c3d78997 | bellard | qemu_get_be32s(f, &bm->addr); |
3060 | c3d78997 | bellard | /* XXX: if a transfer is pending, we do not save it yet */
|
3061 | c3d78997 | bellard | } |
3062 | c3d78997 | bellard | |
3063 | c3d78997 | bellard | /* per IDE interface data */
|
3064 | c3d78997 | bellard | for(i = 0; i < 2; i++) { |
3065 | c3d78997 | bellard | IDEState *s = &d->ide_if[i * 2];
|
3066 | c3d78997 | bellard | uint8_t drive1_selected; |
3067 | c3d78997 | bellard | qemu_get_8s(f, &s->cmd); |
3068 | c3d78997 | bellard | qemu_get_8s(f, &drive1_selected); |
3069 | c3d78997 | bellard | s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)]; |
3070 | c3d78997 | bellard | } |
3071 | c3d78997 | bellard | |
3072 | c3d78997 | bellard | /* per IDE drive data */
|
3073 | c3d78997 | bellard | for(i = 0; i < 4; i++) { |
3074 | aa941b94 | balrog | ide_load(f, &d->ide_if[i]); |
3075 | c3d78997 | bellard | } |
3076 | c3d78997 | bellard | return 0; |
3077 | c3d78997 | bellard | } |
3078 | c3d78997 | bellard | |
3079 | e6a71ae3 | ths | static void piix3_reset(PCIIDEState *d) |
3080 | e6a71ae3 | ths | { |
3081 | e6a71ae3 | ths | uint8_t *pci_conf = d->dev.config; |
3082 | e6a71ae3 | ths | |
3083 | e6a71ae3 | ths | pci_conf[0x04] = 0x00; |
3084 | e6a71ae3 | ths | pci_conf[0x05] = 0x00; |
3085 | e6a71ae3 | ths | pci_conf[0x06] = 0x80; /* FBC */ |
3086 | e6a71ae3 | ths | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
3087 | e6a71ae3 | ths | pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ |
3088 | e6a71ae3 | ths | } |
3089 | e6a71ae3 | ths | |
3090 | 34e538ae | bellard | /* hd_table must contain 4 block drivers */
|
3091 | 34e538ae | bellard | /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
|
3092 | d537cf6c | pbrook | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
3093 | d537cf6c | pbrook | qemu_irq *pic) |
3094 | 34e538ae | bellard | { |
3095 | 34e538ae | bellard | PCIIDEState *d; |
3096 | 34e538ae | bellard | uint8_t *pci_conf; |
3097 | 3b46e624 | ths | |
3098 | 34e538ae | bellard | /* register a function 1 of PIIX3 */
|
3099 | 5fafdf24 | ths | d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
|
3100 | 46e50e9d | bellard | sizeof(PCIIDEState),
|
3101 | 502a5395 | pbrook | devfn, |
3102 | 34e538ae | bellard | NULL, NULL); |
3103 | 5457c8ce | bellard | d->type = IDE_TYPE_PIIX3; |
3104 | 5457c8ce | bellard | |
3105 | 34e538ae | bellard | pci_conf = d->dev.config; |
3106 | 34e538ae | bellard | pci_conf[0x00] = 0x86; // Intel |
3107 | 34e538ae | bellard | pci_conf[0x01] = 0x80; |
3108 | 34e538ae | bellard | pci_conf[0x02] = 0x10; |
3109 | 34e538ae | bellard | pci_conf[0x03] = 0x70; |
3110 | 92510b8c | bellard | pci_conf[0x09] = 0x80; // legacy ATA mode |
3111 | 34e538ae | bellard | pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
3112 | 34e538ae | bellard | pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
3113 | 34e538ae | bellard | pci_conf[0x0e] = 0x00; // header_type |
3114 | 34e538ae | bellard | |
3115 | e6a71ae3 | ths | piix3_reset(d); |
3116 | e6a71ae3 | ths | |
3117 | 5fafdf24 | ths | pci_register_io_region((PCIDevice *)d, 4, 0x10, |
3118 | 98087450 | bellard | PCI_ADDRESS_SPACE_IO, bmdma_map); |
3119 | 34e538ae | bellard | |
3120 | d537cf6c | pbrook | ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]); |
3121 | d537cf6c | pbrook | ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]); |
3122 | 34e538ae | bellard | ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); |
3123 | 34e538ae | bellard | ide_init_ioport(&d->ide_if[2], 0x170, 0x376); |
3124 | c3d78997 | bellard | |
3125 | c3d78997 | bellard | register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); |
3126 | 69b91039 | bellard | } |
3127 | 1ade1de2 | bellard | |
3128 | afcc3cdf | ths | /* hd_table must contain 4 block drivers */
|
3129 | afcc3cdf | ths | /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
|
3130 | afcc3cdf | ths | void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
3131 | afcc3cdf | ths | qemu_irq *pic) |
3132 | afcc3cdf | ths | { |
3133 | afcc3cdf | ths | PCIIDEState *d; |
3134 | afcc3cdf | ths | uint8_t *pci_conf; |
3135 | afcc3cdf | ths | |
3136 | afcc3cdf | ths | /* register a function 1 of PIIX4 */
|
3137 | afcc3cdf | ths | d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
|
3138 | afcc3cdf | ths | sizeof(PCIIDEState),
|
3139 | afcc3cdf | ths | devfn, |
3140 | afcc3cdf | ths | NULL, NULL); |
3141 | afcc3cdf | ths | d->type = IDE_TYPE_PIIX4; |
3142 | afcc3cdf | ths | |
3143 | afcc3cdf | ths | pci_conf = d->dev.config; |
3144 | afcc3cdf | ths | pci_conf[0x00] = 0x86; // Intel |
3145 | afcc3cdf | ths | pci_conf[0x01] = 0x80; |
3146 | afcc3cdf | ths | pci_conf[0x02] = 0x11; |
3147 | afcc3cdf | ths | pci_conf[0x03] = 0x71; |
3148 | afcc3cdf | ths | pci_conf[0x09] = 0x80; // legacy ATA mode |
3149 | afcc3cdf | ths | pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
3150 | afcc3cdf | ths | pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
3151 | afcc3cdf | ths | pci_conf[0x0e] = 0x00; // header_type |
3152 | afcc3cdf | ths | |
3153 | afcc3cdf | ths | piix3_reset(d); |
3154 | afcc3cdf | ths | |
3155 | afcc3cdf | ths | pci_register_io_region((PCIDevice *)d, 4, 0x10, |
3156 | afcc3cdf | ths | PCI_ADDRESS_SPACE_IO, bmdma_map); |
3157 | afcc3cdf | ths | |
3158 | afcc3cdf | ths | ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]); |
3159 | afcc3cdf | ths | ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]); |
3160 | afcc3cdf | ths | ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); |
3161 | afcc3cdf | ths | ide_init_ioport(&d->ide_if[2], 0x170, 0x376); |
3162 | afcc3cdf | ths | |
3163 | afcc3cdf | ths | register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); |
3164 | afcc3cdf | ths | } |
3165 | afcc3cdf | ths | |
3166 | 1ade1de2 | bellard | /***********************************************************/
|
3167 | 1ade1de2 | bellard | /* MacIO based PowerPC IDE */
|
3168 | 1ade1de2 | bellard | |
3169 | 1ade1de2 | bellard | /* PowerMac IDE memory IO */
|
3170 | 1ade1de2 | bellard | static void pmac_ide_writeb (void *opaque, |
3171 | 1ade1de2 | bellard | target_phys_addr_t addr, uint32_t val) |
3172 | 1ade1de2 | bellard | { |
3173 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3174 | 1ade1de2 | bellard | switch (addr) {
|
3175 | 1ade1de2 | bellard | case 1 ... 7: |
3176 | 1ade1de2 | bellard | ide_ioport_write(opaque, addr, val); |
3177 | 1ade1de2 | bellard | break;
|
3178 | 1ade1de2 | bellard | case 8: |
3179 | 1ade1de2 | bellard | case 22: |
3180 | 1ade1de2 | bellard | ide_cmd_write(opaque, 0, val);
|
3181 | 1ade1de2 | bellard | break;
|
3182 | 1ade1de2 | bellard | default:
|
3183 | 1ade1de2 | bellard | break;
|
3184 | 1ade1de2 | bellard | } |
3185 | 1ade1de2 | bellard | } |
3186 | 1ade1de2 | bellard | |
3187 | 1ade1de2 | bellard | static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr) |
3188 | 1ade1de2 | bellard | { |
3189 | 1ade1de2 | bellard | uint8_t retval; |
3190 | 1ade1de2 | bellard | |
3191 | 1ade1de2 | bellard | addr = (addr & 0xFFF) >> 4; |
3192 | 1ade1de2 | bellard | switch (addr) {
|
3193 | 1ade1de2 | bellard | case 1 ... 7: |
3194 | 1ade1de2 | bellard | retval = ide_ioport_read(opaque, addr); |
3195 | 1ade1de2 | bellard | break;
|
3196 | 1ade1de2 | bellard | case 8: |
3197 | 1ade1de2 | bellard | case 22: |
3198 | 1ade1de2 | bellard | retval = ide_status_read(opaque, 0);
|
3199 | 1ade1de2 | bellard | break;
|
3200 | 1ade1de2 | bellard | default:
|
3201 | 1ade1de2 | bellard | retval = 0xFF;
|
3202 | 1ade1de2 | bellard | break;
|
3203 | 1ade1de2 | bellard | } |
3204 | 1ade1de2 | bellard | return retval;
|
3205 | 1ade1de2 | bellard | } |
3206 | 1ade1de2 | bellard | |
3207 | 1ade1de2 | bellard | static void pmac_ide_writew (void *opaque, |
3208 | 1ade1de2 | bellard | target_phys_addr_t addr, uint32_t val) |
3209 | 1ade1de2 | bellard | { |
3210 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3211 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3212 | 1ade1de2 | bellard | val = bswap16(val); |
3213 | 1ade1de2 | bellard | #endif
|
3214 | 1ade1de2 | bellard | if (addr == 0) { |
3215 | 1ade1de2 | bellard | ide_data_writew(opaque, 0, val);
|
3216 | 1ade1de2 | bellard | } |
3217 | 1ade1de2 | bellard | } |
3218 | 1ade1de2 | bellard | |
3219 | 1ade1de2 | bellard | static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr) |
3220 | 1ade1de2 | bellard | { |
3221 | 1ade1de2 | bellard | uint16_t retval; |
3222 | 1ade1de2 | bellard | |
3223 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3224 | 1ade1de2 | bellard | if (addr == 0) { |
3225 | 1ade1de2 | bellard | retval = ide_data_readw(opaque, 0);
|
3226 | 1ade1de2 | bellard | } else {
|
3227 | 1ade1de2 | bellard | retval = 0xFFFF;
|
3228 | 1ade1de2 | bellard | } |
3229 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3230 | 1ade1de2 | bellard | retval = bswap16(retval); |
3231 | 1ade1de2 | bellard | #endif
|
3232 | 1ade1de2 | bellard | return retval;
|
3233 | 1ade1de2 | bellard | } |
3234 | 1ade1de2 | bellard | |
3235 | 1ade1de2 | bellard | static void pmac_ide_writel (void *opaque, |
3236 | 1ade1de2 | bellard | target_phys_addr_t addr, uint32_t val) |
3237 | 1ade1de2 | bellard | { |
3238 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3239 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3240 | 1ade1de2 | bellard | val = bswap32(val); |
3241 | 1ade1de2 | bellard | #endif
|
3242 | 1ade1de2 | bellard | if (addr == 0) { |
3243 | 1ade1de2 | bellard | ide_data_writel(opaque, 0, val);
|
3244 | 1ade1de2 | bellard | } |
3245 | 1ade1de2 | bellard | } |
3246 | 1ade1de2 | bellard | |
3247 | 1ade1de2 | bellard | static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr) |
3248 | 1ade1de2 | bellard | { |
3249 | 1ade1de2 | bellard | uint32_t retval; |
3250 | 1ade1de2 | bellard | |
3251 | 5fafdf24 | ths | addr = (addr & 0xFFF) >> 4; |
3252 | 1ade1de2 | bellard | if (addr == 0) { |
3253 | 1ade1de2 | bellard | retval = ide_data_readl(opaque, 0);
|
3254 | 1ade1de2 | bellard | } else {
|
3255 | 1ade1de2 | bellard | retval = 0xFFFFFFFF;
|
3256 | 1ade1de2 | bellard | } |
3257 | 1ade1de2 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
3258 | 1ade1de2 | bellard | retval = bswap32(retval); |
3259 | 1ade1de2 | bellard | #endif
|
3260 | 1ade1de2 | bellard | return retval;
|
3261 | 1ade1de2 | bellard | } |
3262 | 1ade1de2 | bellard | |
3263 | 1ade1de2 | bellard | static CPUWriteMemoryFunc *pmac_ide_write[] = {
|
3264 | 1ade1de2 | bellard | pmac_ide_writeb, |
3265 | 1ade1de2 | bellard | pmac_ide_writew, |
3266 | 1ade1de2 | bellard | pmac_ide_writel, |
3267 | 1ade1de2 | bellard | }; |
3268 | 1ade1de2 | bellard | |
3269 | 1ade1de2 | bellard | static CPUReadMemoryFunc *pmac_ide_read[] = {
|
3270 | 1ade1de2 | bellard | pmac_ide_readb, |
3271 | 1ade1de2 | bellard | pmac_ide_readw, |
3272 | 1ade1de2 | bellard | pmac_ide_readl, |
3273 | 1ade1de2 | bellard | }; |
3274 | 1ade1de2 | bellard | |
3275 | 1ade1de2 | bellard | /* hd_table must contain 4 block drivers */
|
3276 | 1ade1de2 | bellard | /* PowerMac uses memory mapped registers, not I/O. Return the memory
|
3277 | 1ade1de2 | bellard | I/O index to access the ide. */
|
3278 | d537cf6c | pbrook | int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
|
3279 | 1ade1de2 | bellard | { |
3280 | 1ade1de2 | bellard | IDEState *ide_if; |
3281 | 1ade1de2 | bellard | int pmac_ide_memory;
|
3282 | 1ade1de2 | bellard | |
3283 | 1ade1de2 | bellard | ide_if = qemu_mallocz(sizeof(IDEState) * 2); |
3284 | d537cf6c | pbrook | ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq); |
3285 | 3b46e624 | ths | |
3286 | 1ade1de2 | bellard | pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
|
3287 | 1ade1de2 | bellard | pmac_ide_write, &ide_if[0]);
|
3288 | 1ade1de2 | bellard | return pmac_ide_memory;
|
3289 | 1ade1de2 | bellard | } |
3290 | 201a51fc | balrog | |
3291 | 201a51fc | balrog | /***********************************************************/
|
3292 | 201a51fc | balrog | /* CF-ATA Microdrive */
|
3293 | 201a51fc | balrog | |
3294 | 201a51fc | balrog | #define METADATA_SIZE 0x20 |
3295 | 201a51fc | balrog | |
3296 | 201a51fc | balrog | /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
|
3297 | 201a51fc | balrog | struct md_s {
|
3298 | 201a51fc | balrog | IDEState ide[2];
|
3299 | 201a51fc | balrog | struct pcmcia_card_s card;
|
3300 | 201a51fc | balrog | uint32_t attr_base; |
3301 | 201a51fc | balrog | uint32_t io_base; |
3302 | 201a51fc | balrog | |
3303 | 201a51fc | balrog | /* Card state */
|
3304 | 201a51fc | balrog | uint8_t opt; |
3305 | 201a51fc | balrog | uint8_t stat; |
3306 | 201a51fc | balrog | uint8_t pins; |
3307 | 201a51fc | balrog | |
3308 | 201a51fc | balrog | uint8_t ctrl; |
3309 | 201a51fc | balrog | uint16_t io; |
3310 | 201a51fc | balrog | int cycle;
|
3311 | 201a51fc | balrog | }; |
3312 | 201a51fc | balrog | |
3313 | 201a51fc | balrog | /* Register bitfields */
|
3314 | 201a51fc | balrog | enum md_opt {
|
3315 | 201a51fc | balrog | OPT_MODE_MMAP = 0,
|
3316 | 201a51fc | balrog | OPT_MODE_IOMAP16 = 1,
|
3317 | 201a51fc | balrog | OPT_MODE_IOMAP1 = 2,
|
3318 | 201a51fc | balrog | OPT_MODE_IOMAP2 = 3,
|
3319 | 201a51fc | balrog | OPT_MODE = 0x3f,
|
3320 | 201a51fc | balrog | OPT_LEVIREQ = 0x40,
|
3321 | 201a51fc | balrog | OPT_SRESET = 0x80,
|
3322 | 201a51fc | balrog | }; |
3323 | 201a51fc | balrog | enum md_cstat {
|
3324 | 201a51fc | balrog | STAT_INT = 0x02,
|
3325 | 201a51fc | balrog | STAT_PWRDWN = 0x04,
|
3326 | 201a51fc | balrog | STAT_XE = 0x10,
|
3327 | 201a51fc | balrog | STAT_IOIS8 = 0x20,
|
3328 | 201a51fc | balrog | STAT_SIGCHG = 0x40,
|
3329 | 201a51fc | balrog | STAT_CHANGED = 0x80,
|
3330 | 201a51fc | balrog | }; |
3331 | 201a51fc | balrog | enum md_pins {
|
3332 | 201a51fc | balrog | PINS_MRDY = 0x02,
|
3333 | 201a51fc | balrog | PINS_CRDY = 0x20,
|
3334 | 201a51fc | balrog | }; |
3335 | 201a51fc | balrog | enum md_ctrl {
|
3336 | 201a51fc | balrog | CTRL_IEN = 0x02,
|
3337 | 201a51fc | balrog | CTRL_SRST = 0x04,
|
3338 | 201a51fc | balrog | }; |
3339 | 201a51fc | balrog | |
3340 | 201a51fc | balrog | static inline void md_interrupt_update(struct md_s *s) |
3341 | 201a51fc | balrog | { |
3342 | 201a51fc | balrog | if (!s->card.slot)
|
3343 | 201a51fc | balrog | return;
|
3344 | 201a51fc | balrog | |
3345 | 201a51fc | balrog | qemu_set_irq(s->card.slot->irq, |
3346 | 201a51fc | balrog | !(s->stat & STAT_INT) && /* Inverted */
|
3347 | 201a51fc | balrog | !(s->ctrl & (CTRL_IEN | CTRL_SRST)) && |
3348 | 201a51fc | balrog | !(s->opt & OPT_SRESET)); |
3349 | 201a51fc | balrog | } |
3350 | 201a51fc | balrog | |
3351 | 201a51fc | balrog | static void md_set_irq(void *opaque, int irq, int level) |
3352 | 201a51fc | balrog | { |
3353 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3354 | 201a51fc | balrog | if (level)
|
3355 | 201a51fc | balrog | s->stat |= STAT_INT; |
3356 | 201a51fc | balrog | else
|
3357 | 201a51fc | balrog | s->stat &= ~STAT_INT; |
3358 | 201a51fc | balrog | |
3359 | 201a51fc | balrog | md_interrupt_update(s); |
3360 | 201a51fc | balrog | } |
3361 | 201a51fc | balrog | |
3362 | 201a51fc | balrog | static void md_reset(struct md_s *s) |
3363 | 201a51fc | balrog | { |
3364 | 201a51fc | balrog | s->opt = OPT_MODE_MMAP; |
3365 | 201a51fc | balrog | s->stat = 0;
|
3366 | 201a51fc | balrog | s->pins = 0;
|
3367 | 201a51fc | balrog | s->cycle = 0;
|
3368 | 201a51fc | balrog | s->ctrl = 0;
|
3369 | 201a51fc | balrog | ide_reset(s->ide); |
3370 | 201a51fc | balrog | } |
3371 | 201a51fc | balrog | |
3372 | 9e315fa9 | balrog | static uint8_t md_attr_read(void *opaque, uint32_t at) |
3373 | 201a51fc | balrog | { |
3374 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3375 | 201a51fc | balrog | if (at < s->attr_base) {
|
3376 | 201a51fc | balrog | if (at < s->card.cis_len)
|
3377 | 201a51fc | balrog | return s->card.cis[at];
|
3378 | 201a51fc | balrog | else
|
3379 | 201a51fc | balrog | return 0x00; |
3380 | 201a51fc | balrog | } |
3381 | 201a51fc | balrog | |
3382 | 201a51fc | balrog | at -= s->attr_base; |
3383 | 201a51fc | balrog | |
3384 | 201a51fc | balrog | switch (at) {
|
3385 | 201a51fc | balrog | case 0x00: /* Configuration Option Register */ |
3386 | 201a51fc | balrog | return s->opt;
|
3387 | 201a51fc | balrog | case 0x02: /* Card Configuration Status Register */ |
3388 | 201a51fc | balrog | if (s->ctrl & CTRL_IEN)
|
3389 | 201a51fc | balrog | return s->stat & ~STAT_INT;
|
3390 | 201a51fc | balrog | else
|
3391 | 201a51fc | balrog | return s->stat;
|
3392 | 201a51fc | balrog | case 0x04: /* Pin Replacement Register */ |
3393 | 201a51fc | balrog | return (s->pins & PINS_CRDY) | 0x0c; |
3394 | 201a51fc | balrog | case 0x06: /* Socket and Copy Register */ |
3395 | 201a51fc | balrog | return 0x00; |
3396 | 201a51fc | balrog | #ifdef VERBOSE
|
3397 | 201a51fc | balrog | default:
|
3398 | 201a51fc | balrog | printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
|
3399 | 201a51fc | balrog | #endif
|
3400 | 201a51fc | balrog | } |
3401 | 201a51fc | balrog | |
3402 | 201a51fc | balrog | return 0; |
3403 | 201a51fc | balrog | } |
3404 | 201a51fc | balrog | |
3405 | 9e315fa9 | balrog | static void md_attr_write(void *opaque, uint32_t at, uint8_t value) |
3406 | 201a51fc | balrog | { |
3407 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3408 | 201a51fc | balrog | at -= s->attr_base; |
3409 | 201a51fc | balrog | |
3410 | 201a51fc | balrog | switch (at) {
|
3411 | 201a51fc | balrog | case 0x00: /* Configuration Option Register */ |
3412 | 201a51fc | balrog | s->opt = value & 0xcf;
|
3413 | 201a51fc | balrog | if (value & OPT_SRESET)
|
3414 | 201a51fc | balrog | md_reset(s); |
3415 | 201a51fc | balrog | md_interrupt_update(s); |
3416 | 201a51fc | balrog | break;
|
3417 | 201a51fc | balrog | case 0x02: /* Card Configuration Status Register */ |
3418 | 201a51fc | balrog | if ((s->stat ^ value) & STAT_PWRDWN)
|
3419 | 201a51fc | balrog | s->pins |= PINS_CRDY; |
3420 | 201a51fc | balrog | s->stat &= 0x82;
|
3421 | 201a51fc | balrog | s->stat |= value & 0x74;
|
3422 | 201a51fc | balrog | md_interrupt_update(s); |
3423 | 201a51fc | balrog | /* Word 170 in Identify Device must be equal to STAT_XE */
|
3424 | 201a51fc | balrog | break;
|
3425 | 201a51fc | balrog | case 0x04: /* Pin Replacement Register */ |
3426 | 201a51fc | balrog | s->pins &= PINS_CRDY; |
3427 | 201a51fc | balrog | s->pins |= value & PINS_MRDY; |
3428 | 201a51fc | balrog | break;
|
3429 | 201a51fc | balrog | case 0x06: /* Socket and Copy Register */ |
3430 | 201a51fc | balrog | break;
|
3431 | 201a51fc | balrog | default:
|
3432 | 201a51fc | balrog | printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
|
3433 | 201a51fc | balrog | } |
3434 | 201a51fc | balrog | } |
3435 | 201a51fc | balrog | |
3436 | 9e315fa9 | balrog | static uint16_t md_common_read(void *opaque, uint32_t at) |
3437 | 201a51fc | balrog | { |
3438 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3439 | 201a51fc | balrog | uint16_t ret; |
3440 | 201a51fc | balrog | at -= s->io_base; |
3441 | 201a51fc | balrog | |
3442 | 201a51fc | balrog | switch (s->opt & OPT_MODE) {
|
3443 | 201a51fc | balrog | case OPT_MODE_MMAP:
|
3444 | 201a51fc | balrog | if ((at & ~0x3ff) == 0x400) |
3445 | 201a51fc | balrog | at = 0;
|
3446 | 201a51fc | balrog | break;
|
3447 | 201a51fc | balrog | case OPT_MODE_IOMAP16:
|
3448 | 201a51fc | balrog | at &= 0xf;
|
3449 | 201a51fc | balrog | break;
|
3450 | 201a51fc | balrog | case OPT_MODE_IOMAP1:
|
3451 | 201a51fc | balrog | if ((at & ~0xf) == 0x3f0) |
3452 | 201a51fc | balrog | at -= 0x3e8;
|
3453 | 201a51fc | balrog | else if ((at & ~0xf) == 0x1f0) |
3454 | 201a51fc | balrog | at -= 0x1f0;
|
3455 | 201a51fc | balrog | break;
|
3456 | 201a51fc | balrog | case OPT_MODE_IOMAP2:
|
3457 | 201a51fc | balrog | if ((at & ~0xf) == 0x370) |
3458 | 201a51fc | balrog | at -= 0x368;
|
3459 | 201a51fc | balrog | else if ((at & ~0xf) == 0x170) |
3460 | 201a51fc | balrog | at -= 0x170;
|
3461 | 201a51fc | balrog | } |
3462 | 201a51fc | balrog | |
3463 | 201a51fc | balrog | switch (at) {
|
3464 | 201a51fc | balrog | case 0x0: /* Even RD Data */ |
3465 | 201a51fc | balrog | case 0x8: |
3466 | 201a51fc | balrog | return ide_data_readw(s->ide, 0); |
3467 | 201a51fc | balrog | |
3468 | 201a51fc | balrog | /* TODO: 8-bit accesses */
|
3469 | 201a51fc | balrog | if (s->cycle)
|
3470 | 201a51fc | balrog | ret = s->io >> 8;
|
3471 | 201a51fc | balrog | else {
|
3472 | 201a51fc | balrog | s->io = ide_data_readw(s->ide, 0);
|
3473 | 201a51fc | balrog | ret = s->io & 0xff;
|
3474 | 201a51fc | balrog | } |
3475 | 201a51fc | balrog | s->cycle = !s->cycle; |
3476 | 201a51fc | balrog | return ret;
|
3477 | 201a51fc | balrog | case 0x9: /* Odd RD Data */ |
3478 | 201a51fc | balrog | return s->io >> 8; |
3479 | 201a51fc | balrog | case 0xd: /* Error */ |
3480 | 201a51fc | balrog | return ide_ioport_read(s->ide, 0x1); |
3481 | 201a51fc | balrog | case 0xe: /* Alternate Status */ |
3482 | 201a51fc | balrog | if (s->ide->cur_drive->bs)
|
3483 | 201a51fc | balrog | return s->ide->cur_drive->status;
|
3484 | 201a51fc | balrog | else
|
3485 | 201a51fc | balrog | return 0; |
3486 | 201a51fc | balrog | case 0xf: /* Device Address */ |
3487 | 201a51fc | balrog | return 0xc2 | ((~s->ide->select << 2) & 0x3c); |
3488 | 201a51fc | balrog | default:
|
3489 | 201a51fc | balrog | return ide_ioport_read(s->ide, at);
|
3490 | 201a51fc | balrog | } |
3491 | 201a51fc | balrog | |
3492 | 201a51fc | balrog | return 0; |
3493 | 201a51fc | balrog | } |
3494 | 201a51fc | balrog | |
3495 | 9e315fa9 | balrog | static void md_common_write(void *opaque, uint32_t at, uint16_t value) |
3496 | 201a51fc | balrog | { |
3497 | 201a51fc | balrog | struct md_s *s = (struct md_s *) opaque; |
3498 | 201a51fc | balrog | at -= s->io_base; |
3499 | 201a51fc | balrog | |
3500 | 201a51fc | balrog | switch (s->opt & OPT_MODE) {
|
3501 | 201a51fc | balrog | case OPT_MODE_MMAP:
|
3502 | 201a51fc | balrog | if ((at & ~0x3ff) == 0x400) |
3503 | 201a51fc | balrog | at = 0;
|
3504 | 201a51fc | balrog | break;
|
3505 | 201a51fc | balrog | case OPT_MODE_IOMAP16:
|
3506 | 201a51fc | balrog | at &= 0xf;
|
3507 | 201a51fc | balrog | break;
|
3508 | 201a51fc | balrog | case OPT_MODE_IOMAP1:
|
3509 | 201a51fc | balrog | if ((at & ~0xf) == 0x3f0) |
3510 | 201a51fc | balrog | at -= 0x3e8;
|
3511 | 201a51fc | balrog | else if ((at & ~0xf) == 0x1f0) |
3512 | 201a51fc | balrog | at -= 0x1f0;
|
3513 | 201a51fc | balrog | break;
|
3514 | 201a51fc | balrog | case OPT_MODE_IOMAP2:
|
3515 | 201a51fc | balrog | if ((at & ~0xf) == 0x370) |
3516 | 201a51fc | balrog | at -= 0x368;
|
3517 | 201a51fc | balrog | else if ((at & ~0xf) == 0x170) |
3518 | 201a51fc | balrog | at -= 0x170;
|
3519 | 201a51fc | balrog | } |
3520 | 201a51fc | balrog | |
3521 | 201a51fc | balrog | switch (at) {
|
3522 | 201a51fc | balrog | case 0x0: /* Even WR Data */ |
3523 | 201a51fc | balrog | case 0x8: |
3524 | 201a51fc | balrog | ide_data_writew(s->ide, 0, value);
|
3525 | 201a51fc | balrog | break;
|
3526 | 201a51fc | balrog | |
3527 | 201a51fc | balrog | /* TODO: 8-bit accesses */
|
3528 | 201a51fc | balrog | if (s->cycle)
|
3529 | 201a51fc | balrog | ide_data_writew(s->ide, 0, s->io | (value << 8)); |
3530 | 201a51fc | balrog | else
|
3531 | 201a51fc | balrog | s->io = value & 0xff;
|
3532 | 201a51fc | balrog | s->cycle = !s->cycle; |
3533 | 201a51fc | balrog | break;
|
3534 | 201a51fc | balrog | case 0x9: |
3535 | 201a51fc | balrog | s->io = value & 0xff;
|
3536 | 201a51fc | balrog | s->cycle = !s->cycle; |
3537 | 201a51fc | balrog | break;
|
3538 | 201a51fc | balrog | case 0xd: /* Features */ |
3539 | 201a51fc | balrog | ide_ioport_write(s->ide, 0x1, value);
|
3540 | 201a51fc | balrog | break;
|
3541 | 201a51fc | balrog | case 0xe: /* Device Control */ |
3542 | 201a51fc | balrog | s->ctrl = value; |
3543 | 201a51fc | balrog | if (value & CTRL_SRST)
|
3544 | 201a51fc | balrog | md_reset(s); |
3545 | 201a51fc | balrog | md_interrupt_update(s); |
3546 | 201a51fc | balrog | break;
|
3547 | 201a51fc | balrog | default:
|
3548 | 201a51fc | balrog | if (s->stat & STAT_PWRDWN) {
|
3549 | 201a51fc | balrog | s->pins |= PINS_CRDY; |
3550 | 201a51fc | balrog | s->stat &= ~STAT_PWRDWN; |
3551 | 201a51fc | balrog | } |
3552 | 201a51fc | balrog | ide_ioport_write(s->ide, at, value); |
3553 | 201a51fc | balrog | } |
3554 | 201a51fc | balrog | } |
3555 | 201a51fc | balrog | |
3556 | aa941b94 | balrog | static void md_save(QEMUFile *f, void *opaque) |
3557 | aa941b94 | balrog | { |
3558 | aa941b94 | balrog | struct md_s *s = (struct md_s *) opaque; |
3559 | aa941b94 | balrog | int i;
|
3560 | aa941b94 | balrog | uint8_t drive1_selected; |
3561 | aa941b94 | balrog | |
3562 | aa941b94 | balrog | qemu_put_8s(f, &s->opt); |
3563 | aa941b94 | balrog | qemu_put_8s(f, &s->stat); |
3564 | aa941b94 | balrog | qemu_put_8s(f, &s->pins); |
3565 | aa941b94 | balrog | |
3566 | aa941b94 | balrog | qemu_put_8s(f, &s->ctrl); |
3567 | aa941b94 | balrog | qemu_put_be16s(f, &s->io); |
3568 | aa941b94 | balrog | qemu_put_byte(f, s->cycle); |
3569 | aa941b94 | balrog | |
3570 | aa941b94 | balrog | drive1_selected = (s->ide->cur_drive != s->ide); |
3571 | aa941b94 | balrog | qemu_put_8s(f, &s->ide->cmd); |
3572 | aa941b94 | balrog | qemu_put_8s(f, &drive1_selected); |
3573 | aa941b94 | balrog | |
3574 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
3575 | aa941b94 | balrog | ide_save(f, &s->ide[i]); |
3576 | aa941b94 | balrog | } |
3577 | aa941b94 | balrog | |
3578 | aa941b94 | balrog | static int md_load(QEMUFile *f, void *opaque, int version_id) |
3579 | aa941b94 | balrog | { |
3580 | aa941b94 | balrog | struct md_s *s = (struct md_s *) opaque; |
3581 | aa941b94 | balrog | int i;
|
3582 | aa941b94 | balrog | uint8_t drive1_selected; |
3583 | aa941b94 | balrog | |
3584 | aa941b94 | balrog | qemu_get_8s(f, &s->opt); |
3585 | aa941b94 | balrog | qemu_get_8s(f, &s->stat); |
3586 | aa941b94 | balrog | qemu_get_8s(f, &s->pins); |
3587 | aa941b94 | balrog | |
3588 | aa941b94 | balrog | qemu_get_8s(f, &s->ctrl); |
3589 | aa941b94 | balrog | qemu_get_be16s(f, &s->io); |
3590 | aa941b94 | balrog | s->cycle = qemu_get_byte(f); |
3591 | aa941b94 | balrog | |
3592 | aa941b94 | balrog | qemu_get_8s(f, &s->ide->cmd); |
3593 | aa941b94 | balrog | qemu_get_8s(f, &drive1_selected); |
3594 | aa941b94 | balrog | s->ide->cur_drive = &s->ide[(drive1_selected != 0)];
|
3595 | aa941b94 | balrog | |
3596 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
3597 | aa941b94 | balrog | ide_load(f, &s->ide[i]); |
3598 | aa941b94 | balrog | |
3599 | aa941b94 | balrog | return 0; |
3600 | aa941b94 | balrog | } |
3601 | aa941b94 | balrog | |
3602 | aa941b94 | balrog | static int md_iid = 0; |
3603 | aa941b94 | balrog | |
3604 | 201a51fc | balrog | static const uint8_t dscm1xxxx_cis[0x14a] = { |
3605 | 201a51fc | balrog | [0x000] = CISTPL_DEVICE, /* 5V Device Information */ |
3606 | 201a51fc | balrog | [0x002] = 0x03, /* Tuple length = 4 bytes */ |
3607 | 201a51fc | balrog | [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ |
3608 | 201a51fc | balrog | [0x006] = 0x01, /* Size = 2K bytes */ |
3609 | 201a51fc | balrog | [0x008] = CISTPL_ENDMARK,
|
3610 | 201a51fc | balrog | |
3611 | 201a51fc | balrog | [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */ |
3612 | 201a51fc | balrog | [0x00c] = 0x04, /* Tuple length = 4 byest */ |
3613 | 201a51fc | balrog | [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */ |
3614 | 201a51fc | balrog | [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ |
3615 | 201a51fc | balrog | [0x012] = 0x01, /* Size = 2K bytes */ |
3616 | 201a51fc | balrog | [0x014] = CISTPL_ENDMARK,
|
3617 | 201a51fc | balrog | |
3618 | 201a51fc | balrog | [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */ |
3619 | 201a51fc | balrog | [0x018] = 0x02, /* Tuple length = 2 bytes */ |
3620 | 201a51fc | balrog | [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */ |
3621 | 201a51fc | balrog | [0x01c] = 0x01, |
3622 | 201a51fc | balrog | |
3623 | 201a51fc | balrog | [0x01e] = CISTPL_MANFID, /* Manufacture ID */ |
3624 | 201a51fc | balrog | [0x020] = 0x04, /* Tuple length = 4 bytes */ |
3625 | 201a51fc | balrog | [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */ |
3626 | 201a51fc | balrog | [0x024] = 0x00, |
3627 | 201a51fc | balrog | [0x026] = 0x00, /* PLMID_CARD = 0000 */ |
3628 | 201a51fc | balrog | [0x028] = 0x00, |
3629 | 201a51fc | balrog | |
3630 | 201a51fc | balrog | [0x02a] = CISTPL_VERS_1, /* Level 1 Version */ |
3631 | 201a51fc | balrog | [0x02c] = 0x12, /* Tuple length = 23 bytes */ |
3632 | 201a51fc | balrog | [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */ |
3633 | 201a51fc | balrog | [0x030] = 0x01, /* Minor Version = 1 */ |
3634 | 201a51fc | balrog | [0x032] = 'I', |
3635 | 201a51fc | balrog | [0x034] = 'B', |
3636 | 201a51fc | balrog | [0x036] = 'M', |
3637 | 201a51fc | balrog | [0x038] = 0x00, |
3638 | 201a51fc | balrog | [0x03a] = 'm', |
3639 | 201a51fc | balrog | [0x03c] = 'i', |
3640 | 201a51fc | balrog | [0x03e] = 'c', |
3641 | 201a51fc | balrog | [0x040] = 'r', |
3642 | 201a51fc | balrog | [0x042] = 'o', |
3643 | 201a51fc | balrog | [0x044] = 'd', |
3644 | 201a51fc | balrog | [0x046] = 'r', |
3645 | 201a51fc | balrog | [0x048] = 'i', |
3646 | 201a51fc | balrog | [0x04a] = 'v', |
3647 | 201a51fc | balrog | [0x04c] = 'e', |
3648 | 201a51fc | balrog | [0x04e] = 0x00, |
3649 | 201a51fc | balrog | [0x050] = CISTPL_ENDMARK,
|
3650 | 201a51fc | balrog | |
3651 | 201a51fc | balrog | [0x052] = CISTPL_FUNCID, /* Function ID */ |
3652 | 201a51fc | balrog | [0x054] = 0x02, /* Tuple length = 2 bytes */ |
3653 | 201a51fc | balrog | [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */ |
3654 | 201a51fc | balrog | [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */ |
3655 | 201a51fc | balrog | |
3656 | 201a51fc | balrog | [0x05a] = CISTPL_FUNCE, /* Function Extension */ |
3657 | 201a51fc | balrog | [0x05c] = 0x02, /* Tuple length = 2 bytes */ |
3658 | 201a51fc | balrog | [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */ |
3659 | 201a51fc | balrog | [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */ |
3660 | 201a51fc | balrog | |
3661 | 201a51fc | balrog | [0x062] = CISTPL_FUNCE, /* Function Extension */ |
3662 | 201a51fc | balrog | [0x064] = 0x03, /* Tuple length = 3 bytes */ |
3663 | 201a51fc | balrog | [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */ |
3664 | 201a51fc | balrog | [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */ |
3665 | 201a51fc | balrog | [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */ |
3666 | 201a51fc | balrog | |
3667 | 201a51fc | balrog | [0x06c] = CISTPL_CONFIG, /* Configuration */ |
3668 | 201a51fc | balrog | [0x06e] = 0x05, /* Tuple length = 5 bytes */ |
3669 | 201a51fc | balrog | [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */ |
3670 | 201a51fc | balrog | [0x072] = 0x07, /* TPCC_LAST = 7 */ |
3671 | 201a51fc | balrog | [0x074] = 0x00, /* TPCC_RADR = 0200 */ |
3672 | 201a51fc | balrog | [0x076] = 0x02, |
3673 | 201a51fc | balrog | [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */ |
3674 | 201a51fc | balrog | |
3675 | 201a51fc | balrog | [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3676 | 201a51fc | balrog | [0x07c] = 0x0b, /* Tuple length = 11 bytes */ |
3677 | 201a51fc | balrog | [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */ |
3678 | 201a51fc | balrog | [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */ |
3679 | 201a51fc | balrog | [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */ |
3680 | 201a51fc | balrog | [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
3681 | 201a51fc | balrog | [0x086] = 0x55, /* NomV: 5.0 V */ |
3682 | 201a51fc | balrog | [0x088] = 0x4d, /* MinV: 4.5 V */ |
3683 | 201a51fc | balrog | [0x08a] = 0x5d, /* MaxV: 5.5 V */ |
3684 | 201a51fc | balrog | [0x08c] = 0x4e, /* Peakl: 450 mA */ |
3685 | 201a51fc | balrog | [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */ |
3686 | 201a51fc | balrog | [0x090] = 0x00, /* Window descriptor: Window length = 0 */ |
3687 | 201a51fc | balrog | [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */ |
3688 | 201a51fc | balrog | |
3689 | 201a51fc | balrog | [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3690 | 201a51fc | balrog | [0x096] = 0x06, /* Tuple length = 6 bytes */ |
3691 | 201a51fc | balrog | [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */ |
3692 | 201a51fc | balrog | [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
3693 | 201a51fc | balrog | [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
3694 | 201a51fc | balrog | [0x09e] = 0xb5, /* NomV: 3.3 V */ |
3695 | 201a51fc | balrog | [0x0a0] = 0x1e, |
3696 | 201a51fc | balrog | [0x0a2] = 0x3e, /* Peakl: 350 mA */ |
3697 | 201a51fc | balrog | |
3698 | 201a51fc | balrog | [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3699 | 201a51fc | balrog | [0x0a6] = 0x0d, /* Tuple length = 13 bytes */ |
3700 | 201a51fc | balrog | [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */ |
3701 | 201a51fc | balrog | [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
3702 | 201a51fc | balrog | [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
3703 | 201a51fc | balrog | [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
3704 | 201a51fc | balrog | [0x0b0] = 0x55, /* NomV: 5.0 V */ |
3705 | 201a51fc | balrog | [0x0b2] = 0x4d, /* MinV: 4.5 V */ |
3706 | 201a51fc | balrog | [0x0b4] = 0x5d, /* MaxV: 5.5 V */ |
3707 | 201a51fc | balrog | [0x0b6] = 0x4e, /* Peakl: 450 mA */ |
3708 | 201a51fc | balrog | [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */ |
3709 | 201a51fc | balrog | [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */ |
3710 | 201a51fc | balrog | [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */ |
3711 | 201a51fc | balrog | [0x0be] = 0xff, /* IRQ8..IRQ15 supported */ |
3712 | 201a51fc | balrog | [0x0c0] = 0x20, /* TPCE_MI = support power down mode */ |
3713 | 201a51fc | balrog | |
3714 | 201a51fc | balrog | [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3715 | 201a51fc | balrog | [0x0c4] = 0x06, /* Tuple length = 6 bytes */ |
3716 | 201a51fc | balrog | [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */ |
3717 | 201a51fc | balrog | [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
3718 | 201a51fc | balrog | [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
3719 | 201a51fc | balrog | [0x0cc] = 0xb5, /* NomV: 3.3 V */ |
3720 | 201a51fc | balrog | [0x0ce] = 0x1e, |
3721 | 201a51fc | balrog | [0x0d0] = 0x3e, /* Peakl: 350 mA */ |
3722 | 201a51fc | balrog | |
3723 | 201a51fc | balrog | [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3724 | 201a51fc | balrog | [0x0d4] = 0x12, /* Tuple length = 18 bytes */ |
3725 | 201a51fc | balrog | [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */ |
3726 | 201a51fc | balrog | [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
3727 | 201a51fc | balrog | [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
3728 | 201a51fc | balrog | [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
3729 | 201a51fc | balrog | [0x0de] = 0x55, /* NomV: 5.0 V */ |
3730 | 201a51fc | balrog | [0x0e0] = 0x4d, /* MinV: 4.5 V */ |
3731 | 201a51fc | balrog | [0x0e2] = 0x5d, /* MaxV: 5.5 V */ |
3732 | 201a51fc | balrog | [0x0e4] = 0x4e, /* Peakl: 450 mA */ |
3733 | 201a51fc | balrog | [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ |
3734 | 201a51fc | balrog | [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */ |
3735 | 201a51fc | balrog | [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */ |
3736 | 201a51fc | balrog | [0x0ec] = 0x01, |
3737 | 201a51fc | balrog | [0x0ee] = 0x07, /* Address block length = 8 */ |
3738 | 201a51fc | balrog | [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */ |
3739 | 201a51fc | balrog | [0x0f2] = 0x03, |
3740 | 201a51fc | balrog | [0x0f4] = 0x01, /* Address block length = 2 */ |
3741 | 201a51fc | balrog | [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ |
3742 | 201a51fc | balrog | [0x0f8] = 0x20, /* TPCE_MI = support power down mode */ |
3743 | 201a51fc | balrog | |
3744 | 201a51fc | balrog | [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3745 | 201a51fc | balrog | [0x0fc] = 0x06, /* Tuple length = 6 bytes */ |
3746 | 201a51fc | balrog | [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */ |
3747 | 201a51fc | balrog | [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
3748 | 201a51fc | balrog | [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
3749 | 201a51fc | balrog | [0x104] = 0xb5, /* NomV: 3.3 V */ |
3750 | 201a51fc | balrog | [0x106] = 0x1e, |
3751 | 201a51fc | balrog | [0x108] = 0x3e, /* Peakl: 350 mA */ |
3752 | 201a51fc | balrog | |
3753 | 201a51fc | balrog | [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3754 | 201a51fc | balrog | [0x10c] = 0x12, /* Tuple length = 18 bytes */ |
3755 | 201a51fc | balrog | [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */ |
3756 | 201a51fc | balrog | [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
3757 | 201a51fc | balrog | [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
3758 | 201a51fc | balrog | [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
3759 | 201a51fc | balrog | [0x116] = 0x55, /* NomV: 5.0 V */ |
3760 | 201a51fc | balrog | [0x118] = 0x4d, /* MinV: 4.5 V */ |
3761 | 201a51fc | balrog | [0x11a] = 0x5d, /* MaxV: 5.5 V */ |
3762 | 201a51fc | balrog | [0x11c] = 0x4e, /* Peakl: 450 mA */ |
3763 | 201a51fc | balrog | [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ |
3764 | 201a51fc | balrog | [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */ |
3765 | 201a51fc | balrog | [0x122] = 0x70, /* Field 1 address = 0x0170 */ |
3766 | 201a51fc | balrog | [0x124] = 0x01, |
3767 | 201a51fc | balrog | [0x126] = 0x07, /* Address block length = 8 */ |
3768 | 201a51fc | balrog | [0x128] = 0x76, /* Field 2 address = 0x0376 */ |
3769 | 201a51fc | balrog | [0x12a] = 0x03, |
3770 | 201a51fc | balrog | [0x12c] = 0x01, /* Address block length = 2 */ |
3771 | 201a51fc | balrog | [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ |
3772 | 201a51fc | balrog | [0x130] = 0x20, /* TPCE_MI = support power down mode */ |
3773 | 201a51fc | balrog | |
3774 | 201a51fc | balrog | [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
3775 | 201a51fc | balrog | [0x134] = 0x06, /* Tuple length = 6 bytes */ |
3776 | 201a51fc | balrog | [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */ |
3777 | 201a51fc | balrog | [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
3778 | 201a51fc | balrog | [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
3779 | 201a51fc | balrog | [0x13c] = 0xb5, /* NomV: 3.3 V */ |
3780 | 201a51fc | balrog | [0x13e] = 0x1e, |
3781 | 201a51fc | balrog | [0x140] = 0x3e, /* Peakl: 350 mA */ |
3782 | 201a51fc | balrog | |
3783 | 201a51fc | balrog | [0x142] = CISTPL_NO_LINK, /* No Link */ |
3784 | 201a51fc | balrog | [0x144] = 0x00, /* Tuple length = 0 bytes */ |
3785 | 201a51fc | balrog | |
3786 | 201a51fc | balrog | [0x146] = CISTPL_END, /* Tuple End */ |
3787 | 201a51fc | balrog | }; |
3788 | 201a51fc | balrog | |
3789 | 201a51fc | balrog | static int dscm1xxxx_attach(void *opaque) |
3790 | 201a51fc | balrog | { |
3791 | 201a51fc | balrog | struct md_s *md = (struct md_s *) opaque; |
3792 | 201a51fc | balrog | md->card.attr_read = md_attr_read; |
3793 | 201a51fc | balrog | md->card.attr_write = md_attr_write; |
3794 | 201a51fc | balrog | md->card.common_read = md_common_read; |
3795 | 201a51fc | balrog | md->card.common_write = md_common_write; |
3796 | 201a51fc | balrog | md->card.io_read = md_common_read; |
3797 | 201a51fc | balrog | md->card.io_write = md_common_write; |
3798 | 201a51fc | balrog | |
3799 | 201a51fc | balrog | md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8); |
3800 | 201a51fc | balrog | md->io_base = 0x0;
|
3801 | 201a51fc | balrog | |
3802 | 201a51fc | balrog | md_reset(md); |
3803 | 201a51fc | balrog | md_interrupt_update(md); |
3804 | 201a51fc | balrog | |
3805 | 201a51fc | balrog | md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
|
3806 | 201a51fc | balrog | return 0; |
3807 | 201a51fc | balrog | } |
3808 | 201a51fc | balrog | |
3809 | 201a51fc | balrog | static int dscm1xxxx_detach(void *opaque) |
3810 | 201a51fc | balrog | { |
3811 | 201a51fc | balrog | struct md_s *md = (struct md_s *) opaque; |
3812 | 201a51fc | balrog | md_reset(md); |
3813 | 201a51fc | balrog | return 0; |
3814 | 201a51fc | balrog | } |
3815 | 201a51fc | balrog | |
3816 | 201a51fc | balrog | struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
|
3817 | 201a51fc | balrog | { |
3818 | 201a51fc | balrog | struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s)); |
3819 | 201a51fc | balrog | md->card.state = md; |
3820 | 201a51fc | balrog | md->card.attach = dscm1xxxx_attach; |
3821 | 201a51fc | balrog | md->card.detach = dscm1xxxx_detach; |
3822 | 201a51fc | balrog | md->card.cis = dscm1xxxx_cis; |
3823 | 201a51fc | balrog | md->card.cis_len = sizeof(dscm1xxxx_cis);
|
3824 | 201a51fc | balrog | |
3825 | 201a51fc | balrog | ide_init2(md->ide, bdrv, 0, qemu_allocate_irqs(md_set_irq, md, 1)[0]); |
3826 | 201a51fc | balrog | md->ide->is_cf = 1;
|
3827 | 201a51fc | balrog | md->ide->mdata_size = METADATA_SIZE; |
3828 | 201a51fc | balrog | md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE); |
3829 | aa941b94 | balrog | |
3830 | aa941b94 | balrog | register_savevm("microdrive", md_iid ++, 0, md_save, md_load, md); |
3831 | aa941b94 | balrog | |
3832 | 201a51fc | balrog | return &md->card;
|
3833 | 201a51fc | balrog | } |