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1 | 5fafdf24 | ths | /*
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2 | cdbdb648 | pbrook | * Arm PrimeCell PL190 Vector Interrupt Controller
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3 | cdbdb648 | pbrook | *
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4 | cdbdb648 | pbrook | * Copyright (c) 2006 CodeSourcery.
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5 | cdbdb648 | pbrook | * Written by Paul Brook
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6 | cdbdb648 | pbrook | *
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7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
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8 | cdbdb648 | pbrook | */
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9 | cdbdb648 | pbrook | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "primecell.h" |
12 | 87ecb68b | pbrook | #include "arm-misc.h" |
13 | cdbdb648 | pbrook | |
14 | cdbdb648 | pbrook | /* The number of virtual priority levels. 16 user vectors plus the
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15 | cdbdb648 | pbrook | unvectored IRQ. Chained interrupts would require an additional level
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16 | cdbdb648 | pbrook | if implemented. */
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17 | cdbdb648 | pbrook | |
18 | cdbdb648 | pbrook | #define PL190_NUM_PRIO 17 |
19 | cdbdb648 | pbrook | |
20 | cdbdb648 | pbrook | typedef struct { |
21 | cdbdb648 | pbrook | uint32_t base; |
22 | cdbdb648 | pbrook | DisplayState *ds; |
23 | cdbdb648 | pbrook | uint32_t level; |
24 | cdbdb648 | pbrook | uint32_t soft_level; |
25 | cdbdb648 | pbrook | uint32_t irq_enable; |
26 | cdbdb648 | pbrook | uint32_t fiq_select; |
27 | cdbdb648 | pbrook | uint32_t default_addr; |
28 | cdbdb648 | pbrook | uint8_t vect_control[16];
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29 | cdbdb648 | pbrook | uint32_t vect_addr[PL190_NUM_PRIO]; |
30 | cdbdb648 | pbrook | /* Mask containing interrupts with higher priority than this one. */
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31 | cdbdb648 | pbrook | uint32_t prio_mask[PL190_NUM_PRIO + 1];
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32 | cdbdb648 | pbrook | int protected;
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33 | cdbdb648 | pbrook | /* Current priority level. */
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34 | cdbdb648 | pbrook | int priority;
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35 | cdbdb648 | pbrook | int prev_prio[PL190_NUM_PRIO];
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36 | d537cf6c | pbrook | qemu_irq irq; |
37 | d537cf6c | pbrook | qemu_irq fiq; |
38 | cdbdb648 | pbrook | } pl190_state; |
39 | cdbdb648 | pbrook | |
40 | cdbdb648 | pbrook | static const unsigned char pl190_id[] = |
41 | cdbdb648 | pbrook | { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 }; |
42 | cdbdb648 | pbrook | |
43 | cdbdb648 | pbrook | static inline uint32_t pl190_irq_level(pl190_state *s) |
44 | cdbdb648 | pbrook | { |
45 | cdbdb648 | pbrook | return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
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46 | cdbdb648 | pbrook | } |
47 | cdbdb648 | pbrook | |
48 | cdbdb648 | pbrook | /* Update interrupts. */
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49 | cdbdb648 | pbrook | static void pl190_update(pl190_state *s) |
50 | cdbdb648 | pbrook | { |
51 | cdbdb648 | pbrook | uint32_t level = pl190_irq_level(s); |
52 | cdbdb648 | pbrook | int set;
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53 | cdbdb648 | pbrook | |
54 | cdbdb648 | pbrook | set = (level & s->prio_mask[s->priority]) != 0;
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55 | d537cf6c | pbrook | qemu_set_irq(s->irq, set); |
56 | cdbdb648 | pbrook | set = ((s->level | s->soft_level) & s->fiq_select) != 0;
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57 | d537cf6c | pbrook | qemu_set_irq(s->fiq, set); |
58 | cdbdb648 | pbrook | } |
59 | cdbdb648 | pbrook | |
60 | cdbdb648 | pbrook | static void pl190_set_irq(void *opaque, int irq, int level) |
61 | cdbdb648 | pbrook | { |
62 | cdbdb648 | pbrook | pl190_state *s = (pl190_state *)opaque; |
63 | cdbdb648 | pbrook | |
64 | cdbdb648 | pbrook | if (level)
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65 | cdbdb648 | pbrook | s->level |= 1u << irq;
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66 | cdbdb648 | pbrook | else
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67 | cdbdb648 | pbrook | s->level &= ~(1u << irq);
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68 | cdbdb648 | pbrook | pl190_update(s); |
69 | cdbdb648 | pbrook | } |
70 | cdbdb648 | pbrook | |
71 | cdbdb648 | pbrook | static void pl190_update_vectors(pl190_state *s) |
72 | cdbdb648 | pbrook | { |
73 | cdbdb648 | pbrook | uint32_t mask; |
74 | cdbdb648 | pbrook | int i;
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75 | cdbdb648 | pbrook | int n;
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76 | cdbdb648 | pbrook | |
77 | cdbdb648 | pbrook | mask = 0;
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78 | cdbdb648 | pbrook | for (i = 0; i < 16; i++) |
79 | cdbdb648 | pbrook | { |
80 | cdbdb648 | pbrook | s->prio_mask[i] = mask; |
81 | cdbdb648 | pbrook | if (s->vect_control[i] & 0x20) |
82 | cdbdb648 | pbrook | { |
83 | cdbdb648 | pbrook | n = s->vect_control[i] & 0x1f;
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84 | cdbdb648 | pbrook | mask |= 1 << n;
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85 | cdbdb648 | pbrook | } |
86 | cdbdb648 | pbrook | } |
87 | cdbdb648 | pbrook | s->prio_mask[16] = mask;
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88 | cdbdb648 | pbrook | pl190_update(s); |
89 | cdbdb648 | pbrook | } |
90 | cdbdb648 | pbrook | |
91 | cdbdb648 | pbrook | static uint32_t pl190_read(void *opaque, target_phys_addr_t offset) |
92 | cdbdb648 | pbrook | { |
93 | cdbdb648 | pbrook | pl190_state *s = (pl190_state *)opaque; |
94 | cdbdb648 | pbrook | int i;
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95 | cdbdb648 | pbrook | |
96 | cdbdb648 | pbrook | offset -= s->base; |
97 | cdbdb648 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) { |
98 | cdbdb648 | pbrook | return pl190_id[(offset - 0xfe0) >> 2]; |
99 | cdbdb648 | pbrook | } |
100 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x140) { |
101 | cdbdb648 | pbrook | return s->vect_addr[(offset - 0x100) >> 2]; |
102 | cdbdb648 | pbrook | } |
103 | cdbdb648 | pbrook | if (offset >= 0x200 && offset < 0x240) { |
104 | cdbdb648 | pbrook | return s->vect_control[(offset - 0x200) >> 2]; |
105 | cdbdb648 | pbrook | } |
106 | cdbdb648 | pbrook | switch (offset >> 2) { |
107 | cdbdb648 | pbrook | case 0: /* IRQSTATUS */ |
108 | cdbdb648 | pbrook | return pl190_irq_level(s);
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109 | cdbdb648 | pbrook | case 1: /* FIQSATUS */ |
110 | cdbdb648 | pbrook | return (s->level | s->soft_level) & s->fiq_select;
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111 | cdbdb648 | pbrook | case 2: /* RAWINTR */ |
112 | cdbdb648 | pbrook | return s->level | s->soft_level;
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113 | cdbdb648 | pbrook | case 3: /* INTSELECT */ |
114 | cdbdb648 | pbrook | return s->fiq_select;
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115 | cdbdb648 | pbrook | case 4: /* INTENABLE */ |
116 | cdbdb648 | pbrook | return s->irq_enable;
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117 | cdbdb648 | pbrook | case 6: /* SOFTINT */ |
118 | cdbdb648 | pbrook | return s->soft_level;
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119 | cdbdb648 | pbrook | case 8: /* PROTECTION */ |
120 | cdbdb648 | pbrook | return s->protected;
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121 | cdbdb648 | pbrook | case 12: /* VECTADDR */ |
122 | cdbdb648 | pbrook | /* Read vector address at the start of an ISR. Increases the
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123 | cdbdb648 | pbrook | current priority level to that of the current interrupt. */
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124 | cdbdb648 | pbrook | for (i = 0; i < s->priority; i++) |
125 | cdbdb648 | pbrook | { |
126 | cdbdb648 | pbrook | if ((s->level | s->soft_level) & s->prio_mask[i])
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127 | cdbdb648 | pbrook | break;
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128 | cdbdb648 | pbrook | } |
129 | cdbdb648 | pbrook | /* Reading this value with no pending interrupts is undefined.
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130 | cdbdb648 | pbrook | We return the default address. */
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131 | cdbdb648 | pbrook | if (i == PL190_NUM_PRIO)
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132 | cdbdb648 | pbrook | return s->vect_addr[16]; |
133 | cdbdb648 | pbrook | if (i < s->priority)
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134 | cdbdb648 | pbrook | { |
135 | cdbdb648 | pbrook | s->prev_prio[i] = s->priority; |
136 | cdbdb648 | pbrook | s->priority = i; |
137 | cdbdb648 | pbrook | pl190_update(s); |
138 | cdbdb648 | pbrook | } |
139 | cdbdb648 | pbrook | return s->vect_addr[s->priority];
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140 | cdbdb648 | pbrook | case 13: /* DEFVECTADDR */ |
141 | cdbdb648 | pbrook | return s->vect_addr[16]; |
142 | cdbdb648 | pbrook | default:
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143 | 4d1165fa | pbrook | cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset); |
144 | cdbdb648 | pbrook | return 0; |
145 | cdbdb648 | pbrook | } |
146 | cdbdb648 | pbrook | } |
147 | cdbdb648 | pbrook | |
148 | cdbdb648 | pbrook | static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val) |
149 | cdbdb648 | pbrook | { |
150 | cdbdb648 | pbrook | pl190_state *s = (pl190_state *)opaque; |
151 | cdbdb648 | pbrook | |
152 | cdbdb648 | pbrook | offset -= s->base; |
153 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x140) { |
154 | cdbdb648 | pbrook | s->vect_addr[(offset - 0x100) >> 2] = val; |
155 | cdbdb648 | pbrook | pl190_update_vectors(s); |
156 | cdbdb648 | pbrook | return;
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157 | cdbdb648 | pbrook | } |
158 | cdbdb648 | pbrook | if (offset >= 0x200 && offset < 0x240) { |
159 | cdbdb648 | pbrook | s->vect_control[(offset - 0x200) >> 2] = val; |
160 | cdbdb648 | pbrook | pl190_update_vectors(s); |
161 | cdbdb648 | pbrook | return;
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162 | cdbdb648 | pbrook | } |
163 | cdbdb648 | pbrook | switch (offset >> 2) { |
164 | cdbdb648 | pbrook | case 0: /* SELECT */ |
165 | cdbdb648 | pbrook | /* This is a readonly register, but linux tries to write to it
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166 | cdbdb648 | pbrook | anyway. Ignore the write. */
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167 | cdbdb648 | pbrook | break;
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168 | cdbdb648 | pbrook | case 3: /* INTSELECT */ |
169 | cdbdb648 | pbrook | s->fiq_select = val; |
170 | cdbdb648 | pbrook | break;
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171 | cdbdb648 | pbrook | case 4: /* INTENABLE */ |
172 | cdbdb648 | pbrook | s->irq_enable |= val; |
173 | cdbdb648 | pbrook | break;
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174 | cdbdb648 | pbrook | case 5: /* INTENCLEAR */ |
175 | cdbdb648 | pbrook | s->irq_enable &= ~val; |
176 | cdbdb648 | pbrook | break;
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177 | cdbdb648 | pbrook | case 6: /* SOFTINT */ |
178 | cdbdb648 | pbrook | s->soft_level |= val; |
179 | cdbdb648 | pbrook | break;
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180 | cdbdb648 | pbrook | case 7: /* SOFTINTCLEAR */ |
181 | cdbdb648 | pbrook | s->soft_level &= ~val; |
182 | cdbdb648 | pbrook | break;
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183 | cdbdb648 | pbrook | case 8: /* PROTECTION */ |
184 | cdbdb648 | pbrook | /* TODO: Protection (supervisor only access) is not implemented. */
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185 | cdbdb648 | pbrook | s->protected = val & 1;
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186 | cdbdb648 | pbrook | break;
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187 | cdbdb648 | pbrook | case 12: /* VECTADDR */ |
188 | cdbdb648 | pbrook | /* Restore the previous priority level. The value written is
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189 | cdbdb648 | pbrook | ignored. */
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190 | cdbdb648 | pbrook | if (s->priority < PL190_NUM_PRIO)
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191 | cdbdb648 | pbrook | s->priority = s->prev_prio[s->priority]; |
192 | cdbdb648 | pbrook | break;
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193 | cdbdb648 | pbrook | case 13: /* DEFVECTADDR */ |
194 | cdbdb648 | pbrook | s->default_addr = val; |
195 | cdbdb648 | pbrook | break;
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196 | cdbdb648 | pbrook | case 0xc0: /* ITCR */ |
197 | cdbdb648 | pbrook | if (val)
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198 | cdbdb648 | pbrook | cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
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199 | cdbdb648 | pbrook | break;
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200 | cdbdb648 | pbrook | default:
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201 | 4d1165fa | pbrook | cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset); |
202 | cdbdb648 | pbrook | return;
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203 | cdbdb648 | pbrook | } |
204 | cdbdb648 | pbrook | pl190_update(s); |
205 | cdbdb648 | pbrook | } |
206 | cdbdb648 | pbrook | |
207 | cdbdb648 | pbrook | static CPUReadMemoryFunc *pl190_readfn[] = {
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208 | cdbdb648 | pbrook | pl190_read, |
209 | cdbdb648 | pbrook | pl190_read, |
210 | cdbdb648 | pbrook | pl190_read |
211 | cdbdb648 | pbrook | }; |
212 | cdbdb648 | pbrook | |
213 | cdbdb648 | pbrook | static CPUWriteMemoryFunc *pl190_writefn[] = {
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214 | cdbdb648 | pbrook | pl190_write, |
215 | cdbdb648 | pbrook | pl190_write, |
216 | cdbdb648 | pbrook | pl190_write |
217 | cdbdb648 | pbrook | }; |
218 | cdbdb648 | pbrook | |
219 | 9596ebb7 | pbrook | static void pl190_reset(pl190_state *s) |
220 | cdbdb648 | pbrook | { |
221 | cdbdb648 | pbrook | int i;
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222 | cdbdb648 | pbrook | |
223 | cdbdb648 | pbrook | for (i = 0; i < 16; i++) |
224 | cdbdb648 | pbrook | { |
225 | cdbdb648 | pbrook | s->vect_addr[i] = 0;
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226 | cdbdb648 | pbrook | s->vect_control[i] = 0;
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227 | cdbdb648 | pbrook | } |
228 | cdbdb648 | pbrook | s->vect_addr[16] = 0; |
229 | cdbdb648 | pbrook | s->prio_mask[17] = 0xffffffff; |
230 | cdbdb648 | pbrook | s->priority = PL190_NUM_PRIO; |
231 | cdbdb648 | pbrook | pl190_update_vectors(s); |
232 | cdbdb648 | pbrook | } |
233 | cdbdb648 | pbrook | |
234 | d537cf6c | pbrook | qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq) |
235 | cdbdb648 | pbrook | { |
236 | cdbdb648 | pbrook | pl190_state *s; |
237 | d537cf6c | pbrook | qemu_irq *qi; |
238 | cdbdb648 | pbrook | int iomemtype;
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239 | cdbdb648 | pbrook | |
240 | cdbdb648 | pbrook | s = (pl190_state *)qemu_mallocz(sizeof(pl190_state));
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241 | cdbdb648 | pbrook | iomemtype = cpu_register_io_memory(0, pl190_readfn,
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242 | cdbdb648 | pbrook | pl190_writefn, s); |
243 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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244 | 069dd10a | pbrook | qi = qemu_allocate_irqs(pl190_set_irq, s, 32);
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245 | cdbdb648 | pbrook | s->base = base; |
246 | cdbdb648 | pbrook | s->irq = irq; |
247 | cdbdb648 | pbrook | s->fiq = fiq; |
248 | cdbdb648 | pbrook | pl190_reset(s); |
249 | cdbdb648 | pbrook | /* ??? Save/restore. */
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250 | d537cf6c | pbrook | return qi;
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251 | cdbdb648 | pbrook | } |