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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA255/270 processor support.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | c1713132 | balrog | *
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7 | 3efda49d | balrog | * This code is licenced under the GNU GPL v2.
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8 | c1713132 | balrog | */
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9 | c1713132 | balrog | #ifndef PXA_H
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10 | c1713132 | balrog | # define PXA_H "pxa.h" |
11 | c1713132 | balrog | |
12 | c1713132 | balrog | /* Interrupt numbers */
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13 | c1713132 | balrog | # define PXA2XX_PIC_SSP3 0 |
14 | c1713132 | balrog | # define PXA2XX_PIC_USBH2 2 |
15 | c1713132 | balrog | # define PXA2XX_PIC_USBH1 3 |
16 | 31b87f2e | balrog | # define PXA2XX_PIC_KEYPAD 4 |
17 | c1713132 | balrog | # define PXA2XX_PIC_PWRI2C 6 |
18 | c1713132 | balrog | # define PXA25X_PIC_HWUART 7 |
19 | c1713132 | balrog | # define PXA27X_PIC_OST_4_11 7 |
20 | c1713132 | balrog | # define PXA2XX_PIC_GPIO_0 8 |
21 | c1713132 | balrog | # define PXA2XX_PIC_GPIO_1 9 |
22 | c1713132 | balrog | # define PXA2XX_PIC_GPIO_X 10 |
23 | c1713132 | balrog | # define PXA2XX_PIC_I2S 13 |
24 | c1713132 | balrog | # define PXA26X_PIC_ASSP 15 |
25 | c1713132 | balrog | # define PXA25X_PIC_NSSP 16 |
26 | c1713132 | balrog | # define PXA27X_PIC_SSP2 16 |
27 | c1713132 | balrog | # define PXA2XX_PIC_LCD 17 |
28 | c1713132 | balrog | # define PXA2XX_PIC_I2C 18 |
29 | c1713132 | balrog | # define PXA2XX_PIC_ICP 19 |
30 | c1713132 | balrog | # define PXA2XX_PIC_STUART 20 |
31 | c1713132 | balrog | # define PXA2XX_PIC_BTUART 21 |
32 | c1713132 | balrog | # define PXA2XX_PIC_FFUART 22 |
33 | c1713132 | balrog | # define PXA2XX_PIC_MMC 23 |
34 | c1713132 | balrog | # define PXA2XX_PIC_SSP 24 |
35 | c1713132 | balrog | # define PXA2XX_PIC_DMA 25 |
36 | c1713132 | balrog | # define PXA2XX_PIC_OST_0 26 |
37 | c1713132 | balrog | # define PXA2XX_PIC_RTC1HZ 30 |
38 | c1713132 | balrog | # define PXA2XX_PIC_RTCALARM 31 |
39 | c1713132 | balrog | |
40 | c1713132 | balrog | /* DMA requests */
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41 | c1713132 | balrog | # define PXA2XX_RX_RQ_I2S 2 |
42 | c1713132 | balrog | # define PXA2XX_TX_RQ_I2S 3 |
43 | c1713132 | balrog | # define PXA2XX_RX_RQ_BTUART 4 |
44 | c1713132 | balrog | # define PXA2XX_TX_RQ_BTUART 5 |
45 | c1713132 | balrog | # define PXA2XX_RX_RQ_FFUART 6 |
46 | c1713132 | balrog | # define PXA2XX_TX_RQ_FFUART 7 |
47 | c1713132 | balrog | # define PXA2XX_RX_RQ_SSP1 13 |
48 | c1713132 | balrog | # define PXA2XX_TX_RQ_SSP1 14 |
49 | c1713132 | balrog | # define PXA2XX_RX_RQ_SSP2 15 |
50 | c1713132 | balrog | # define PXA2XX_TX_RQ_SSP2 16 |
51 | c1713132 | balrog | # define PXA2XX_RX_RQ_ICP 17 |
52 | c1713132 | balrog | # define PXA2XX_TX_RQ_ICP 18 |
53 | c1713132 | balrog | # define PXA2XX_RX_RQ_STUART 19 |
54 | c1713132 | balrog | # define PXA2XX_TX_RQ_STUART 20 |
55 | c1713132 | balrog | # define PXA2XX_RX_RQ_MMCI 21 |
56 | c1713132 | balrog | # define PXA2XX_TX_RQ_MMCI 22 |
57 | c1713132 | balrog | # define PXA2XX_USB_RQ(x) ((x) + 24) |
58 | c1713132 | balrog | # define PXA2XX_RX_RQ_SSP3 66 |
59 | c1713132 | balrog | # define PXA2XX_TX_RQ_SSP3 67 |
60 | c1713132 | balrog | |
61 | d95b2f8d | balrog | # define PXA2XX_SDRAM_BASE 0xa0000000 |
62 | d95b2f8d | balrog | # define PXA2XX_INTERNAL_BASE 0x5c000000 |
63 | a07dec22 | balrog | # define PXA2XX_INTERNAL_SIZE 0x40000 |
64 | c1713132 | balrog | |
65 | c1713132 | balrog | /* pxa2xx_pic.c */
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66 | c1713132 | balrog | qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); |
67 | c1713132 | balrog | |
68 | a171fe39 | balrog | /* pxa2xx_timer.c */
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69 | 3f582262 | balrog | void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
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70 | 3f582262 | balrog | void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
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71 | a171fe39 | balrog | |
72 | c1713132 | balrog | /* pxa2xx_gpio.c */
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73 | c1713132 | balrog | struct pxa2xx_gpio_info_s;
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74 | c1713132 | balrog | struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
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75 | c1713132 | balrog | CPUState *env, qemu_irq *pic, int lines);
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76 | 38641a52 | balrog | qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s);
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77 | 38641a52 | balrog | void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, |
78 | 38641a52 | balrog | int line, qemu_irq handler);
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79 | 38641a52 | balrog | void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler); |
80 | c1713132 | balrog | |
81 | c1713132 | balrog | /* pxa2xx_dma.c */
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82 | c1713132 | balrog | struct pxa2xx_dma_state_s;
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83 | c1713132 | balrog | struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
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84 | c1713132 | balrog | qemu_irq irq); |
85 | c1713132 | balrog | struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
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86 | c1713132 | balrog | qemu_irq irq); |
87 | c1713132 | balrog | void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on); |
88 | c1713132 | balrog | |
89 | a171fe39 | balrog | /* pxa2xx_lcd.c */
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90 | a171fe39 | balrog | struct pxa2xx_lcdc_s;
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91 | a171fe39 | balrog | struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
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92 | a171fe39 | balrog | qemu_irq irq, DisplayState *ds); |
93 | 38641a52 | balrog | void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler); |
94 | a171fe39 | balrog | void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
95 | a171fe39 | balrog | |
96 | a171fe39 | balrog | /* pxa2xx_mmci.c */
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97 | a171fe39 | balrog | struct pxa2xx_mmci_s;
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98 | a171fe39 | balrog | struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
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99 | 87ecb68b | pbrook | BlockDriverState *bd, qemu_irq irq, void *dma);
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100 | 02ce600c | balrog | void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, |
101 | 02ce600c | balrog | qemu_irq coverswitch); |
102 | a171fe39 | balrog | |
103 | a171fe39 | balrog | /* pxa2xx_pcmcia.c */
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104 | a171fe39 | balrog | struct pxa2xx_pcmcia_s;
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105 | a171fe39 | balrog | struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
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106 | a171fe39 | balrog | int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card); |
107 | a171fe39 | balrog | int pxa2xx_pcmcia_dettach(void *opaque); |
108 | a171fe39 | balrog | void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); |
109 | a171fe39 | balrog | |
110 | 31b87f2e | balrog | /* pxa2xx_keypad.c */
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111 | 31b87f2e | balrog | struct keymap {
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112 | 31b87f2e | balrog | int column;
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113 | 31b87f2e | balrog | int row;
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114 | 31b87f2e | balrog | }; |
115 | 31b87f2e | balrog | struct pxa2xx_keypad_s;
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116 | 31b87f2e | balrog | struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
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117 | 31b87f2e | balrog | qemu_irq irq); |
118 | 31b87f2e | balrog | void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map, |
119 | 31b87f2e | balrog | int size);
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120 | 31b87f2e | balrog | |
121 | c1713132 | balrog | /* pxa2xx.c */
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122 | c1713132 | balrog | struct pxa2xx_ssp_s;
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123 | c1713132 | balrog | void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, |
124 | c1713132 | balrog | uint32_t (*readfn)(void *opaque),
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125 | c1713132 | balrog | void (*writefn)(void *opaque, uint32_t value), void *opaque); |
126 | c1713132 | balrog | |
127 | 3f582262 | balrog | struct pxa2xx_i2c_s;
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128 | 3f582262 | balrog | struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
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129 | 2a163929 | balrog | qemu_irq irq, uint32_t page_size); |
130 | 3f582262 | balrog | i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s);
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131 | 3f582262 | balrog | |
132 | c1713132 | balrog | struct pxa2xx_i2s_s;
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133 | c1713132 | balrog | struct pxa2xx_fir_s;
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134 | c1713132 | balrog | |
135 | c1713132 | balrog | struct pxa2xx_state_s {
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136 | c1713132 | balrog | CPUState *env; |
137 | c1713132 | balrog | qemu_irq *pic; |
138 | 38641a52 | balrog | qemu_irq reset; |
139 | c1713132 | balrog | struct pxa2xx_dma_state_s *dma;
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140 | c1713132 | balrog | struct pxa2xx_gpio_info_s *gpio;
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141 | a171fe39 | balrog | struct pxa2xx_lcdc_s *lcd;
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142 | c1713132 | balrog | struct pxa2xx_ssp_s **ssp;
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143 | 3f582262 | balrog | struct pxa2xx_i2c_s *i2c[2]; |
144 | a171fe39 | balrog | struct pxa2xx_mmci_s *mmc;
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145 | a171fe39 | balrog | struct pxa2xx_pcmcia_s *pcmcia[2]; |
146 | c1713132 | balrog | struct pxa2xx_i2s_s *i2s;
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147 | c1713132 | balrog | struct pxa2xx_fir_s *fir;
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148 | 31b87f2e | balrog | struct pxa2xx_keypad_s *kp;
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149 | c1713132 | balrog | |
150 | c1713132 | balrog | /* Power management */
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151 | c1713132 | balrog | target_phys_addr_t pm_base; |
152 | c1713132 | balrog | uint32_t pm_regs[0x40];
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153 | c1713132 | balrog | |
154 | c1713132 | balrog | /* Clock management */
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155 | c1713132 | balrog | target_phys_addr_t cm_base; |
156 | c1713132 | balrog | uint32_t cm_regs[4];
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157 | c1713132 | balrog | uint32_t clkcfg; |
158 | c1713132 | balrog | |
159 | c1713132 | balrog | /* Memory management */
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160 | c1713132 | balrog | target_phys_addr_t mm_base; |
161 | c1713132 | balrog | uint32_t mm_regs[0x1a];
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162 | c1713132 | balrog | |
163 | c1713132 | balrog | /* Performance monitoring */
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164 | c1713132 | balrog | uint32_t pmnc; |
165 | c1713132 | balrog | |
166 | c1713132 | balrog | /* Real-Time clock */
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167 | c1713132 | balrog | target_phys_addr_t rtc_base; |
168 | c1713132 | balrog | uint32_t rttr; |
169 | c1713132 | balrog | uint32_t rtsr; |
170 | c1713132 | balrog | uint32_t rtar; |
171 | c1713132 | balrog | uint32_t rdar1; |
172 | c1713132 | balrog | uint32_t rdar2; |
173 | c1713132 | balrog | uint32_t ryar1; |
174 | c1713132 | balrog | uint32_t ryar2; |
175 | c1713132 | balrog | uint32_t swar1; |
176 | c1713132 | balrog | uint32_t swar2; |
177 | c1713132 | balrog | uint32_t piar; |
178 | c1713132 | balrog | uint32_t last_rcnr; |
179 | c1713132 | balrog | uint32_t last_rdcr; |
180 | c1713132 | balrog | uint32_t last_rycr; |
181 | c1713132 | balrog | uint32_t last_swcr; |
182 | c1713132 | balrog | uint32_t last_rtcpicr; |
183 | c1713132 | balrog | int64_t last_hz; |
184 | c1713132 | balrog | int64_t last_sw; |
185 | c1713132 | balrog | int64_t last_pi; |
186 | c1713132 | balrog | QEMUTimer *rtc_hz; |
187 | c1713132 | balrog | QEMUTimer *rtc_rdal1; |
188 | c1713132 | balrog | QEMUTimer *rtc_rdal2; |
189 | c1713132 | balrog | QEMUTimer *rtc_swal1; |
190 | c1713132 | balrog | QEMUTimer *rtc_swal2; |
191 | c1713132 | balrog | QEMUTimer *rtc_pi; |
192 | c1713132 | balrog | }; |
193 | c1713132 | balrog | |
194 | c1713132 | balrog | struct pxa2xx_i2s_s {
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195 | c1713132 | balrog | target_phys_addr_t base; |
196 | c1713132 | balrog | qemu_irq irq; |
197 | c1713132 | balrog | struct pxa2xx_dma_state_s *dma;
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198 | c1713132 | balrog | void (*data_req)(void *, int, int); |
199 | c1713132 | balrog | |
200 | c1713132 | balrog | uint32_t control[2];
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201 | c1713132 | balrog | uint32_t status; |
202 | c1713132 | balrog | uint32_t mask; |
203 | c1713132 | balrog | uint32_t clk; |
204 | c1713132 | balrog | |
205 | c1713132 | balrog | int enable;
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206 | c1713132 | balrog | int rx_len;
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207 | c1713132 | balrog | int tx_len;
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208 | c1713132 | balrog | void (*codec_out)(void *, uint32_t); |
209 | c1713132 | balrog | uint32_t (*codec_in)(void *);
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210 | c1713132 | balrog | void *opaque;
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211 | c1713132 | balrog | |
212 | c1713132 | balrog | int fifo_len;
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213 | c1713132 | balrog | uint32_t fifo[16];
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214 | c1713132 | balrog | }; |
215 | c1713132 | balrog | |
216 | c1713132 | balrog | # define PA_FMT "0x%08lx" |
217 | 444ce241 | bellard | # define REG_FMT "0x" TARGET_FMT_plx |
218 | c1713132 | balrog | |
219 | d95b2f8d | balrog | struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds, |
220 | d95b2f8d | balrog | const char *revision); |
221 | d95b2f8d | balrog | struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds); |
222 | c1713132 | balrog | |
223 | 87ecb68b | pbrook | /* usb-ohci.c */
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224 | 87ecb68b | pbrook | void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, |
225 | 87ecb68b | pbrook | qemu_irq irq); |
226 | 87ecb68b | pbrook | |
227 | c1713132 | balrog | #endif /* PXA_H */ |