root / hw / pxa2xx_pic.c @ 1ffc346f
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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA Programmable Interrupt Controller.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Copyright (c) 2006 Thorsten Zitterell
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6 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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7 | c1713132 | balrog | *
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8 | c1713132 | balrog | * This code is licenced under the GPL.
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9 | c1713132 | balrog | */
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10 | c1713132 | balrog | |
11 | 87ecb68b | pbrook | #include "hw.h" |
12 | 87ecb68b | pbrook | #include "pxa.h" |
13 | c1713132 | balrog | |
14 | c1713132 | balrog | #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ |
15 | c1713132 | balrog | #define ICMR 0x04 /* Interrupt Controller Mask register */ |
16 | c1713132 | balrog | #define ICLR 0x08 /* Interrupt Controller Level register */ |
17 | c1713132 | balrog | #define ICFP 0x0c /* Interrupt Controller FIQ Pending register */ |
18 | c1713132 | balrog | #define ICPR 0x10 /* Interrupt Controller Pending register */ |
19 | c1713132 | balrog | #define ICCR 0x14 /* Interrupt Controller Control register */ |
20 | c1713132 | balrog | #define ICHP 0x18 /* Interrupt Controller Highest Priority register */ |
21 | c1713132 | balrog | #define IPR0 0x1c /* Interrupt Controller Priority register 0 */ |
22 | c1713132 | balrog | #define IPR31 0x98 /* Interrupt Controller Priority register 31 */ |
23 | c1713132 | balrog | #define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */ |
24 | c1713132 | balrog | #define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */ |
25 | c1713132 | balrog | #define ICLR2 0xa4 /* Interrupt Controller Level register 2 */ |
26 | c1713132 | balrog | #define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */ |
27 | c1713132 | balrog | #define ICPR2 0xac /* Interrupt Controller Pending register 2 */ |
28 | c1713132 | balrog | #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ |
29 | c1713132 | balrog | #define IPR39 0xcc /* Interrupt Controller Priority register 39 */ |
30 | c1713132 | balrog | |
31 | c1713132 | balrog | #define PXA2XX_PIC_SRCS 40 |
32 | c1713132 | balrog | |
33 | c1713132 | balrog | struct pxa2xx_pic_state_s {
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34 | c1713132 | balrog | target_phys_addr_t base; |
35 | c1713132 | balrog | CPUState *cpu_env; |
36 | c1713132 | balrog | uint32_t int_enabled[2];
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37 | c1713132 | balrog | uint32_t int_pending[2];
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38 | c1713132 | balrog | uint32_t is_fiq[2];
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39 | c1713132 | balrog | uint32_t int_idle; |
40 | c1713132 | balrog | uint32_t priority[PXA2XX_PIC_SRCS]; |
41 | c1713132 | balrog | }; |
42 | c1713132 | balrog | |
43 | c1713132 | balrog | static void pxa2xx_pic_update(void *opaque) |
44 | c1713132 | balrog | { |
45 | c1713132 | balrog | uint32_t mask[2];
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46 | c1713132 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
47 | c1713132 | balrog | |
48 | c1713132 | balrog | if (s->cpu_env->halted) {
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49 | c1713132 | balrog | mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle); |
50 | c1713132 | balrog | mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle); |
51 | c1713132 | balrog | if (mask[0] || mask[1]) |
52 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB); |
53 | c1713132 | balrog | } |
54 | c1713132 | balrog | |
55 | c1713132 | balrog | mask[0] = s->int_pending[0] & s->int_enabled[0]; |
56 | c1713132 | balrog | mask[1] = s->int_pending[1] & s->int_enabled[1]; |
57 | c1713132 | balrog | |
58 | c1713132 | balrog | if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) |
59 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ); |
60 | c1713132 | balrog | else
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61 | c1713132 | balrog | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ); |
62 | c1713132 | balrog | |
63 | c1713132 | balrog | if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) |
64 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
65 | c1713132 | balrog | else
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66 | c1713132 | balrog | cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
67 | c1713132 | balrog | } |
68 | c1713132 | balrog | |
69 | c1713132 | balrog | /* Note: Here level means state of the signal on a pin, not
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70 | c1713132 | balrog | * IRQ/FIQ distinction as in PXA Developer Manual. */
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71 | c1713132 | balrog | static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) |
72 | c1713132 | balrog | { |
73 | c1713132 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
74 | c1713132 | balrog | int int_set = (irq >= 32); |
75 | c1713132 | balrog | irq &= 31;
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76 | c1713132 | balrog | |
77 | c1713132 | balrog | if (level)
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78 | c1713132 | balrog | s->int_pending[int_set] |= 1 << irq;
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79 | c1713132 | balrog | else
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80 | c1713132 | balrog | s->int_pending[int_set] &= ~(1 << irq);
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81 | c1713132 | balrog | |
82 | c1713132 | balrog | pxa2xx_pic_update(opaque); |
83 | c1713132 | balrog | } |
84 | c1713132 | balrog | |
85 | c1713132 | balrog | static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) { |
86 | c1713132 | balrog | int i, int_set, irq;
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87 | c1713132 | balrog | uint32_t bit, mask[2];
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88 | c1713132 | balrog | uint32_t ichp = 0x003f003f; /* Both IDs invalid */ |
89 | c1713132 | balrog | |
90 | c1713132 | balrog | mask[0] = s->int_pending[0] & s->int_enabled[0]; |
91 | c1713132 | balrog | mask[1] = s->int_pending[1] & s->int_enabled[1]; |
92 | c1713132 | balrog | |
93 | c1713132 | balrog | for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) { |
94 | c1713132 | balrog | irq = s->priority[i] & 0x3f;
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95 | c1713132 | balrog | if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) { |
96 | c1713132 | balrog | /* Source peripheral ID is valid. */
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97 | c1713132 | balrog | bit = 1 << (irq & 31); |
98 | c1713132 | balrog | int_set = (irq >= 32);
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99 | c1713132 | balrog | |
100 | c1713132 | balrog | if (mask[int_set] & bit & s->is_fiq[int_set]) {
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101 | c1713132 | balrog | /* FIQ asserted */
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102 | c1713132 | balrog | ichp &= 0xffff0000;
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103 | c1713132 | balrog | ichp |= (1 << 15) | irq; |
104 | c1713132 | balrog | } |
105 | c1713132 | balrog | |
106 | c1713132 | balrog | if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
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107 | c1713132 | balrog | /* IRQ asserted */
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108 | c1713132 | balrog | ichp &= 0x0000ffff;
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109 | c1713132 | balrog | ichp |= (1 << 31) | (irq << 16); |
110 | c1713132 | balrog | } |
111 | c1713132 | balrog | } |
112 | c1713132 | balrog | } |
113 | c1713132 | balrog | |
114 | c1713132 | balrog | return ichp;
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115 | c1713132 | balrog | } |
116 | c1713132 | balrog | |
117 | c1713132 | balrog | static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset) |
118 | c1713132 | balrog | { |
119 | c1713132 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
120 | c1713132 | balrog | offset -= s->base; |
121 | c1713132 | balrog | |
122 | c1713132 | balrog | switch (offset) {
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123 | c1713132 | balrog | case ICIP: /* IRQ Pending register */ |
124 | c1713132 | balrog | return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0]; |
125 | c1713132 | balrog | case ICIP2: /* IRQ Pending register 2 */ |
126 | c1713132 | balrog | return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1]; |
127 | c1713132 | balrog | case ICMR: /* Mask register */ |
128 | c1713132 | balrog | return s->int_enabled[0]; |
129 | c1713132 | balrog | case ICMR2: /* Mask register 2 */ |
130 | c1713132 | balrog | return s->int_enabled[1]; |
131 | c1713132 | balrog | case ICLR: /* Level register */ |
132 | c1713132 | balrog | return s->is_fiq[0]; |
133 | c1713132 | balrog | case ICLR2: /* Level register 2 */ |
134 | c1713132 | balrog | return s->is_fiq[1]; |
135 | c1713132 | balrog | case ICCR: /* Idle mask */ |
136 | c1713132 | balrog | return (s->int_idle == 0); |
137 | c1713132 | balrog | case ICFP: /* FIQ Pending register */ |
138 | c1713132 | balrog | return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0]; |
139 | c1713132 | balrog | case ICFP2: /* FIQ Pending register 2 */ |
140 | c1713132 | balrog | return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1]; |
141 | c1713132 | balrog | case ICPR: /* Pending register */ |
142 | c1713132 | balrog | return s->int_pending[0]; |
143 | c1713132 | balrog | case ICPR2: /* Pending register 2 */ |
144 | c1713132 | balrog | return s->int_pending[1]; |
145 | c1713132 | balrog | case IPR0 ... IPR31:
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146 | c1713132 | balrog | return s->priority[0 + ((offset - IPR0 ) >> 2)]; |
147 | c1713132 | balrog | case IPR32 ... IPR39:
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148 | c1713132 | balrog | return s->priority[32 + ((offset - IPR32) >> 2)]; |
149 | c1713132 | balrog | case ICHP: /* Highest Priority register */ |
150 | c1713132 | balrog | return pxa2xx_pic_highest(s);
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151 | c1713132 | balrog | default:
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152 | c1713132 | balrog | printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); |
153 | c1713132 | balrog | return 0; |
154 | c1713132 | balrog | } |
155 | c1713132 | balrog | } |
156 | c1713132 | balrog | |
157 | c1713132 | balrog | static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset, |
158 | c1713132 | balrog | uint32_t value) |
159 | c1713132 | balrog | { |
160 | c1713132 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
161 | c1713132 | balrog | offset -= s->base; |
162 | c1713132 | balrog | |
163 | c1713132 | balrog | switch (offset) {
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164 | c1713132 | balrog | case ICMR: /* Mask register */ |
165 | c1713132 | balrog | s->int_enabled[0] = value;
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166 | c1713132 | balrog | break;
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167 | c1713132 | balrog | case ICMR2: /* Mask register 2 */ |
168 | c1713132 | balrog | s->int_enabled[1] = value;
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169 | c1713132 | balrog | break;
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170 | c1713132 | balrog | case ICLR: /* Level register */ |
171 | c1713132 | balrog | s->is_fiq[0] = value;
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172 | c1713132 | balrog | break;
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173 | c1713132 | balrog | case ICLR2: /* Level register 2 */ |
174 | c1713132 | balrog | s->is_fiq[1] = value;
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175 | c1713132 | balrog | break;
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176 | c1713132 | balrog | case ICCR: /* Idle mask */ |
177 | c1713132 | balrog | s->int_idle = (value & 1) ? 0 : ~0; |
178 | c1713132 | balrog | break;
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179 | c1713132 | balrog | case IPR0 ... IPR31:
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180 | c1713132 | balrog | s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f; |
181 | c1713132 | balrog | break;
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182 | c1713132 | balrog | case IPR32 ... IPR39:
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183 | c1713132 | balrog | s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; |
184 | c1713132 | balrog | break;
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185 | c1713132 | balrog | default:
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186 | c1713132 | balrog | printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset); |
187 | c1713132 | balrog | return;
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188 | c1713132 | balrog | } |
189 | c1713132 | balrog | pxa2xx_pic_update(opaque); |
190 | c1713132 | balrog | } |
191 | c1713132 | balrog | |
192 | c1713132 | balrog | /* Interrupt Controller Coprocessor Space Register Mapping */
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193 | c1713132 | balrog | static const int pxa2xx_cp_reg_map[0x10] = { |
194 | c1713132 | balrog | [0x0 ... 0xf] = -1, |
195 | c1713132 | balrog | [0x0] = ICIP,
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196 | c1713132 | balrog | [0x1] = ICMR,
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197 | c1713132 | balrog | [0x2] = ICLR,
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198 | c1713132 | balrog | [0x3] = ICFP,
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199 | c1713132 | balrog | [0x4] = ICPR,
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200 | c1713132 | balrog | [0x5] = ICHP,
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201 | c1713132 | balrog | [0x6] = ICIP2,
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202 | c1713132 | balrog | [0x7] = ICMR2,
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203 | c1713132 | balrog | [0x8] = ICLR2,
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204 | c1713132 | balrog | [0x9] = ICFP2,
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205 | c1713132 | balrog | [0xa] = ICPR2,
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206 | c1713132 | balrog | }; |
207 | c1713132 | balrog | |
208 | c1713132 | balrog | static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) |
209 | c1713132 | balrog | { |
210 | c1713132 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
211 | c1713132 | balrog | target_phys_addr_t offset; |
212 | c1713132 | balrog | |
213 | c1713132 | balrog | if (pxa2xx_cp_reg_map[reg] == -1) { |
214 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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215 | c1713132 | balrog | return 0; |
216 | c1713132 | balrog | } |
217 | c1713132 | balrog | |
218 | c1713132 | balrog | offset = s->base + pxa2xx_cp_reg_map[reg]; |
219 | c1713132 | balrog | return pxa2xx_pic_mem_read(opaque, offset);
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220 | c1713132 | balrog | } |
221 | c1713132 | balrog | |
222 | c1713132 | balrog | static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, |
223 | c1713132 | balrog | uint32_t value) |
224 | c1713132 | balrog | { |
225 | c1713132 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
226 | c1713132 | balrog | target_phys_addr_t offset; |
227 | c1713132 | balrog | |
228 | c1713132 | balrog | if (pxa2xx_cp_reg_map[reg] == -1) { |
229 | c1713132 | balrog | printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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230 | c1713132 | balrog | return;
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231 | c1713132 | balrog | } |
232 | c1713132 | balrog | |
233 | c1713132 | balrog | offset = s->base + pxa2xx_cp_reg_map[reg]; |
234 | c1713132 | balrog | pxa2xx_pic_mem_write(opaque, offset, value); |
235 | c1713132 | balrog | } |
236 | c1713132 | balrog | |
237 | c1713132 | balrog | static CPUReadMemoryFunc *pxa2xx_pic_readfn[] = {
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238 | c1713132 | balrog | pxa2xx_pic_mem_read, |
239 | c1713132 | balrog | pxa2xx_pic_mem_read, |
240 | c1713132 | balrog | pxa2xx_pic_mem_read, |
241 | c1713132 | balrog | }; |
242 | c1713132 | balrog | |
243 | c1713132 | balrog | static CPUWriteMemoryFunc *pxa2xx_pic_writefn[] = {
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244 | c1713132 | balrog | pxa2xx_pic_mem_write, |
245 | c1713132 | balrog | pxa2xx_pic_mem_write, |
246 | c1713132 | balrog | pxa2xx_pic_mem_write, |
247 | c1713132 | balrog | }; |
248 | c1713132 | balrog | |
249 | aa941b94 | balrog | static void pxa2xx_pic_save(QEMUFile *f, void *opaque) |
250 | aa941b94 | balrog | { |
251 | aa941b94 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
252 | aa941b94 | balrog | int i;
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253 | aa941b94 | balrog | |
254 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
255 | aa941b94 | balrog | qemu_put_be32s(f, &s->int_enabled[i]); |
256 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
257 | aa941b94 | balrog | qemu_put_be32s(f, &s->int_pending[i]); |
258 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
259 | aa941b94 | balrog | qemu_put_be32s(f, &s->is_fiq[i]); |
260 | aa941b94 | balrog | qemu_put_be32s(f, &s->int_idle); |
261 | aa941b94 | balrog | for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
262 | aa941b94 | balrog | qemu_put_be32s(f, &s->priority[i]); |
263 | aa941b94 | balrog | } |
264 | aa941b94 | balrog | |
265 | aa941b94 | balrog | static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) |
266 | aa941b94 | balrog | { |
267 | aa941b94 | balrog | struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque; |
268 | aa941b94 | balrog | int i;
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269 | aa941b94 | balrog | |
270 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
271 | aa941b94 | balrog | qemu_get_be32s(f, &s->int_enabled[i]); |
272 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
273 | aa941b94 | balrog | qemu_get_be32s(f, &s->int_pending[i]); |
274 | aa941b94 | balrog | for (i = 0; i < 2; i ++) |
275 | aa941b94 | balrog | qemu_get_be32s(f, &s->is_fiq[i]); |
276 | aa941b94 | balrog | qemu_get_be32s(f, &s->int_idle); |
277 | aa941b94 | balrog | for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
278 | aa941b94 | balrog | qemu_get_be32s(f, &s->priority[i]); |
279 | aa941b94 | balrog | |
280 | aa941b94 | balrog | pxa2xx_pic_update(opaque); |
281 | aa941b94 | balrog | return 0; |
282 | aa941b94 | balrog | } |
283 | aa941b94 | balrog | |
284 | c1713132 | balrog | qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) |
285 | c1713132 | balrog | { |
286 | c1713132 | balrog | struct pxa2xx_pic_state_s *s;
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287 | c1713132 | balrog | int iomemtype;
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288 | c1713132 | balrog | qemu_irq *qi; |
289 | c1713132 | balrog | |
290 | c1713132 | balrog | s = (struct pxa2xx_pic_state_s *)
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291 | c1713132 | balrog | qemu_mallocz(sizeof(struct pxa2xx_pic_state_s)); |
292 | c1713132 | balrog | if (!s)
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293 | c1713132 | balrog | return NULL; |
294 | c1713132 | balrog | |
295 | c1713132 | balrog | s->cpu_env = env; |
296 | c1713132 | balrog | s->base = base; |
297 | c1713132 | balrog | |
298 | c1713132 | balrog | s->int_pending[0] = 0; |
299 | c1713132 | balrog | s->int_pending[1] = 0; |
300 | c1713132 | balrog | s->int_enabled[0] = 0; |
301 | c1713132 | balrog | s->int_enabled[1] = 0; |
302 | c1713132 | balrog | s->is_fiq[0] = 0; |
303 | c1713132 | balrog | s->is_fiq[1] = 0; |
304 | c1713132 | balrog | |
305 | c1713132 | balrog | qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS); |
306 | c1713132 | balrog | |
307 | c1713132 | balrog | /* Enable IC memory-mapped registers access. */
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308 | c1713132 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_pic_readfn,
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309 | c1713132 | balrog | pxa2xx_pic_writefn, s); |
310 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00100000, iomemtype);
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311 | c1713132 | balrog | |
312 | c1713132 | balrog | /* Enable IC coprocessor access. */
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313 | c1713132 | balrog | cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
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314 | c1713132 | balrog | |
315 | aa941b94 | balrog | register_savevm("pxa2xx_pic", 0, 0, pxa2xx_pic_save, pxa2xx_pic_load, s); |
316 | aa941b94 | balrog | |
317 | c1713132 | balrog | return qi;
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318 | c1713132 | balrog | } |