root / hw / sh_intc.h @ 1ffc346f
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1 | 80f515e6 | balrog | #ifndef __SH_INTC_H__
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2 | 80f515e6 | balrog | #define __SH_INTC_H__
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3 | 80f515e6 | balrog | |
4 | 80f515e6 | balrog | typedef unsigned char intc_enum; |
5 | 80f515e6 | balrog | |
6 | 80f515e6 | balrog | struct intc_vect {
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7 | 80f515e6 | balrog | intc_enum enum_id; |
8 | 80f515e6 | balrog | unsigned short vect; |
9 | 80f515e6 | balrog | }; |
10 | 80f515e6 | balrog | |
11 | 80f515e6 | balrog | #define INTC_VECT(enum_id, vect) { enum_id, vect }
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12 | 80f515e6 | balrog | |
13 | 80f515e6 | balrog | struct intc_group {
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14 | 80f515e6 | balrog | intc_enum enum_id; |
15 | 80f515e6 | balrog | intc_enum enum_ids[32];
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16 | 80f515e6 | balrog | }; |
17 | 80f515e6 | balrog | |
18 | 80f515e6 | balrog | #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
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19 | 80f515e6 | balrog | |
20 | 80f515e6 | balrog | struct intc_mask_reg {
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21 | 80f515e6 | balrog | unsigned long set_reg, clr_reg, reg_width; |
22 | 80f515e6 | balrog | intc_enum enum_ids[32];
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23 | 80f515e6 | balrog | unsigned long value; |
24 | 80f515e6 | balrog | }; |
25 | 80f515e6 | balrog | |
26 | 80f515e6 | balrog | struct intc_prio_reg {
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27 | 80f515e6 | balrog | unsigned long set_reg, clr_reg, reg_width, field_width; |
28 | 80f515e6 | balrog | intc_enum enum_ids[16];
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29 | 80f515e6 | balrog | unsigned long value; |
30 | 80f515e6 | balrog | }; |
31 | 80f515e6 | balrog | |
32 | 80f515e6 | balrog | #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) |
33 | 80f515e6 | balrog | |
34 | 80f515e6 | balrog | struct intc_source {
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35 | 80f515e6 | balrog | unsigned short vect; |
36 | 80f515e6 | balrog | intc_enum next_enum_id; |
37 | 80f515e6 | balrog | |
38 | e96e2044 | ths | int asserted; /* emulates the interrupt signal line from device to intc */ |
39 | 80f515e6 | balrog | int enable_count;
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40 | 80f515e6 | balrog | int enable_max;
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41 | e96e2044 | ths | int pending; /* emulates the result of signal and masking */ |
42 | e96e2044 | ths | struct intc_desc *parent;
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43 | 80f515e6 | balrog | }; |
44 | 80f515e6 | balrog | |
45 | 80f515e6 | balrog | struct intc_desc {
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46 | 80f515e6 | balrog | struct intc_source *sources;
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47 | 80f515e6 | balrog | int nr_sources;
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48 | 80f515e6 | balrog | struct intc_mask_reg *mask_regs;
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49 | 80f515e6 | balrog | int nr_mask_regs;
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50 | 80f515e6 | balrog | struct intc_prio_reg *prio_regs;
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51 | 80f515e6 | balrog | int nr_prio_regs;
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52 | 80f515e6 | balrog | |
53 | 80f515e6 | balrog | int iomemtype;
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54 | e96e2044 | ths | int pending; /* number of interrupt sources that has pending set */ |
55 | 80f515e6 | balrog | }; |
56 | 80f515e6 | balrog | |
57 | e96e2044 | ths | int sh_intc_get_pending_vector(struct intc_desc *desc, int imask); |
58 | 80f515e6 | balrog | struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id); |
59 | e96e2044 | ths | void sh_intc_toggle_source(struct intc_source *source, |
60 | e96e2044 | ths | int enable_adj, int assert_adj); |
61 | 80f515e6 | balrog | |
62 | 80f515e6 | balrog | void sh_intc_register_sources(struct intc_desc *desc, |
63 | 80f515e6 | balrog | struct intc_vect *vectors,
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64 | 80f515e6 | balrog | int nr_vectors,
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65 | 80f515e6 | balrog | struct intc_group *groups,
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66 | 80f515e6 | balrog | int nr_groups);
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67 | 80f515e6 | balrog | |
68 | 80f515e6 | balrog | int sh_intc_init(struct intc_desc *desc, |
69 | 80f515e6 | balrog | int nr_sources,
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70 | 80f515e6 | balrog | struct intc_mask_reg *mask_regs,
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71 | 80f515e6 | balrog | int nr_mask_regs,
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72 | 80f515e6 | balrog | struct intc_prio_reg *prio_regs,
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73 | 80f515e6 | balrog | int nr_prio_regs);
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74 | 80f515e6 | balrog | |
75 | 80f515e6 | balrog | #endif /* __SH_INTC_H__ */ |