root / hw / sh_timer.c @ 1ffc346f
History | View | Annotate | Download (8.5 kB)
1 | cd1a3f68 | ths | /*
|
---|---|---|---|
2 | cd1a3f68 | ths | * SuperH Timer modules.
|
3 | cd1a3f68 | ths | *
|
4 | cd1a3f68 | ths | * Copyright (c) 2007 Magnus Damm
|
5 | cd1a3f68 | ths | * Based on arm_timer.c by Paul Brook
|
6 | cd1a3f68 | ths | * Copyright (c) 2005-2006 CodeSourcery.
|
7 | cd1a3f68 | ths | *
|
8 | cd1a3f68 | ths | * This code is licenced under the GPL.
|
9 | cd1a3f68 | ths | */
|
10 | cd1a3f68 | ths | |
11 | 87ecb68b | pbrook | #include "hw.h" |
12 | 87ecb68b | pbrook | #include "sh.h" |
13 | 87ecb68b | pbrook | #include "qemu-timer.h" |
14 | cd1a3f68 | ths | |
15 | cd1a3f68 | ths | //#define DEBUG_TIMER
|
16 | cd1a3f68 | ths | |
17 | cd1a3f68 | ths | #define TIMER_TCR_TPSC (7 << 0) |
18 | cd1a3f68 | ths | #define TIMER_TCR_CKEG (3 << 3) |
19 | cd1a3f68 | ths | #define TIMER_TCR_UNIE (1 << 5) |
20 | cd1a3f68 | ths | #define TIMER_TCR_ICPE (3 << 6) |
21 | cd1a3f68 | ths | #define TIMER_TCR_UNF (1 << 8) |
22 | cd1a3f68 | ths | #define TIMER_TCR_ICPF (1 << 9) |
23 | cd1a3f68 | ths | #define TIMER_TCR_RESERVED (0x3f << 10) |
24 | cd1a3f68 | ths | |
25 | cd1a3f68 | ths | #define TIMER_FEAT_CAPT (1 << 0) |
26 | cd1a3f68 | ths | #define TIMER_FEAT_EXTCLK (1 << 1) |
27 | cd1a3f68 | ths | |
28 | cd1a3f68 | ths | typedef struct { |
29 | cd1a3f68 | ths | ptimer_state *timer; |
30 | cd1a3f68 | ths | uint32_t tcnt; |
31 | cd1a3f68 | ths | uint32_t tcor; |
32 | cd1a3f68 | ths | uint32_t tcr; |
33 | cd1a3f68 | ths | uint32_t tcpr; |
34 | cd1a3f68 | ths | int freq;
|
35 | cd1a3f68 | ths | int int_level;
|
36 | 703243a0 | balrog | int old_level;
|
37 | cd1a3f68 | ths | int feat;
|
38 | cd1a3f68 | ths | int enabled;
|
39 | 703243a0 | balrog | struct intc_source *irq;
|
40 | cd1a3f68 | ths | } sh_timer_state; |
41 | cd1a3f68 | ths | |
42 | cd1a3f68 | ths | /* Check all active timers, and schedule the next timer interrupt. */
|
43 | cd1a3f68 | ths | |
44 | cd1a3f68 | ths | static void sh_timer_update(sh_timer_state *s) |
45 | cd1a3f68 | ths | { |
46 | 703243a0 | balrog | int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
|
47 | 703243a0 | balrog | |
48 | 703243a0 | balrog | if (new_level != s->old_level)
|
49 | 703243a0 | balrog | sh_intc_toggle_source(s->irq, 0, new_level ? 1 : -1); |
50 | 703243a0 | balrog | |
51 | 703243a0 | balrog | s->old_level = s->int_level; |
52 | 703243a0 | balrog | s->int_level = new_level; |
53 | cd1a3f68 | ths | } |
54 | cd1a3f68 | ths | |
55 | 9596ebb7 | pbrook | static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset) |
56 | cd1a3f68 | ths | { |
57 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
58 | cd1a3f68 | ths | |
59 | cd1a3f68 | ths | switch (offset >> 2) { |
60 | cd1a3f68 | ths | case 0: |
61 | cd1a3f68 | ths | return s->tcor;
|
62 | cd1a3f68 | ths | case 1: |
63 | cd1a3f68 | ths | return ptimer_get_count(s->timer);
|
64 | cd1a3f68 | ths | case 2: |
65 | cd1a3f68 | ths | return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); |
66 | cd1a3f68 | ths | case 3: |
67 | cd1a3f68 | ths | if (s->feat & TIMER_FEAT_CAPT)
|
68 | cd1a3f68 | ths | return s->tcpr;
|
69 | cd1a3f68 | ths | default:
|
70 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
|
71 | cd1a3f68 | ths | (int)offset);
|
72 | cd1a3f68 | ths | return 0; |
73 | cd1a3f68 | ths | } |
74 | cd1a3f68 | ths | } |
75 | cd1a3f68 | ths | |
76 | cd1a3f68 | ths | static void sh_timer_write(void *opaque, target_phys_addr_t offset, |
77 | cd1a3f68 | ths | uint32_t value) |
78 | cd1a3f68 | ths | { |
79 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
80 | cd1a3f68 | ths | int freq;
|
81 | cd1a3f68 | ths | |
82 | cd1a3f68 | ths | switch (offset >> 2) { |
83 | cd1a3f68 | ths | case 0: |
84 | cd1a3f68 | ths | s->tcor = value; |
85 | cd1a3f68 | ths | ptimer_set_limit(s->timer, s->tcor, 0);
|
86 | cd1a3f68 | ths | break;
|
87 | cd1a3f68 | ths | case 1: |
88 | cd1a3f68 | ths | s->tcnt = value; |
89 | cd1a3f68 | ths | ptimer_set_count(s->timer, s->tcnt); |
90 | cd1a3f68 | ths | break;
|
91 | cd1a3f68 | ths | case 2: |
92 | cd1a3f68 | ths | if (s->enabled) {
|
93 | cd1a3f68 | ths | /* Pause the timer if it is running. This may cause some
|
94 | cd1a3f68 | ths | inaccuracy dure to rounding, but avoids a whole lot of other
|
95 | cd1a3f68 | ths | messyness. */
|
96 | cd1a3f68 | ths | ptimer_stop(s->timer); |
97 | cd1a3f68 | ths | } |
98 | cd1a3f68 | ths | freq = s->freq; |
99 | cd1a3f68 | ths | /* ??? Need to recalculate expiry time after changing divisor. */
|
100 | cd1a3f68 | ths | switch (value & TIMER_TCR_TPSC) {
|
101 | cd1a3f68 | ths | case 0: freq >>= 2; break; |
102 | cd1a3f68 | ths | case 1: freq >>= 4; break; |
103 | cd1a3f68 | ths | case 2: freq >>= 6; break; |
104 | cd1a3f68 | ths | case 3: freq >>= 8; break; |
105 | cd1a3f68 | ths | case 4: freq >>= 10; break; |
106 | cd1a3f68 | ths | case 6: |
107 | cd1a3f68 | ths | case 7: if (s->feat & TIMER_FEAT_EXTCLK) break; |
108 | cd1a3f68 | ths | default: cpu_abort (cpu_single_env,
|
109 | cd1a3f68 | ths | "sh_timer_write: Reserved TPSC value\n"); break; |
110 | cd1a3f68 | ths | } |
111 | cd1a3f68 | ths | switch ((value & TIMER_TCR_CKEG) >> 3) { |
112 | cd1a3f68 | ths | case 0: break; |
113 | cd1a3f68 | ths | case 1: |
114 | cd1a3f68 | ths | case 2: |
115 | cd1a3f68 | ths | case 3: if (s->feat & TIMER_FEAT_EXTCLK) break; |
116 | cd1a3f68 | ths | default: cpu_abort (cpu_single_env,
|
117 | cd1a3f68 | ths | "sh_timer_write: Reserved CKEG value\n"); break; |
118 | cd1a3f68 | ths | } |
119 | cd1a3f68 | ths | switch ((value & TIMER_TCR_ICPE) >> 6) { |
120 | cd1a3f68 | ths | case 0: break; |
121 | cd1a3f68 | ths | case 2: |
122 | cd1a3f68 | ths | case 3: if (s->feat & TIMER_FEAT_CAPT) break; |
123 | cd1a3f68 | ths | default: cpu_abort (cpu_single_env,
|
124 | cd1a3f68 | ths | "sh_timer_write: Reserved ICPE value\n"); break; |
125 | cd1a3f68 | ths | } |
126 | cd1a3f68 | ths | if ((value & TIMER_TCR_UNF) == 0) |
127 | cd1a3f68 | ths | s->int_level = 0;
|
128 | cd1a3f68 | ths | |
129 | cd1a3f68 | ths | value &= ~TIMER_TCR_UNF; |
130 | cd1a3f68 | ths | |
131 | cd1a3f68 | ths | if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
|
132 | cd1a3f68 | ths | cpu_abort (cpu_single_env, |
133 | cd1a3f68 | ths | "sh_timer_write: Reserved ICPF value\n");
|
134 | cd1a3f68 | ths | |
135 | cd1a3f68 | ths | value &= ~TIMER_TCR_ICPF; /* capture not supported */
|
136 | cd1a3f68 | ths | |
137 | cd1a3f68 | ths | if (value & TIMER_TCR_RESERVED)
|
138 | cd1a3f68 | ths | cpu_abort (cpu_single_env, |
139 | cd1a3f68 | ths | "sh_timer_write: Reserved TCR bits set\n");
|
140 | cd1a3f68 | ths | s->tcr = value; |
141 | cd1a3f68 | ths | ptimer_set_limit(s->timer, s->tcor, 0);
|
142 | cd1a3f68 | ths | ptimer_set_freq(s->timer, freq); |
143 | cd1a3f68 | ths | if (s->enabled) {
|
144 | cd1a3f68 | ths | /* Restart the timer if still enabled. */
|
145 | cd1a3f68 | ths | ptimer_run(s->timer, 0);
|
146 | cd1a3f68 | ths | } |
147 | cd1a3f68 | ths | break;
|
148 | cd1a3f68 | ths | case 3: |
149 | cd1a3f68 | ths | if (s->feat & TIMER_FEAT_CAPT) {
|
150 | cd1a3f68 | ths | s->tcpr = value; |
151 | cd1a3f68 | ths | break;
|
152 | cd1a3f68 | ths | } |
153 | cd1a3f68 | ths | default:
|
154 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
|
155 | cd1a3f68 | ths | (int)offset);
|
156 | cd1a3f68 | ths | } |
157 | cd1a3f68 | ths | sh_timer_update(s); |
158 | cd1a3f68 | ths | } |
159 | cd1a3f68 | ths | |
160 | cd1a3f68 | ths | static void sh_timer_start_stop(void *opaque, int enable) |
161 | cd1a3f68 | ths | { |
162 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
163 | cd1a3f68 | ths | |
164 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
|
165 | cd1a3f68 | ths | printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
|
166 | cd1a3f68 | ths | #endif
|
167 | cd1a3f68 | ths | |
168 | cd1a3f68 | ths | if (s->enabled && !enable) {
|
169 | cd1a3f68 | ths | ptimer_stop(s->timer); |
170 | cd1a3f68 | ths | } |
171 | cd1a3f68 | ths | if (!s->enabled && enable) {
|
172 | cd1a3f68 | ths | ptimer_run(s->timer, 0);
|
173 | cd1a3f68 | ths | } |
174 | cd1a3f68 | ths | s->enabled = !!enable; |
175 | cd1a3f68 | ths | |
176 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
|
177 | cd1a3f68 | ths | printf("sh_timer_start_stop done %d\n", s->enabled);
|
178 | cd1a3f68 | ths | #endif
|
179 | cd1a3f68 | ths | } |
180 | cd1a3f68 | ths | |
181 | cd1a3f68 | ths | static void sh_timer_tick(void *opaque) |
182 | cd1a3f68 | ths | { |
183 | cd1a3f68 | ths | sh_timer_state *s = (sh_timer_state *)opaque; |
184 | cd1a3f68 | ths | s->int_level = s->enabled; |
185 | cd1a3f68 | ths | sh_timer_update(s); |
186 | cd1a3f68 | ths | } |
187 | cd1a3f68 | ths | |
188 | 703243a0 | balrog | static void *sh_timer_init(uint32_t freq, int feat, struct intc_source *irq) |
189 | cd1a3f68 | ths | { |
190 | cd1a3f68 | ths | sh_timer_state *s; |
191 | cd1a3f68 | ths | QEMUBH *bh; |
192 | cd1a3f68 | ths | |
193 | cd1a3f68 | ths | s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state));
|
194 | cd1a3f68 | ths | s->freq = freq; |
195 | cd1a3f68 | ths | s->feat = feat; |
196 | cd1a3f68 | ths | s->tcor = 0xffffffff;
|
197 | cd1a3f68 | ths | s->tcnt = 0xffffffff;
|
198 | cd1a3f68 | ths | s->tcpr = 0xdeadbeef;
|
199 | cd1a3f68 | ths | s->tcor = 0;
|
200 | cd1a3f68 | ths | s->enabled = 0;
|
201 | 703243a0 | balrog | s->irq = irq; |
202 | cd1a3f68 | ths | |
203 | cd1a3f68 | ths | bh = qemu_bh_new(sh_timer_tick, s); |
204 | cd1a3f68 | ths | s->timer = ptimer_init(bh); |
205 | cd1a3f68 | ths | /* ??? Save/restore. */
|
206 | cd1a3f68 | ths | return s;
|
207 | cd1a3f68 | ths | } |
208 | cd1a3f68 | ths | |
209 | cd1a3f68 | ths | typedef struct { |
210 | cd1a3f68 | ths | void *timer[3]; |
211 | cd1a3f68 | ths | int level[3]; |
212 | cd1a3f68 | ths | uint32_t tocr; |
213 | cd1a3f68 | ths | uint32_t tstr; |
214 | cd1a3f68 | ths | target_phys_addr_t base; |
215 | cd1a3f68 | ths | int feat;
|
216 | cd1a3f68 | ths | } tmu012_state; |
217 | cd1a3f68 | ths | |
218 | cd1a3f68 | ths | static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset) |
219 | cd1a3f68 | ths | { |
220 | cd1a3f68 | ths | tmu012_state *s = (tmu012_state *)opaque; |
221 | cd1a3f68 | ths | |
222 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
|
223 | cd1a3f68 | ths | printf("tmu012_read 0x%lx\n", (unsigned long) offset); |
224 | cd1a3f68 | ths | #endif
|
225 | cd1a3f68 | ths | offset -= s->base; |
226 | cd1a3f68 | ths | |
227 | cd1a3f68 | ths | if (offset >= 0x20) { |
228 | cd1a3f68 | ths | if (!(s->feat & TMU012_FEAT_3CHAN))
|
229 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
|
230 | cd1a3f68 | ths | (int)offset);
|
231 | cd1a3f68 | ths | return sh_timer_read(s->timer[2], offset - 0x20); |
232 | cd1a3f68 | ths | } |
233 | cd1a3f68 | ths | |
234 | cd1a3f68 | ths | if (offset >= 0x14) |
235 | cd1a3f68 | ths | return sh_timer_read(s->timer[1], offset - 0x14); |
236 | cd1a3f68 | ths | |
237 | cd1a3f68 | ths | if (offset >= 0x08) |
238 | cd1a3f68 | ths | return sh_timer_read(s->timer[0], offset - 0x08); |
239 | cd1a3f68 | ths | |
240 | cd1a3f68 | ths | if (offset == 4) |
241 | cd1a3f68 | ths | return s->tstr;
|
242 | cd1a3f68 | ths | |
243 | cd1a3f68 | ths | if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) |
244 | cd1a3f68 | ths | return s->tocr;
|
245 | cd1a3f68 | ths | |
246 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
|
247 | cd1a3f68 | ths | (int)offset);
|
248 | cd1a3f68 | ths | return 0; |
249 | cd1a3f68 | ths | } |
250 | cd1a3f68 | ths | |
251 | cd1a3f68 | ths | static void tmu012_write(void *opaque, target_phys_addr_t offset, |
252 | cd1a3f68 | ths | uint32_t value) |
253 | cd1a3f68 | ths | { |
254 | cd1a3f68 | ths | tmu012_state *s = (tmu012_state *)opaque; |
255 | cd1a3f68 | ths | |
256 | cd1a3f68 | ths | #ifdef DEBUG_TIMER
|
257 | cd1a3f68 | ths | printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); |
258 | cd1a3f68 | ths | #endif
|
259 | cd1a3f68 | ths | offset -= s->base; |
260 | cd1a3f68 | ths | |
261 | cd1a3f68 | ths | if (offset >= 0x20) { |
262 | cd1a3f68 | ths | if (!(s->feat & TMU012_FEAT_3CHAN))
|
263 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
|
264 | cd1a3f68 | ths | (int)offset);
|
265 | cd1a3f68 | ths | sh_timer_write(s->timer[2], offset - 0x20, value); |
266 | cd1a3f68 | ths | return;
|
267 | cd1a3f68 | ths | } |
268 | cd1a3f68 | ths | |
269 | cd1a3f68 | ths | if (offset >= 0x14) { |
270 | cd1a3f68 | ths | sh_timer_write(s->timer[1], offset - 0x14, value); |
271 | cd1a3f68 | ths | return;
|
272 | cd1a3f68 | ths | } |
273 | cd1a3f68 | ths | |
274 | cd1a3f68 | ths | if (offset >= 0x08) { |
275 | cd1a3f68 | ths | sh_timer_write(s->timer[0], offset - 0x08, value); |
276 | cd1a3f68 | ths | return;
|
277 | cd1a3f68 | ths | } |
278 | cd1a3f68 | ths | |
279 | cd1a3f68 | ths | if (offset == 4) { |
280 | cd1a3f68 | ths | sh_timer_start_stop(s->timer[0], value & (1 << 0)); |
281 | cd1a3f68 | ths | sh_timer_start_stop(s->timer[1], value & (1 << 1)); |
282 | cd1a3f68 | ths | if (s->feat & TMU012_FEAT_3CHAN)
|
283 | cd1a3f68 | ths | sh_timer_start_stop(s->timer[2], value & (1 << 2)); |
284 | cd1a3f68 | ths | else
|
285 | cd1a3f68 | ths | if (value & (1 << 2)) |
286 | cd1a3f68 | ths | cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
|
287 | cd1a3f68 | ths | |
288 | cd1a3f68 | ths | s->tstr = value; |
289 | cd1a3f68 | ths | return;
|
290 | cd1a3f68 | ths | } |
291 | cd1a3f68 | ths | |
292 | cd1a3f68 | ths | if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { |
293 | cd1a3f68 | ths | s->tocr = value & (1 << 0); |
294 | cd1a3f68 | ths | } |
295 | cd1a3f68 | ths | } |
296 | cd1a3f68 | ths | |
297 | cd1a3f68 | ths | static CPUReadMemoryFunc *tmu012_readfn[] = {
|
298 | cd1a3f68 | ths | tmu012_read, |
299 | cd1a3f68 | ths | tmu012_read, |
300 | cd1a3f68 | ths | tmu012_read |
301 | cd1a3f68 | ths | }; |
302 | cd1a3f68 | ths | |
303 | cd1a3f68 | ths | static CPUWriteMemoryFunc *tmu012_writefn[] = {
|
304 | cd1a3f68 | ths | tmu012_write, |
305 | cd1a3f68 | ths | tmu012_write, |
306 | cd1a3f68 | ths | tmu012_write |
307 | cd1a3f68 | ths | }; |
308 | cd1a3f68 | ths | |
309 | 703243a0 | balrog | void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, |
310 | 703243a0 | balrog | struct intc_source *ch0_irq, struct intc_source *ch1_irq, |
311 | 703243a0 | balrog | struct intc_source *ch2_irq0, struct intc_source *ch2_irq1) |
312 | cd1a3f68 | ths | { |
313 | cd1a3f68 | ths | int iomemtype;
|
314 | cd1a3f68 | ths | tmu012_state *s; |
315 | cd1a3f68 | ths | int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; |
316 | cd1a3f68 | ths | |
317 | cd1a3f68 | ths | s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
|
318 | cd1a3f68 | ths | s->base = base; |
319 | cd1a3f68 | ths | s->feat = feat; |
320 | 703243a0 | balrog | s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
|
321 | 703243a0 | balrog | s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
|
322 | cd1a3f68 | ths | if (feat & TMU012_FEAT_3CHAN)
|
323 | 703243a0 | balrog | s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
|
324 | 703243a0 | balrog | ch2_irq0); /* ch2_irq1 not supported */
|
325 | cd1a3f68 | ths | iomemtype = cpu_register_io_memory(0, tmu012_readfn,
|
326 | cd1a3f68 | ths | tmu012_writefn, s); |
327 | cd1a3f68 | ths | cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
328 | cd1a3f68 | ths | /* ??? Save/restore. */
|
329 | cd1a3f68 | ths | } |