root / target-arm / machine.c @ 1ffc346f
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1 | 8dd3dca3 | aurel32 | #include "hw/hw.h" |
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2 | 8dd3dca3 | aurel32 | #include "hw/boards.h" |
3 | 8dd3dca3 | aurel32 | |
4 | 8dd3dca3 | aurel32 | void register_machines(void) |
5 | 8dd3dca3 | aurel32 | { |
6 | 8dd3dca3 | aurel32 | qemu_register_machine(&integratorcp_machine); |
7 | 8dd3dca3 | aurel32 | qemu_register_machine(&versatilepb_machine); |
8 | 8dd3dca3 | aurel32 | qemu_register_machine(&versatileab_machine); |
9 | 8dd3dca3 | aurel32 | qemu_register_machine(&realview_machine); |
10 | 8dd3dca3 | aurel32 | qemu_register_machine(&akitapda_machine); |
11 | 8dd3dca3 | aurel32 | qemu_register_machine(&spitzpda_machine); |
12 | 8dd3dca3 | aurel32 | qemu_register_machine(&borzoipda_machine); |
13 | 8dd3dca3 | aurel32 | qemu_register_machine(&terrierpda_machine); |
14 | 8dd3dca3 | aurel32 | qemu_register_machine(&palmte_machine); |
15 | 8dd3dca3 | aurel32 | qemu_register_machine(&n800_machine); |
16 | 8dd3dca3 | aurel32 | qemu_register_machine(&lm3s811evb_machine); |
17 | 8dd3dca3 | aurel32 | qemu_register_machine(&lm3s6965evb_machine); |
18 | 8dd3dca3 | aurel32 | qemu_register_machine(&connex_machine); |
19 | 8dd3dca3 | aurel32 | qemu_register_machine(&verdex_machine); |
20 | 8dd3dca3 | aurel32 | qemu_register_machine(&mainstone2_machine); |
21 | 8dd3dca3 | aurel32 | qemu_register_machine(&musicpal_machine); |
22 | 8dd3dca3 | aurel32 | } |
23 | 8dd3dca3 | aurel32 | |
24 | 8dd3dca3 | aurel32 | void cpu_save(QEMUFile *f, void *opaque) |
25 | 8dd3dca3 | aurel32 | { |
26 | 8dd3dca3 | aurel32 | int i;
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27 | 8dd3dca3 | aurel32 | CPUARMState *env = (CPUARMState *)opaque; |
28 | 8dd3dca3 | aurel32 | |
29 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
30 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->regs[i]); |
31 | 8dd3dca3 | aurel32 | } |
32 | 8dd3dca3 | aurel32 | qemu_put_be32(f, cpsr_read(env)); |
33 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->spsr); |
34 | 8dd3dca3 | aurel32 | for (i = 0; i < 6; i++) { |
35 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_spsr[i]); |
36 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_r13[i]); |
37 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_r14[i]); |
38 | 8dd3dca3 | aurel32 | } |
39 | 8dd3dca3 | aurel32 | for (i = 0; i < 5; i++) { |
40 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->usr_regs[i]); |
41 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->fiq_regs[i]); |
42 | 8dd3dca3 | aurel32 | } |
43 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c0_cpuid); |
44 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c0_cachetype); |
45 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_sys); |
46 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_coproc); |
47 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_xscaleauxcr); |
48 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_base0); |
49 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_base1); |
50 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_mask); |
51 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_data); |
52 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_insn); |
53 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c3); |
54 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c5_insn); |
55 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c5_data); |
56 | 8dd3dca3 | aurel32 | for (i = 0; i < 8; i++) { |
57 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_region[i]); |
58 | 8dd3dca3 | aurel32 | } |
59 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_insn); |
60 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_data); |
61 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c9_insn); |
62 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c9_data); |
63 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_fcse); |
64 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_context); |
65 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls1); |
66 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls2); |
67 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls3); |
68 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c15_cpar); |
69 | 8dd3dca3 | aurel32 | |
70 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->features); |
71 | 8dd3dca3 | aurel32 | |
72 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP)) {
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73 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
74 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
75 | 8dd3dca3 | aurel32 | u.d = env->vfp.regs[i]; |
76 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.upper); |
77 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.lower); |
78 | 8dd3dca3 | aurel32 | } |
79 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
80 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.xregs[i]); |
81 | 8dd3dca3 | aurel32 | } |
82 | 8dd3dca3 | aurel32 | |
83 | 8dd3dca3 | aurel32 | /* TODO: Should use proper FPSCR access functions. */
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84 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.vec_len); |
85 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.vec_stride); |
86 | 8dd3dca3 | aurel32 | |
87 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP3)) {
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88 | 8dd3dca3 | aurel32 | for (i = 16; i < 32; i++) { |
89 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
90 | 8dd3dca3 | aurel32 | u.d = env->vfp.regs[i]; |
91 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.upper); |
92 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.lower); |
93 | 8dd3dca3 | aurel32 | } |
94 | 8dd3dca3 | aurel32 | } |
95 | 8dd3dca3 | aurel32 | } |
96 | 8dd3dca3 | aurel32 | |
97 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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98 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
99 | 8dd3dca3 | aurel32 | qemu_put_be64(f, env->iwmmxt.regs[i]); |
100 | 8dd3dca3 | aurel32 | } |
101 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
102 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->iwmmxt.cregs[i]); |
103 | 8dd3dca3 | aurel32 | } |
104 | 8dd3dca3 | aurel32 | } |
105 | 8dd3dca3 | aurel32 | |
106 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_M)) {
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107 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.other_sp); |
108 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.vecbase); |
109 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.basepri); |
110 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.control); |
111 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.current_sp); |
112 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.exception); |
113 | 8dd3dca3 | aurel32 | } |
114 | 8dd3dca3 | aurel32 | } |
115 | 8dd3dca3 | aurel32 | |
116 | 8dd3dca3 | aurel32 | int cpu_load(QEMUFile *f, void *opaque, int version_id) |
117 | 8dd3dca3 | aurel32 | { |
118 | 8dd3dca3 | aurel32 | CPUARMState *env = (CPUARMState *)opaque; |
119 | 8dd3dca3 | aurel32 | int i;
|
120 | 8dd3dca3 | aurel32 | |
121 | 8dd3dca3 | aurel32 | if (version_id != ARM_CPU_SAVE_VERSION)
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122 | 8dd3dca3 | aurel32 | return -EINVAL;
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123 | 8dd3dca3 | aurel32 | |
124 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
125 | 8dd3dca3 | aurel32 | env->regs[i] = qemu_get_be32(f); |
126 | 8dd3dca3 | aurel32 | } |
127 | 8dd3dca3 | aurel32 | cpsr_write(env, qemu_get_be32(f), 0xffffffff);
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128 | 8dd3dca3 | aurel32 | env->spsr = qemu_get_be32(f); |
129 | 8dd3dca3 | aurel32 | for (i = 0; i < 6; i++) { |
130 | 8dd3dca3 | aurel32 | env->banked_spsr[i] = qemu_get_be32(f); |
131 | 8dd3dca3 | aurel32 | env->banked_r13[i] = qemu_get_be32(f); |
132 | 8dd3dca3 | aurel32 | env->banked_r14[i] = qemu_get_be32(f); |
133 | 8dd3dca3 | aurel32 | } |
134 | 8dd3dca3 | aurel32 | for (i = 0; i < 5; i++) { |
135 | 8dd3dca3 | aurel32 | env->usr_regs[i] = qemu_get_be32(f); |
136 | 8dd3dca3 | aurel32 | env->fiq_regs[i] = qemu_get_be32(f); |
137 | 8dd3dca3 | aurel32 | } |
138 | 8dd3dca3 | aurel32 | env->cp15.c0_cpuid = qemu_get_be32(f); |
139 | 8dd3dca3 | aurel32 | env->cp15.c0_cachetype = qemu_get_be32(f); |
140 | 8dd3dca3 | aurel32 | env->cp15.c1_sys = qemu_get_be32(f); |
141 | 8dd3dca3 | aurel32 | env->cp15.c1_coproc = qemu_get_be32(f); |
142 | 8dd3dca3 | aurel32 | env->cp15.c1_xscaleauxcr = qemu_get_be32(f); |
143 | 8dd3dca3 | aurel32 | env->cp15.c2_base0 = qemu_get_be32(f); |
144 | 8dd3dca3 | aurel32 | env->cp15.c2_base1 = qemu_get_be32(f); |
145 | 8dd3dca3 | aurel32 | env->cp15.c2_mask = qemu_get_be32(f); |
146 | 8dd3dca3 | aurel32 | env->cp15.c2_data = qemu_get_be32(f); |
147 | 8dd3dca3 | aurel32 | env->cp15.c2_insn = qemu_get_be32(f); |
148 | 8dd3dca3 | aurel32 | env->cp15.c3 = qemu_get_be32(f); |
149 | 8dd3dca3 | aurel32 | env->cp15.c5_insn = qemu_get_be32(f); |
150 | 8dd3dca3 | aurel32 | env->cp15.c5_data = qemu_get_be32(f); |
151 | 8dd3dca3 | aurel32 | for (i = 0; i < 8; i++) { |
152 | 8dd3dca3 | aurel32 | env->cp15.c6_region[i] = qemu_get_be32(f); |
153 | 8dd3dca3 | aurel32 | } |
154 | 8dd3dca3 | aurel32 | env->cp15.c6_insn = qemu_get_be32(f); |
155 | 8dd3dca3 | aurel32 | env->cp15.c6_data = qemu_get_be32(f); |
156 | 8dd3dca3 | aurel32 | env->cp15.c9_insn = qemu_get_be32(f); |
157 | 8dd3dca3 | aurel32 | env->cp15.c9_data = qemu_get_be32(f); |
158 | 8dd3dca3 | aurel32 | env->cp15.c13_fcse = qemu_get_be32(f); |
159 | 8dd3dca3 | aurel32 | env->cp15.c13_context = qemu_get_be32(f); |
160 | 8dd3dca3 | aurel32 | env->cp15.c13_tls1 = qemu_get_be32(f); |
161 | 8dd3dca3 | aurel32 | env->cp15.c13_tls2 = qemu_get_be32(f); |
162 | 8dd3dca3 | aurel32 | env->cp15.c13_tls3 = qemu_get_be32(f); |
163 | 8dd3dca3 | aurel32 | env->cp15.c15_cpar = qemu_get_be32(f); |
164 | 8dd3dca3 | aurel32 | |
165 | 8dd3dca3 | aurel32 | env->features = qemu_get_be32(f); |
166 | 8dd3dca3 | aurel32 | |
167 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP)) {
|
168 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
169 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
170 | 8dd3dca3 | aurel32 | u.l.upper = qemu_get_be32(f); |
171 | 8dd3dca3 | aurel32 | u.l.lower = qemu_get_be32(f); |
172 | 8dd3dca3 | aurel32 | env->vfp.regs[i] = u.d; |
173 | 8dd3dca3 | aurel32 | } |
174 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
175 | 8dd3dca3 | aurel32 | env->vfp.xregs[i] = qemu_get_be32(f); |
176 | 8dd3dca3 | aurel32 | } |
177 | 8dd3dca3 | aurel32 | |
178 | 8dd3dca3 | aurel32 | /* TODO: Should use proper FPSCR access functions. */
|
179 | 8dd3dca3 | aurel32 | env->vfp.vec_len = qemu_get_be32(f); |
180 | 8dd3dca3 | aurel32 | env->vfp.vec_stride = qemu_get_be32(f); |
181 | 8dd3dca3 | aurel32 | |
182 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP3)) {
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183 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
184 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
185 | 8dd3dca3 | aurel32 | u.l.upper = qemu_get_be32(f); |
186 | 8dd3dca3 | aurel32 | u.l.lower = qemu_get_be32(f); |
187 | 8dd3dca3 | aurel32 | env->vfp.regs[i] = u.d; |
188 | 8dd3dca3 | aurel32 | } |
189 | 8dd3dca3 | aurel32 | } |
190 | 8dd3dca3 | aurel32 | } |
191 | 8dd3dca3 | aurel32 | |
192 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
193 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
194 | 8dd3dca3 | aurel32 | env->iwmmxt.regs[i] = qemu_get_be64(f); |
195 | 8dd3dca3 | aurel32 | } |
196 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
197 | 8dd3dca3 | aurel32 | env->iwmmxt.cregs[i] = qemu_get_be32(f); |
198 | 8dd3dca3 | aurel32 | } |
199 | 8dd3dca3 | aurel32 | } |
200 | 8dd3dca3 | aurel32 | |
201 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_M)) {
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202 | 8dd3dca3 | aurel32 | env->v7m.other_sp = qemu_get_be32(f); |
203 | 8dd3dca3 | aurel32 | env->v7m.vecbase = qemu_get_be32(f); |
204 | 8dd3dca3 | aurel32 | env->v7m.basepri = qemu_get_be32(f); |
205 | 8dd3dca3 | aurel32 | env->v7m.control = qemu_get_be32(f); |
206 | 8dd3dca3 | aurel32 | env->v7m.current_sp = qemu_get_be32(f); |
207 | 8dd3dca3 | aurel32 | env->v7m.exception = qemu_get_be32(f); |
208 | 8dd3dca3 | aurel32 | } |
209 | 8dd3dca3 | aurel32 | |
210 | 8dd3dca3 | aurel32 | return 0; |
211 | 8dd3dca3 | aurel32 | } |
212 | 8dd3dca3 | aurel32 |