root / target-mips / exec.h @ 1ffc346f
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1 | 6af0bf9c | bellard | #if !defined(__QEMU_MIPS_EXEC_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_EXEC_H__
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3 | 6af0bf9c | bellard | |
4 | 01dbbdf1 | bellard | //#define DEBUG_OP
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5 | 6af0bf9c | bellard | |
6 | c570fd16 | ths | #include "config.h" |
7 | 6af0bf9c | bellard | #include "mips-defs.h" |
8 | 6af0bf9c | bellard | #include "dyngen-exec.h" |
9 | 01179c38 | ths | #include "cpu-defs.h" |
10 | 6af0bf9c | bellard | |
11 | 6af0bf9c | bellard | register struct CPUMIPSState *env asm(AREG0); |
12 | 6af0bf9c | bellard | |
13 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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14 | c570fd16 | ths | #define T0 (env->t0)
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15 | c570fd16 | ths | #define T1 (env->t1)
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16 | c570fd16 | ths | #else
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17 | 958fb4a9 | ths | register target_ulong T0 asm(AREG1); |
18 | 958fb4a9 | ths | register target_ulong T1 asm(AREG2); |
19 | c570fd16 | ths | #endif
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20 | 6af0bf9c | bellard | |
21 | 6af0bf9c | bellard | #if defined (USE_HOST_FLOAT_REGS)
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22 | 6ea83fed | bellard | #error "implement me." |
23 | 6af0bf9c | bellard | #else
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24 | ead9360e | ths | #define FDT0 (env->fpu->ft0.fd)
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25 | ead9360e | ths | #define FDT1 (env->fpu->ft1.fd)
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26 | ead9360e | ths | #define FDT2 (env->fpu->ft2.fd)
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27 | ead9360e | ths | #define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
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28 | ead9360e | ths | #define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
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29 | ead9360e | ths | #define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
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30 | ead9360e | ths | #define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
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31 | ead9360e | ths | #define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
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32 | ead9360e | ths | #define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
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33 | ead9360e | ths | #define DT0 (env->fpu->ft0.d)
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34 | ead9360e | ths | #define DT1 (env->fpu->ft1.d)
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35 | ead9360e | ths | #define DT2 (env->fpu->ft2.d)
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36 | ead9360e | ths | #define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
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37 | ead9360e | ths | #define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
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38 | ead9360e | ths | #define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
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39 | ead9360e | ths | #define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
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40 | ead9360e | ths | #define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
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41 | ead9360e | ths | #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
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42 | 6af0bf9c | bellard | #endif
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43 | 6af0bf9c | bellard | |
44 | 6af0bf9c | bellard | #include "cpu.h" |
45 | 6af0bf9c | bellard | #include "exec-all.h" |
46 | 6af0bf9c | bellard | |
47 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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48 | a9049a07 | bellard | #include "softmmu_exec.h" |
49 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
50 | 6af0bf9c | bellard | |
51 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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52 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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53 | c570fd16 | ths | void do_dsll (void); |
54 | c570fd16 | ths | void do_dsll32 (void); |
55 | c570fd16 | ths | void do_dsra (void); |
56 | c570fd16 | ths | void do_dsra32 (void); |
57 | c570fd16 | ths | void do_dsrl (void); |
58 | c570fd16 | ths | void do_dsrl32 (void); |
59 | c570fd16 | ths | void do_drotr (void); |
60 | c570fd16 | ths | void do_drotr32 (void); |
61 | c570fd16 | ths | void do_dsllv (void); |
62 | c570fd16 | ths | void do_dsrav (void); |
63 | c570fd16 | ths | void do_dsrlv (void); |
64 | c570fd16 | ths | void do_drotrv (void); |
65 | 05f778c8 | ths | void do_dclo (void); |
66 | 05f778c8 | ths | void do_dclz (void); |
67 | c570fd16 | ths | #endif
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68 | c570fd16 | ths | #endif
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69 | c570fd16 | ths | |
70 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
71 | 80c27194 | ths | void do_div (void); |
72 | 80c27194 | ths | #endif
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73 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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74 | 6af0bf9c | bellard | void do_mult (void); |
75 | 6af0bf9c | bellard | void do_multu (void); |
76 | 6af0bf9c | bellard | void do_madd (void); |
77 | 6af0bf9c | bellard | void do_maddu (void); |
78 | 6af0bf9c | bellard | void do_msub (void); |
79 | 6af0bf9c | bellard | void do_msubu (void); |
80 | e9c71dd1 | ths | void do_muls (void); |
81 | e9c71dd1 | ths | void do_mulsu (void); |
82 | e9c71dd1 | ths | void do_macc (void); |
83 | e9c71dd1 | ths | void do_macchi (void); |
84 | e9c71dd1 | ths | void do_maccu (void); |
85 | e9c71dd1 | ths | void do_macchiu (void); |
86 | e9c71dd1 | ths | void do_msac (void); |
87 | e9c71dd1 | ths | void do_msachi (void); |
88 | e9c71dd1 | ths | void do_msacu (void); |
89 | e9c71dd1 | ths | void do_msachiu (void); |
90 | e9c71dd1 | ths | void do_mulhi (void); |
91 | e9c71dd1 | ths | void do_mulhiu (void); |
92 | e9c71dd1 | ths | void do_mulshi (void); |
93 | e9c71dd1 | ths | void do_mulshiu (void); |
94 | 80c27194 | ths | #endif
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95 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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96 | c570fd16 | ths | void do_ddiv (void); |
97 | 80c27194 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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98 | c570fd16 | ths | void do_ddivu (void); |
99 | c570fd16 | ths | #endif
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100 | 6af0bf9c | bellard | #endif
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101 | 873eb012 | ths | void do_mfc0_random(void); |
102 | 873eb012 | ths | void do_mfc0_count(void); |
103 | 7a387fff | ths | void do_mtc0_entryhi(uint32_t in);
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104 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val);
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105 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void); |
106 | 6ea83fed | bellard | void dump_fpu(CPUState *env);
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107 | 5fafdf24 | ths | void fpu_dump_state(CPUState *env, FILE *f,
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108 | 6ea83fed | bellard | int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
109 | 6ea83fed | bellard | int flags);
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110 | 6ea83fed | bellard | void dump_sc (void); |
111 | 6af0bf9c | bellard | void do_pmon (int function); |
112 | 6af0bf9c | bellard | |
113 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
114 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
115 | 6af0bf9c | bellard | void do_interrupt (CPUState *env);
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116 | 29929e34 | ths | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); |
117 | 6af0bf9c | bellard | |
118 | 6af0bf9c | bellard | void cpu_loop_exit(void); |
119 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code); |
120 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception);
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121 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code); |
122 | 4ad40f36 | bellard | void do_raise_exception_direct (uint32_t exception);
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123 | 6af0bf9c | bellard | |
124 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
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125 | 6af0bf9c | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
126 | 6af0bf9c | bellard | int flags);
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127 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void); |
128 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env); |
129 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env); |
130 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value);
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131 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value);
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132 | 42532189 | ths | void cpu_mips_start_count(CPUState *env);
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133 | 42532189 | ths | void cpu_mips_stop_count(CPUState *env);
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134 | a4bc3afc | ths | void cpu_mips_update_irq (CPUState *env);
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135 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env);
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136 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
137 | 6af0bf9c | bellard | |
138 | ead9360e | ths | void do_cfc1 (int reg); |
139 | ead9360e | ths | void do_ctc1 (int reg); |
140 | 57fa1fb3 | ths | |
141 | 57fa1fb3 | ths | #define FOP_PROTO(op) \
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142 | 57fa1fb3 | ths | void do_float_ ## op ## _s(void); \ |
143 | 57fa1fb3 | ths | void do_float_ ## op ## _d(void); |
144 | 57fa1fb3 | ths | FOP_PROTO(roundl) |
145 | 57fa1fb3 | ths | FOP_PROTO(roundw) |
146 | 57fa1fb3 | ths | FOP_PROTO(truncl) |
147 | 57fa1fb3 | ths | FOP_PROTO(truncw) |
148 | 57fa1fb3 | ths | FOP_PROTO(ceill) |
149 | 57fa1fb3 | ths | FOP_PROTO(ceilw) |
150 | 57fa1fb3 | ths | FOP_PROTO(floorl) |
151 | 57fa1fb3 | ths | FOP_PROTO(floorw) |
152 | 57fa1fb3 | ths | FOP_PROTO(rsqrt) |
153 | 57fa1fb3 | ths | FOP_PROTO(recip) |
154 | 57fa1fb3 | ths | #undef FOP_PROTO
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155 | 57fa1fb3 | ths | |
156 | 57fa1fb3 | ths | #define FOP_PROTO(op) \
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157 | 57fa1fb3 | ths | void do_float_ ## op ## _s(void); \ |
158 | 57fa1fb3 | ths | void do_float_ ## op ## _d(void); \ |
159 | 57fa1fb3 | ths | void do_float_ ## op ## _ps(void); |
160 | 57fa1fb3 | ths | FOP_PROTO(add) |
161 | 57fa1fb3 | ths | FOP_PROTO(sub) |
162 | 57fa1fb3 | ths | FOP_PROTO(mul) |
163 | 57fa1fb3 | ths | FOP_PROTO(div) |
164 | 57fa1fb3 | ths | FOP_PROTO(recip1) |
165 | 57fa1fb3 | ths | FOP_PROTO(recip2) |
166 | 57fa1fb3 | ths | FOP_PROTO(rsqrt1) |
167 | 57fa1fb3 | ths | FOP_PROTO(rsqrt2) |
168 | 57fa1fb3 | ths | #undef FOP_PROTO
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169 | 57fa1fb3 | ths | |
170 | fd4a04eb | ths | void do_float_cvtd_s(void); |
171 | fd4a04eb | ths | void do_float_cvtd_w(void); |
172 | fd4a04eb | ths | void do_float_cvtd_l(void); |
173 | fd4a04eb | ths | void do_float_cvtl_d(void); |
174 | fd4a04eb | ths | void do_float_cvtl_s(void); |
175 | fd4a04eb | ths | void do_float_cvtps_pw(void); |
176 | fd4a04eb | ths | void do_float_cvtpw_ps(void); |
177 | fd4a04eb | ths | void do_float_cvts_d(void); |
178 | fd4a04eb | ths | void do_float_cvts_w(void); |
179 | fd4a04eb | ths | void do_float_cvts_l(void); |
180 | fd4a04eb | ths | void do_float_cvts_pl(void); |
181 | fd4a04eb | ths | void do_float_cvts_pu(void); |
182 | fd4a04eb | ths | void do_float_cvtw_s(void); |
183 | fd4a04eb | ths | void do_float_cvtw_d(void); |
184 | 57fa1fb3 | ths | |
185 | fd4a04eb | ths | void do_float_addr_ps(void); |
186 | 57fa1fb3 | ths | void do_float_mulr_ps(void); |
187 | fd4a04eb | ths | |
188 | 57fa1fb3 | ths | #define FOP_PROTO(op) \
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189 | fd4a04eb | ths | void do_cmp_d_ ## op(long cc); \ |
190 | fd4a04eb | ths | void do_cmpabs_d_ ## op(long cc); \ |
191 | fd4a04eb | ths | void do_cmp_s_ ## op(long cc); \ |
192 | fd4a04eb | ths | void do_cmpabs_s_ ## op(long cc); \ |
193 | fd4a04eb | ths | void do_cmp_ps_ ## op(long cc); \ |
194 | fd4a04eb | ths | void do_cmpabs_ps_ ## op(long cc); |
195 | fd4a04eb | ths | |
196 | 57fa1fb3 | ths | FOP_PROTO(f) |
197 | 57fa1fb3 | ths | FOP_PROTO(un) |
198 | 57fa1fb3 | ths | FOP_PROTO(eq) |
199 | 57fa1fb3 | ths | FOP_PROTO(ueq) |
200 | 57fa1fb3 | ths | FOP_PROTO(olt) |
201 | 57fa1fb3 | ths | FOP_PROTO(ult) |
202 | 57fa1fb3 | ths | FOP_PROTO(ole) |
203 | 57fa1fb3 | ths | FOP_PROTO(ule) |
204 | 57fa1fb3 | ths | FOP_PROTO(sf) |
205 | 57fa1fb3 | ths | FOP_PROTO(ngle) |
206 | 57fa1fb3 | ths | FOP_PROTO(seq) |
207 | 57fa1fb3 | ths | FOP_PROTO(ngl) |
208 | 57fa1fb3 | ths | FOP_PROTO(lt) |
209 | 57fa1fb3 | ths | FOP_PROTO(nge) |
210 | 57fa1fb3 | ths | FOP_PROTO(le) |
211 | 57fa1fb3 | ths | FOP_PROTO(ngt) |
212 | 57fa1fb3 | ths | #undef FOP_PROTO
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213 | fd4a04eb | ths | |
214 | aa343735 | ths | static always_inline void env_to_regs(void) |
215 | bfed01fc | ths | { |
216 | bfed01fc | ths | } |
217 | bfed01fc | ths | |
218 | aa343735 | ths | static always_inline void regs_to_env(void) |
219 | bfed01fc | ths | { |
220 | bfed01fc | ths | } |
221 | bfed01fc | ths | |
222 | aa343735 | ths | static always_inline int cpu_halted(CPUState *env) |
223 | 08fa4bab | ths | { |
224 | bfed01fc | ths | if (!env->halted)
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225 | bfed01fc | ths | return 0; |
226 | bfed01fc | ths | if (env->interrupt_request &
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227 | bfed01fc | ths | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { |
228 | bfed01fc | ths | env->halted = 0;
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229 | bfed01fc | ths | return 0; |
230 | bfed01fc | ths | } |
231 | bfed01fc | ths | return EXCP_HALTED;
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232 | bfed01fc | ths | } |
233 | bfed01fc | ths | |
234 | aa343735 | ths | static always_inline void compute_hflags(CPUState *env) |
235 | 08fa4bab | ths | { |
236 | b8aa4598 | ths | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
237 | b8aa4598 | ths | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU); |
238 | 08fa4bab | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
239 | 08fa4bab | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
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240 | 671880e6 | ths | !(env->hflags & MIPS_HFLAG_DM)) { |
241 | 623a930e | ths | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
242 | 671880e6 | ths | } |
243 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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244 | 623a930e | ths | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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245 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_PX)) ||
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246 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_UX)))
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247 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64; |
248 | 08fa4bab | ths | #endif
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249 | 671880e6 | ths | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
250 | 623a930e | ths | !(env->hflags & MIPS_HFLAG_KSU)) |
251 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_CP0; |
252 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_CU1)) |
253 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_FPU; |
254 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_FR)) |
255 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_F64; |
256 | b8aa4598 | ths | if (env->insn_flags & ISA_MIPS32R2) {
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257 | a139a3ad | ths | if (env->fpu->fcr0 & (1 << FCR0_F64)) |
258 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
259 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS32) { |
260 | b8aa4598 | ths | if (env->hflags & MIPS_HFLAG_64)
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261 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
262 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS4) { |
263 | b8aa4598 | ths | /* All supported MIPS IV CPUs use the XX (CU3) to enable
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264 | b8aa4598 | ths | and disable the MIPS IV extensions to the MIPS III ISA.
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265 | b8aa4598 | ths | Some other MIPS IV CPUs ignore the bit, so the check here
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266 | b8aa4598 | ths | would be too restrictive for them. */
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267 | b8aa4598 | ths | if (env->CP0_Status & (1 << CP0St_CU3)) |
268 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
269 | b8aa4598 | ths | } |
270 | 08fa4bab | ths | } |
271 | 08fa4bab | ths | |
272 | 6af0bf9c | bellard | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |