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/*
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* OneNAND flash memories emulation.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "qemu-common.h" |
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#include "flash.h" |
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#include "irq.h" |
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#include "sysemu.h" |
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#include "block.h" |
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11 |
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6) |
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struct onenand_s {
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uint32_t id; |
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int shift;
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target_phys_addr_t base; |
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qemu_irq intr; |
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qemu_irq rdy; |
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BlockDriverState *bdrv; |
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BlockDriverState *bdrv_cur; |
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uint8_t *image; |
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uint8_t *otp; |
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uint8_t *current; |
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ram_addr_t ram; |
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uint8_t *boot[2];
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uint8_t *data[2][2]; |
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int iomemtype;
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int cycle;
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int otpmode;
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uint16_t addr[8];
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uint16_t unladdr[8];
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int bufaddr;
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int count;
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uint16_t command; |
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uint16_t config[2];
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uint16_t status; |
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uint16_t intstatus; |
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uint16_t wpstatus; |
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struct ecc_state_s ecc;
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int density_mask;
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int secs;
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int secs_cur;
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int blocks;
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uint8_t *blockwp; |
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}; |
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enum {
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ONEN_BUF_BLOCK = 0,
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ONEN_BUF_BLOCK2 = 1,
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ONEN_BUF_DEST_BLOCK = 2,
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ONEN_BUF_DEST_PAGE = 3,
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ONEN_BUF_PAGE = 7,
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}; |
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enum {
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ONEN_ERR_CMD = 1 << 10, |
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ONEN_ERR_ERASE = 1 << 11, |
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ONEN_ERR_PROG = 1 << 12, |
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ONEN_ERR_LOAD = 1 << 13, |
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}; |
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enum {
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ONEN_INT_RESET = 1 << 4, |
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ONEN_INT_ERASE = 1 << 5, |
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ONEN_INT_PROG = 1 << 6, |
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ONEN_INT_LOAD = 1 << 7, |
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ONEN_INT = 1 << 15, |
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}; |
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enum {
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ONEN_LOCK_LOCKTIGHTEN = 1 << 0, |
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ONEN_LOCK_LOCKED = 1 << 1, |
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ONEN_LOCK_UNLOCKED = 1 << 2, |
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}; |
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void onenand_base_update(void *opaque, target_phys_addr_t new) |
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{ |
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struct onenand_s *s = (struct onenand_s *) opaque; |
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s->base = new; |
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/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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* write boot commands. Also take note of the BWPS bit. */
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cpu_register_physical_memory(s->base + (0x0000 << s->shift),
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0x0200 << s->shift, s->iomemtype);
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cpu_register_physical_memory(s->base + (0x0200 << s->shift),
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0xbe00 << s->shift,
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(s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
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if (s->iomemtype)
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cpu_register_physical_memory(s->base + (0xc000 << s->shift),
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0x4000 << s->shift, s->iomemtype);
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} |
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void onenand_base_unmap(void *opaque) |
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{ |
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struct onenand_s *s = (struct onenand_s *) opaque; |
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cpu_register_physical_memory(s->base, |
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0x10000 << s->shift, IO_MEM_UNASSIGNED);
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} |
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static void onenand_intr_update(struct onenand_s *s) |
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{ |
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qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
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} |
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/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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static void onenand_reset(struct onenand_s *s, int cold) |
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{ |
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memset(&s->addr, 0, sizeof(s->addr)); |
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s->command = 0;
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s->count = 1;
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s->bufaddr = 0;
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s->config[0] = 0x40c0; |
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s->config[1] = 0x0000; |
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onenand_intr_update(s); |
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qemu_irq_raise(s->rdy); |
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s->status = 0x0000;
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s->intstatus = cold ? 0x8080 : 0x8010; |
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s->unladdr[0] = 0; |
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s->unladdr[1] = 0; |
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s->wpstatus = 0x0002;
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s->cycle = 0;
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s->otpmode = 0;
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s->bdrv_cur = s->bdrv; |
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s->current = s->image; |
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s->secs_cur = s->secs; |
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if (cold) {
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/* Lock the whole flash */
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memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); |
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if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0) |
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cpu_abort(cpu_single_env, "%s: Loading the BootRAM failed.\n",
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__FUNCTION__); |
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} |
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} |
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static inline int onenand_load_main(struct onenand_s *s, int sec, int secn, |
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void *dest)
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{ |
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if (s->bdrv_cur)
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return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(dest, s->current + (sec << 9), secn << 9); |
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return 0; |
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} |
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static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn, |
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void *src)
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{ |
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if (s->bdrv_cur)
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return bdrv_write(s->bdrv_cur, sec, src, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (sec << 9), src, secn << 9); |
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return 0; |
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} |
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static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn, |
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void *dest)
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{ |
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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else
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memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
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return 0; |
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} |
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static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn, |
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void *src)
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{ |
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(buf + ((sec & 31) << 4), src, secn << 4); |
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return bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0; |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (s->secs_cur << 9) + (sec << 4), src, secn << 4); |
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return 0; |
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} |
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static inline int onenand_erase(struct onenand_s *s, int sec, int num) |
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{ |
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/* TODO: optimise */
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uint8_t buf[512];
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memset(buf, 0xff, sizeof(buf)); |
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for (; num > 0; num --, sec ++) { |
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if (onenand_prog_main(s, sec, 1, buf)) |
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return 1; |
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if (onenand_prog_spare(s, sec, 1, buf)) |
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return 1; |
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} |
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return 0; |
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} |
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static void onenand_command(struct onenand_s *s, int cmd) |
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{ |
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \ |
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9)); |
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ |
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buf += (s->bufaddr & 3) << 9; |
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ |
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buf += (s->bufaddr & 3) << 4; |
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switch (cmd) {
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case 0x00: /* Load single/multiple sector data unit into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_M() |
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if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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#if 0
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SETBUF_S()
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x13: /* Load single/multiple spare sector into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_S() |
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x80: /* Program single/multiple sector data unit from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_M() |
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if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
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#if 0
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SETBUF_S()
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
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case 0x1a: /* Program single/multiple spare area sector from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_S() |
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
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case 0x1b: /* Copy-back program */ |
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SETBUF_S() |
329 |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
331 |
if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
333 |
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SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) |
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if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
337 |
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/* TODO: spare areas */
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|
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
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case 0x23: /* Unlock NAND array block(s) */ |
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s->intstatus |= ONEN_INT; |
345 |
|
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/* XXX the previous (?) area should be locked automatically */
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
348 |
if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD; |
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break;
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} |
352 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
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break;
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
356 |
} |
357 |
break;
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case 0x2a: /* Lock NAND array block(s) */ |
359 |
s->intstatus |= ONEN_INT; |
360 |
|
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
362 |
if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD; |
364 |
break;
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} |
366 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
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break;
|
368 |
|
369 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; |
370 |
} |
371 |
break;
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case 0x2c: /* Lock-tight NAND array block(s) */ |
373 |
s->intstatus |= ONEN_INT; |
374 |
|
375 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
376 |
if (b >= s->blocks) {
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377 |
s->status |= ONEN_ERR_CMD; |
378 |
break;
|
379 |
} |
380 |
if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
381 |
continue;
|
382 |
|
383 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; |
384 |
} |
385 |
break;
|
386 |
|
387 |
case 0x71: /* Erase-Verify-Read */ |
388 |
s->intstatus |= ONEN_INT; |
389 |
break;
|
390 |
case 0x95: /* Multi-block erase */ |
391 |
qemu_irq_pulse(s->intr); |
392 |
/* Fall through. */
|
393 |
case 0x94: /* Block erase */ |
394 |
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
395 |
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) |
396 |
<< (BLOCK_SHIFT - 9);
|
397 |
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) |
398 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; |
399 |
|
400 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
401 |
break;
|
402 |
case 0xb0: /* Erase suspend */ |
403 |
break;
|
404 |
case 0x30: /* Erase resume */ |
405 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
406 |
break;
|
407 |
|
408 |
case 0xf0: /* Reset NAND Flash core */ |
409 |
onenand_reset(s, 0);
|
410 |
break;
|
411 |
case 0xf3: /* Reset OneNAND */ |
412 |
onenand_reset(s, 0);
|
413 |
break;
|
414 |
|
415 |
case 0x65: /* OTP Access */ |
416 |
s->intstatus |= ONEN_INT; |
417 |
s->bdrv_cur = 0;
|
418 |
s->current = s->otp; |
419 |
s->secs_cur = 1 << (BLOCK_SHIFT - 9); |
420 |
s->addr[ONEN_BUF_BLOCK] = 0;
|
421 |
s->otpmode = 1;
|
422 |
break;
|
423 |
|
424 |
default:
|
425 |
s->status |= ONEN_ERR_CMD; |
426 |
s->intstatus |= ONEN_INT; |
427 |
fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
428 |
__FUNCTION__, cmd); |
429 |
} |
430 |
|
431 |
onenand_intr_update(s); |
432 |
} |
433 |
|
434 |
static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) |
435 |
{ |
436 |
struct onenand_s *s = (struct onenand_s *) opaque; |
437 |
int offset = (addr - s->base) >> s->shift;
|
438 |
|
439 |
switch (offset) {
|
440 |
case 0x0000 ... 0xc000: |
441 |
return lduw_le_p(s->boot[0] + (addr - s->base)); |
442 |
|
443 |
case 0xf000: /* Manufacturer ID */ |
444 |
return (s->id >> 16) & 0xff; |
445 |
case 0xf001: /* Device ID */ |
446 |
return (s->id >> 8) & 0xff; |
447 |
/* TODO: get the following values from a real chip! */
|
448 |
case 0xf002: /* Version ID */ |
449 |
return (s->id >> 0) & 0xff; |
450 |
case 0xf003: /* Data Buffer size */ |
451 |
return 1 << PAGE_SHIFT; |
452 |
case 0xf004: /* Boot Buffer size */ |
453 |
return 0x200; |
454 |
case 0xf005: /* Amount of buffers */ |
455 |
return 1 | (2 << 8); |
456 |
case 0xf006: /* Technology */ |
457 |
return 0; |
458 |
|
459 |
case 0xf100 ... 0xf107: /* Start addresses */ |
460 |
return s->addr[offset - 0xf100]; |
461 |
|
462 |
case 0xf200: /* Start buffer */ |
463 |
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
464 |
|
465 |
case 0xf220: /* Command */ |
466 |
return s->command;
|
467 |
case 0xf221: /* System Configuration 1 */ |
468 |
return s->config[0] & 0xffe0; |
469 |
case 0xf222: /* System Configuration 2 */ |
470 |
return s->config[1]; |
471 |
|
472 |
case 0xf240: /* Controller Status */ |
473 |
return s->status;
|
474 |
case 0xf241: /* Interrupt */ |
475 |
return s->intstatus;
|
476 |
case 0xf24c: /* Unlock Start Block Address */ |
477 |
return s->unladdr[0]; |
478 |
case 0xf24d: /* Unlock End Block Address */ |
479 |
return s->unladdr[1]; |
480 |
case 0xf24e: /* Write Protection Status */ |
481 |
return s->wpstatus;
|
482 |
|
483 |
case 0xff00: /* ECC Status */ |
484 |
return 0x00; |
485 |
case 0xff01: /* ECC Result of main area data */ |
486 |
case 0xff02: /* ECC Result of spare area data */ |
487 |
case 0xff03: /* ECC Result of main area data */ |
488 |
case 0xff04: /* ECC Result of spare area data */ |
489 |
cpu_abort(cpu_single_env, "%s: imeplement ECC\n", __FUNCTION__);
|
490 |
return 0x0000; |
491 |
} |
492 |
|
493 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
494 |
__FUNCTION__, offset); |
495 |
return 0; |
496 |
} |
497 |
|
498 |
static void onenand_write(void *opaque, target_phys_addr_t addr, |
499 |
uint32_t value) |
500 |
{ |
501 |
struct onenand_s *s = (struct onenand_s *) opaque; |
502 |
int offset = (addr - s->base) >> s->shift;
|
503 |
int sec;
|
504 |
|
505 |
switch (offset) {
|
506 |
case 0x0000 ... 0x01ff: |
507 |
case 0x8000 ... 0x800f: |
508 |
if (s->cycle) {
|
509 |
s->cycle = 0;
|
510 |
|
511 |
if (value == 0x0000) { |
512 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
513 |
onenand_load_main(s, sec, |
514 |
1 << (PAGE_SHIFT - 9), s->data[0][0]); |
515 |
s->addr[ONEN_BUF_PAGE] += 4;
|
516 |
s->addr[ONEN_BUF_PAGE] &= 0xff;
|
517 |
} |
518 |
break;
|
519 |
} |
520 |
|
521 |
switch (value) {
|
522 |
case 0x00f0: /* Reset OneNAND */ |
523 |
onenand_reset(s, 0);
|
524 |
break;
|
525 |
|
526 |
case 0x00e0: /* Load Data into Buffer */ |
527 |
s->cycle = 1;
|
528 |
break;
|
529 |
|
530 |
case 0x0090: /* Read Identification Data */ |
531 |
memset(s->boot[0], 0, 3 << s->shift); |
532 |
s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff; |
533 |
s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff; |
534 |
s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
535 |
break;
|
536 |
|
537 |
default:
|
538 |
fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
|
539 |
__FUNCTION__, value); |
540 |
} |
541 |
break;
|
542 |
|
543 |
case 0xf100 ... 0xf107: /* Start addresses */ |
544 |
s->addr[offset - 0xf100] = value;
|
545 |
break;
|
546 |
|
547 |
case 0xf200: /* Start buffer */ |
548 |
s->bufaddr = (value >> 8) & 0xf; |
549 |
if (PAGE_SHIFT == 11) |
550 |
s->count = (value & 3) ?: 4; |
551 |
else if (PAGE_SHIFT == 10) |
552 |
s->count = (value & 1) ?: 2; |
553 |
break;
|
554 |
|
555 |
case 0xf220: /* Command */ |
556 |
if (s->intstatus & (1 << 15)) |
557 |
break;
|
558 |
s->command = value; |
559 |
onenand_command(s, s->command); |
560 |
break;
|
561 |
case 0xf221: /* System Configuration 1 */ |
562 |
s->config[0] = value;
|
563 |
onenand_intr_update(s); |
564 |
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); |
565 |
break;
|
566 |
case 0xf222: /* System Configuration 2 */ |
567 |
s->config[1] = value;
|
568 |
break;
|
569 |
|
570 |
case 0xf241: /* Interrupt */ |
571 |
s->intstatus &= value; |
572 |
if ((1 << 15) & ~s->intstatus) |
573 |
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | |
574 |
ONEN_ERR_PROG | ONEN_ERR_LOAD); |
575 |
onenand_intr_update(s); |
576 |
break;
|
577 |
case 0xf24c: /* Unlock Start Block Address */ |
578 |
s->unladdr[0] = value & (s->blocks - 1); |
579 |
/* For some reason we have to set the end address to by default
|
580 |
* be same as start because the software forgets to write anything
|
581 |
* in there. */
|
582 |
s->unladdr[1] = value & (s->blocks - 1); |
583 |
break;
|
584 |
case 0xf24d: /* Unlock End Block Address */ |
585 |
s->unladdr[1] = value & (s->blocks - 1); |
586 |
break;
|
587 |
|
588 |
default:
|
589 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
590 |
__FUNCTION__, offset); |
591 |
} |
592 |
} |
593 |
|
594 |
static CPUReadMemoryFunc *onenand_readfn[] = {
|
595 |
onenand_read, /* TODO */
|
596 |
onenand_read, |
597 |
onenand_read, |
598 |
}; |
599 |
|
600 |
static CPUWriteMemoryFunc *onenand_writefn[] = {
|
601 |
onenand_write, /* TODO */
|
602 |
onenand_write, |
603 |
onenand_write, |
604 |
}; |
605 |
|
606 |
void *onenand_init(uint32_t id, int regshift, qemu_irq irq) |
607 |
{ |
608 |
struct onenand_s *s = (struct onenand_s *) qemu_mallocz(sizeof(*s)); |
609 |
int bdrv_index = drive_get_index(IF_MTD, 0, 0); |
610 |
uint32_t size = 1 << (24 + ((id >> 12) & 7)); |
611 |
void *ram;
|
612 |
|
613 |
s->shift = regshift; |
614 |
s->intr = irq; |
615 |
s->rdy = 0;
|
616 |
s->id = id; |
617 |
s->blocks = size >> BLOCK_SHIFT; |
618 |
s->secs = size >> 9;
|
619 |
s->blockwp = qemu_malloc(s->blocks); |
620 |
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; |
621 |
s->iomemtype = cpu_register_io_memory(0, onenand_readfn,
|
622 |
onenand_writefn, s); |
623 |
if (bdrv_index == -1) |
624 |
s->image = memset(qemu_malloc(size + (size >> 5)),
|
625 |
0xff, size + (size >> 5)); |
626 |
else
|
627 |
s->bdrv = drives_table[bdrv_index].bdrv; |
628 |
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), |
629 |
0xff, (64 + 2) << PAGE_SHIFT); |
630 |
s->ram = qemu_ram_alloc(0xc000 << s->shift);
|
631 |
ram = phys_ram_base + s->ram; |
632 |
s->boot[0] = ram + (0x0000 << s->shift); |
633 |
s->boot[1] = ram + (0x8000 << s->shift); |
634 |
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); |
635 |
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); |
636 |
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); |
637 |
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); |
638 |
|
639 |
onenand_reset(s, 1);
|
640 |
|
641 |
return s;
|
642 |
} |