root / hw / pflash_cfi01.c @ 1ffc346f
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/*
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* CFI parallel flash with Intel command set emulation
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*
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* Copyright (c) 2006 Thorsten Zitterell
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - CFI queries
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*
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* It does not support timings
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* It does not support flash interleaving
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*
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* It does not implement much more ...
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*/
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#include "hw.h" |
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#include "flash.h" |
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#include "block.h" |
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#include "qemu-timer.h" |
44 |
|
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#define PFLASH_BUG(fmt, args...) \
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do { \
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printf("PFLASH: Possible BUG - " fmt, ##args); \ |
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exit(1); \
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} while(0) |
50 |
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/* #define PFLASH_DEBUG */
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, args...) \
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do { \
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printf("PFLASH: " fmt , ##args); \ |
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} while (0) |
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#else
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#define DPRINTF(fmt, args...) do { } while (0) |
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#endif
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struct pflash_t {
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BlockDriverState *bs; |
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target_ulong base; |
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target_ulong sector_len; |
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target_ulong total_len; |
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int width;
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int wcycle; /* if 0, the flash is read normally */ |
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int bypass;
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int ro;
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uint8_t cmd; |
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uint8_t status; |
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uint16_t ident[4];
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uint8_t cfi_len; |
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uint8_t cfi_table[0x52];
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target_ulong counter; |
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QEMUTimer *timer; |
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ram_addr_t off; |
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int fl_mem;
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void *storage;
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}; |
81 |
|
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static void pflash_timer (void *opaque) |
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{ |
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pflash_t *pfl = opaque; |
85 |
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */
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pfl->status ^= 0x80;
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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cpu_register_physical_memory(pfl->base, pfl->total_len, |
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pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
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pfl->wcycle = 0;
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} |
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pfl->cmd = 0;
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} |
98 |
|
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static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width) |
100 |
{ |
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target_ulong boff; |
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uint32_t ret; |
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uint8_t *p; |
104 |
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ret = -1;
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offset -= pfl->base; |
107 |
boff = offset & 0xFF; /* why this here ?? */ |
108 |
|
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if (pfl->width == 2) |
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boff = boff >> 1;
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else if (pfl->width == 4) |
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boff = boff >> 2;
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|
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DPRINTF("%s: reading offset " TARGET_FMT_lx " under cmd %02x\n", |
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__func__, boff, pfl->cmd); |
116 |
|
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switch (pfl->cmd) {
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case 0x00: |
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/* Flash area read */
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p = pfl->storage; |
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switch (width) {
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case 1: |
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ret = p[offset]; |
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DPRINTF("%s: data offset " TARGET_FMT_lx " %02x\n", |
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__func__, offset, ret); |
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break;
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case 2: |
128 |
#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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#else
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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#endif
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DPRINTF("%s: data offset " TARGET_FMT_lx " %04x\n", |
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__func__, offset, ret); |
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break;
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case 4: |
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16; |
142 |
ret |= p[offset + 2] << 8; |
143 |
ret |= p[offset + 3];
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#else
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ret = p[offset]; |
146 |
ret |= p[offset + 1] << 8; |
147 |
ret |= p[offset + 1] << 8; |
148 |
ret |= p[offset + 2] << 16; |
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ret |= p[offset + 3] << 24; |
150 |
#endif
|
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DPRINTF("%s: data offset " TARGET_FMT_lx " %08x\n", |
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__func__, offset, ret); |
153 |
break;
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default:
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DPRINTF("BUG in %s\n", __func__);
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} |
157 |
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break;
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case 0x20: /* Block erase */ |
160 |
case 0x50: /* Clear status register */ |
161 |
case 0x60: /* Block /un)lock */ |
162 |
case 0x70: /* Status Register */ |
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case 0xe8: /* Write block */ |
164 |
/* Status register read */
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ret = pfl->status; |
166 |
DPRINTF("%s: status %x\n", __func__, ret);
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break;
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case 0x98: /* Query mode */ |
169 |
if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff]; |
173 |
break;
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default:
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/* This should never happen : reset state & treat it as a read */
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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} |
180 |
return ret;
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} |
182 |
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset, |
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int size)
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{ |
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int offset_end;
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if (pfl->bs) {
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offset_end = offset + size; |
190 |
/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9; |
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bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset); |
195 |
} |
196 |
} |
197 |
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static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value, |
199 |
int width)
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{ |
201 |
target_ulong boff; |
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uint8_t *p; |
203 |
uint8_t cmd; |
204 |
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/* WARNING: when the memory area is in ROMD mode, the offset is a
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ram offset, not a physical address */
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cmd = value; |
208 |
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if (pfl->wcycle == 0) |
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offset -= (target_ulong)(long)pfl->storage;
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else
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offset -= pfl->base; |
213 |
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DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d wcycle 0x%x\n", |
215 |
__func__, offset, value, width, pfl->wcycle); |
216 |
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/* Set the device in I/O access mode */
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cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); |
219 |
boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2) |
222 |
boff = boff >> 1;
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else if (pfl->width == 4) |
224 |
boff = boff >> 2;
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switch (pfl->wcycle) {
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case 0: |
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/* read mode */
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switch (cmd) {
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case 0x00: /* ??? */ |
231 |
goto reset_flash;
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case 0x20: /* Block erase */ |
233 |
p = pfl->storage; |
234 |
offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: block erase at " TARGET_FMT_lx " bytes " |
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TARGET_FMT_lx "\n",
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__func__, offset, pfl->sector_len); |
239 |
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memset(p + offset, 0xff, pfl->sector_len);
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pflash_update(pfl, offset, pfl->sector_len); |
242 |
pfl->status |= 0x80; /* Ready! */ |
243 |
break;
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case 0x50: /* Clear status bits */ |
245 |
DPRINTF("%s: Clear status bits\n", __func__);
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pfl->status = 0x0;
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goto reset_flash;
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case 0x60: /* Block (un)lock */ |
249 |
DPRINTF("%s: Block unlock\n", __func__);
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break;
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case 0x70: /* Status Register */ |
252 |
DPRINTF("%s: Read status register\n", __func__);
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pfl->cmd = cmd; |
254 |
return;
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case 0x98: /* CFI query */ |
256 |
DPRINTF("%s: CFI query\n", __func__);
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break;
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case 0xe8: /* Write to buffer */ |
259 |
DPRINTF("%s: Write to buffer\n", __func__);
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pfl->status |= 0x80; /* Ready! */ |
261 |
break;
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case 0xff: /* Read array mode */ |
263 |
DPRINTF("%s: Read array mode\n", __func__);
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goto reset_flash;
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default:
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goto error_flash;
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} |
268 |
pfl->wcycle++; |
269 |
pfl->cmd = cmd; |
270 |
return;
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case 1: |
272 |
switch (pfl->cmd) {
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case 0x20: /* Block erase */ |
274 |
case 0x28: |
275 |
if (cmd == 0xd0) { /* confirm */ |
276 |
pfl->wcycle = 1;
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pfl->status |= 0x80;
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} else if (cmd == 0xff) { /* read array mode */ |
279 |
goto reset_flash;
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280 |
} else
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goto error_flash;
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break;
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case 0xe8: |
285 |
DPRINTF("%s: block write of %x bytes\n", __func__, cmd);
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pfl->counter = cmd; |
287 |
pfl->wcycle++; |
288 |
break;
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289 |
case 0x60: |
290 |
if (cmd == 0xd0) { |
291 |
pfl->wcycle = 0;
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292 |
pfl->status |= 0x80;
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} else if (cmd == 0x01) { |
294 |
pfl->wcycle = 0;
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pfl->status |= 0x80;
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296 |
} else if (cmd == 0xff) { |
297 |
goto reset_flash;
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298 |
} else {
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299 |
DPRINTF("%s: Unknown (un)locking command\n", __func__);
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300 |
goto reset_flash;
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301 |
} |
302 |
break;
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303 |
case 0x98: |
304 |
if (cmd == 0xff) { |
305 |
goto reset_flash;
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306 |
} else {
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307 |
DPRINTF("%s: leaving query mode\n", __func__);
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308 |
} |
309 |
break;
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310 |
default:
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311 |
goto error_flash;
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312 |
} |
313 |
return;
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314 |
case 2: |
315 |
switch (pfl->cmd) {
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316 |
case 0xe8: /* Block write */ |
317 |
p = pfl->storage; |
318 |
DPRINTF("%s: block write offset " TARGET_FMT_lx
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319 |
" value %x counter " TARGET_FMT_lx "\n", |
320 |
__func__, offset, value, pfl->counter); |
321 |
switch (width) {
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322 |
case 1: |
323 |
p[offset] = value; |
324 |
pflash_update(pfl, offset, 1);
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325 |
break;
|
326 |
case 2: |
327 |
#if defined(TARGET_WORDS_BIGENDIAN)
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328 |
p[offset] = value >> 8;
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329 |
p[offset + 1] = value;
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330 |
#else
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331 |
p[offset] = value; |
332 |
p[offset + 1] = value >> 8; |
333 |
#endif
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334 |
pflash_update(pfl, offset, 2);
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335 |
break;
|
336 |
case 4: |
337 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
338 |
p[offset] = value >> 24;
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339 |
p[offset + 1] = value >> 16; |
340 |
p[offset + 2] = value >> 8; |
341 |
p[offset + 3] = value;
|
342 |
#else
|
343 |
p[offset] = value; |
344 |
p[offset + 1] = value >> 8; |
345 |
p[offset + 2] = value >> 16; |
346 |
p[offset + 3] = value >> 24; |
347 |
#endif
|
348 |
pflash_update(pfl, offset, 4);
|
349 |
break;
|
350 |
} |
351 |
|
352 |
pfl->status |= 0x80;
|
353 |
|
354 |
if (!pfl->counter) {
|
355 |
DPRINTF("%s: block write finished\n", __func__);
|
356 |
pfl->wcycle++; |
357 |
} |
358 |
|
359 |
pfl->counter--; |
360 |
break;
|
361 |
default:
|
362 |
goto error_flash;
|
363 |
} |
364 |
return;
|
365 |
case 3: /* Confirm mode */ |
366 |
switch (pfl->cmd) {
|
367 |
case 0xe8: /* Block write */ |
368 |
if (cmd == 0xd0) { |
369 |
pfl->wcycle = 0;
|
370 |
pfl->status |= 0x80;
|
371 |
} else {
|
372 |
DPRINTF("%s: unknown command for \"write block\"\n", __func__);
|
373 |
PFLASH_BUG("Write block confirm");
|
374 |
goto reset_flash;
|
375 |
} |
376 |
break;
|
377 |
default:
|
378 |
goto error_flash;
|
379 |
} |
380 |
return;
|
381 |
default:
|
382 |
/* Should never happen */
|
383 |
DPRINTF("%s: invalid write state\n", __func__);
|
384 |
goto reset_flash;
|
385 |
} |
386 |
return;
|
387 |
|
388 |
error_flash:
|
389 |
printf("%s: Unimplemented flash cmd sequence "
|
390 |
"(offset " TARGET_FMT_lx ", wcycle 0x%x cmd 0x%x value 0x%x\n", |
391 |
__func__, offset, pfl->wcycle, pfl->cmd, value); |
392 |
|
393 |
reset_flash:
|
394 |
cpu_register_physical_memory(pfl->base, pfl->total_len, |
395 |
pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
396 |
|
397 |
pfl->bypass = 0;
|
398 |
pfl->wcycle = 0;
|
399 |
pfl->cmd = 0;
|
400 |
return;
|
401 |
} |
402 |
|
403 |
|
404 |
static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
405 |
{ |
406 |
return pflash_read(opaque, addr, 1); |
407 |
} |
408 |
|
409 |
static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
410 |
{ |
411 |
pflash_t *pfl = opaque; |
412 |
|
413 |
return pflash_read(pfl, addr, 2); |
414 |
} |
415 |
|
416 |
static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
417 |
{ |
418 |
pflash_t *pfl = opaque; |
419 |
|
420 |
return pflash_read(pfl, addr, 4); |
421 |
} |
422 |
|
423 |
static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
424 |
uint32_t value) |
425 |
{ |
426 |
pflash_write(opaque, addr, value, 1);
|
427 |
} |
428 |
|
429 |
static void pflash_writew (void *opaque, target_phys_addr_t addr, |
430 |
uint32_t value) |
431 |
{ |
432 |
pflash_t *pfl = opaque; |
433 |
|
434 |
pflash_write(pfl, addr, value, 2);
|
435 |
} |
436 |
|
437 |
static void pflash_writel (void *opaque, target_phys_addr_t addr, |
438 |
uint32_t value) |
439 |
{ |
440 |
pflash_t *pfl = opaque; |
441 |
|
442 |
pflash_write(pfl, addr, value, 4);
|
443 |
} |
444 |
|
445 |
static CPUWriteMemoryFunc *pflash_write_ops[] = {
|
446 |
&pflash_writeb, |
447 |
&pflash_writew, |
448 |
&pflash_writel, |
449 |
}; |
450 |
|
451 |
static CPUReadMemoryFunc *pflash_read_ops[] = {
|
452 |
&pflash_readb, |
453 |
&pflash_readw, |
454 |
&pflash_readl, |
455 |
}; |
456 |
|
457 |
/* Count trailing zeroes of a 32 bits quantity */
|
458 |
static int ctz32 (uint32_t n) |
459 |
{ |
460 |
int ret;
|
461 |
|
462 |
ret = 0;
|
463 |
if (!(n & 0xFFFF)) { |
464 |
ret += 16;
|
465 |
n = n >> 16;
|
466 |
} |
467 |
if (!(n & 0xFF)) { |
468 |
ret += 8;
|
469 |
n = n >> 8;
|
470 |
} |
471 |
if (!(n & 0xF)) { |
472 |
ret += 4;
|
473 |
n = n >> 4;
|
474 |
} |
475 |
if (!(n & 0x3)) { |
476 |
ret += 2;
|
477 |
n = n >> 2;
|
478 |
} |
479 |
if (!(n & 0x1)) { |
480 |
ret++; |
481 |
n = n >> 1;
|
482 |
} |
483 |
#if 0 /* This is not necessary as n is never 0 */
|
484 |
if (!n)
|
485 |
ret++;
|
486 |
#endif
|
487 |
|
488 |
return ret;
|
489 |
} |
490 |
|
491 |
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
492 |
BlockDriverState *bs, uint32_t sector_len, |
493 |
int nb_blocs, int width, |
494 |
uint16_t id0, uint16_t id1, |
495 |
uint16_t id2, uint16_t id3) |
496 |
{ |
497 |
pflash_t *pfl; |
498 |
target_long total_len; |
499 |
|
500 |
total_len = sector_len * nb_blocs; |
501 |
|
502 |
/* XXX: to be fixed */
|
503 |
#if 0
|
504 |
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
505 |
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
506 |
return NULL;
|
507 |
#endif
|
508 |
|
509 |
pfl = qemu_mallocz(sizeof(pflash_t));
|
510 |
|
511 |
if (pfl == NULL) |
512 |
return NULL; |
513 |
pfl->storage = phys_ram_base + off; |
514 |
pfl->fl_mem = cpu_register_io_memory(0,
|
515 |
pflash_read_ops, pflash_write_ops, pfl); |
516 |
pfl->off = off; |
517 |
cpu_register_physical_memory(base, total_len, |
518 |
off | pfl->fl_mem | IO_MEM_ROMD); |
519 |
|
520 |
pfl->bs = bs; |
521 |
if (pfl->bs) {
|
522 |
/* read the initial flash content */
|
523 |
bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
524 |
} |
525 |
#if 0 /* XXX: there should be a bit to set up read-only,
|
526 |
* the same way the hardware does (with WP pin).
|
527 |
*/
|
528 |
pfl->ro = 1;
|
529 |
#else
|
530 |
pfl->ro = 0;
|
531 |
#endif
|
532 |
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
533 |
pfl->base = base; |
534 |
pfl->sector_len = sector_len; |
535 |
pfl->total_len = total_len; |
536 |
pfl->width = width; |
537 |
pfl->wcycle = 0;
|
538 |
pfl->cmd = 0;
|
539 |
pfl->status = 0;
|
540 |
pfl->ident[0] = id0;
|
541 |
pfl->ident[1] = id1;
|
542 |
pfl->ident[2] = id2;
|
543 |
pfl->ident[3] = id3;
|
544 |
/* Hardcoded CFI table */
|
545 |
pfl->cfi_len = 0x52;
|
546 |
/* Standard "QRY" string */
|
547 |
pfl->cfi_table[0x10] = 'Q'; |
548 |
pfl->cfi_table[0x11] = 'R'; |
549 |
pfl->cfi_table[0x12] = 'Y'; |
550 |
/* Command set (Intel) */
|
551 |
pfl->cfi_table[0x13] = 0x01; |
552 |
pfl->cfi_table[0x14] = 0x00; |
553 |
/* Primary extended table address (none) */
|
554 |
pfl->cfi_table[0x15] = 0x31; |
555 |
pfl->cfi_table[0x16] = 0x00; |
556 |
/* Alternate command set (none) */
|
557 |
pfl->cfi_table[0x17] = 0x00; |
558 |
pfl->cfi_table[0x18] = 0x00; |
559 |
/* Alternate extended table (none) */
|
560 |
pfl->cfi_table[0x19] = 0x00; |
561 |
pfl->cfi_table[0x1A] = 0x00; |
562 |
/* Vcc min */
|
563 |
pfl->cfi_table[0x1B] = 0x45; |
564 |
/* Vcc max */
|
565 |
pfl->cfi_table[0x1C] = 0x55; |
566 |
/* Vpp min (no Vpp pin) */
|
567 |
pfl->cfi_table[0x1D] = 0x00; |
568 |
/* Vpp max (no Vpp pin) */
|
569 |
pfl->cfi_table[0x1E] = 0x00; |
570 |
/* Reserved */
|
571 |
pfl->cfi_table[0x1F] = 0x07; |
572 |
/* Timeout for min size buffer write */
|
573 |
pfl->cfi_table[0x20] = 0x07; |
574 |
/* Typical timeout for block erase */
|
575 |
pfl->cfi_table[0x21] = 0x0a; |
576 |
/* Typical timeout for full chip erase (4096 ms) */
|
577 |
pfl->cfi_table[0x22] = 0x00; |
578 |
/* Reserved */
|
579 |
pfl->cfi_table[0x23] = 0x04; |
580 |
/* Max timeout for buffer write */
|
581 |
pfl->cfi_table[0x24] = 0x04; |
582 |
/* Max timeout for block erase */
|
583 |
pfl->cfi_table[0x25] = 0x04; |
584 |
/* Max timeout for chip erase */
|
585 |
pfl->cfi_table[0x26] = 0x00; |
586 |
/* Device size */
|
587 |
pfl->cfi_table[0x27] = ctz32(total_len); // + 1; |
588 |
/* Flash device interface (8 & 16 bits) */
|
589 |
pfl->cfi_table[0x28] = 0x02; |
590 |
pfl->cfi_table[0x29] = 0x00; |
591 |
/* Max number of bytes in multi-bytes write */
|
592 |
pfl->cfi_table[0x2A] = 0x04; |
593 |
pfl->cfi_table[0x2B] = 0x00; |
594 |
/* Number of erase block regions (uniform) */
|
595 |
pfl->cfi_table[0x2C] = 0x01; |
596 |
/* Erase block region 1 */
|
597 |
pfl->cfi_table[0x2D] = nb_blocs - 1; |
598 |
pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
599 |
pfl->cfi_table[0x2F] = sector_len >> 8; |
600 |
pfl->cfi_table[0x30] = sector_len >> 16; |
601 |
|
602 |
/* Extended */
|
603 |
pfl->cfi_table[0x31] = 'P'; |
604 |
pfl->cfi_table[0x32] = 'R'; |
605 |
pfl->cfi_table[0x33] = 'I'; |
606 |
|
607 |
pfl->cfi_table[0x34] = '1'; |
608 |
pfl->cfi_table[0x35] = '1'; |
609 |
|
610 |
pfl->cfi_table[0x36] = 0x00; |
611 |
pfl->cfi_table[0x37] = 0x00; |
612 |
pfl->cfi_table[0x38] = 0x00; |
613 |
pfl->cfi_table[0x39] = 0x00; |
614 |
|
615 |
pfl->cfi_table[0x3a] = 0x00; |
616 |
|
617 |
pfl->cfi_table[0x3b] = 0x00; |
618 |
pfl->cfi_table[0x3c] = 0x00; |
619 |
|
620 |
return pfl;
|
621 |
} |