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/*
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* QEMU 16450 UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-char.h" |
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#include "isa.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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#define UART_MCR_RTS 0x02 /* RTS complement */ |
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#define UART_MCR_DTR 0x01 /* DTR complement */ |
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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#define UART_MSR_RI 0x40 /* Ring Indicator */ |
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#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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#define UART_MSR_CTS 0x10 /* Clear to Send */ |
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#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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#define UART_LSR_FE 0x08 /* Frame error indicator */ |
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#define UART_LSR_PE 0x04 /* Parity error indicator */ |
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#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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#define UART_LSR_DR 0x01 /* Receiver data ready */ |
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/*
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* Delay TX IRQ after sending as much characters as the given interval would
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* contain on real hardware. This avoids overloading the guest if it processes
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* its output buffer in a loop inside the TX IRQ handler.
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*/
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#define THROTTLE_TX_INTERVAL 10 /* ms */ |
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struct SerialState {
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uint16_t divider; |
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uint8_t rbr; /* receive register */
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uint8_t ier; |
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uint8_t iir; /* read only */
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uint8_t lcr; |
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uint8_t mcr; |
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uint8_t lsr; /* read only */
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uint8_t msr; /* read only */
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uint8_t scr; |
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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int thr_ipending;
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qemu_irq irq; |
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CharDriverState *chr; |
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int last_break_enable;
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target_phys_addr_t base; |
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int it_shift;
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int baudbase;
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QEMUTimer *tx_timer; |
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int tx_burst;
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}; |
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static void serial_receive_byte(SerialState *s, int ch); |
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static void serial_update_irq(SerialState *s) |
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{ |
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if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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s->iir = UART_IIR_RDI; |
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} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
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s->iir = UART_IIR_THRI; |
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} else {
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s->iir = UART_IIR_NO_INT; |
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} |
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if (s->iir != UART_IIR_NO_INT) {
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qemu_irq_raise(s->irq); |
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} else {
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qemu_irq_lower(s->irq); |
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} |
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} |
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static void serial_tx_done(void *opaque) |
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{ |
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SerialState *s = opaque; |
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if (s->tx_burst < 0) { |
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uint16_t divider; |
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if (s->divider)
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divider = s->divider; |
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else
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divider = 1;
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/* We assume 10 bits/char, OK for this purpose. */
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s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
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(1000000 * 10 / (s->baudbase / divider)); |
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} |
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s->thr_ipending = 1;
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s->lsr |= UART_LSR_THRE; |
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s->lsr |= UART_LSR_TEMT; |
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serial_update_irq(s); |
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} |
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static void serial_update_parameters(SerialState *s) |
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{ |
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int speed, parity, data_bits, stop_bits;
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QEMUSerialSetParams ssp; |
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if (s->lcr & 0x08) { |
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if (s->lcr & 0x10) |
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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} |
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if (s->lcr & 0x04) |
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stop_bits = 2;
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else
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stop_bits = 1;
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data_bits = (s->lcr & 0x03) + 5; |
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if (s->divider == 0) |
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return;
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speed = s->baudbase / s->divider; |
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ssp.speed = speed; |
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ssp.parity = parity; |
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ssp.data_bits = data_bits; |
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ssp.stop_bits = stop_bits; |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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#if 0
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printf("speed=%d parity=%c data=%d stop=%d\n",
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speed, parity, data_bits, stop_bits);
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#endif
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} |
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static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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SerialState *s = opaque; |
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unsigned char ch; |
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addr &= 7;
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#ifdef DEBUG_SERIAL
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printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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default:
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case 0: |
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0xff00) | val;
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serial_update_parameters(s); |
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} else {
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s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_THRE; |
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serial_update_irq(s); |
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ch = val; |
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if (!(s->mcr & UART_MCR_LOOP)) {
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/* when not in loopback mode, send the char */
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qemu_chr_write(s->chr, &ch, 1);
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} else {
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/* in loopback mode, say that we just received a char */
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serial_receive_byte(s, ch); |
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} |
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if (s->tx_burst > 0) { |
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s->tx_burst--; |
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serial_tx_done(s); |
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} else if (s->tx_burst == 0) { |
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s->tx_burst--; |
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qemu_mod_timer(s->tx_timer, qemu_get_clock(vm_clock) + |
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ticks_per_sec * THROTTLE_TX_INTERVAL / 1000);
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} |
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} |
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break;
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case 1: |
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0x00ff) | (val << 8); |
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serial_update_parameters(s); |
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} else {
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s->ier = val & 0x0f;
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if (s->lsr & UART_LSR_THRE) {
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s->thr_ipending = 1;
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} |
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serial_update_irq(s); |
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} |
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break;
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case 2: |
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break;
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case 3: |
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{ |
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int break_enable;
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s->lcr = val; |
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serial_update_parameters(s); |
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break_enable = (val >> 6) & 1; |
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if (break_enable != s->last_break_enable) {
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s->last_break_enable = break_enable; |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
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&break_enable); |
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} |
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} |
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break;
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case 4: |
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s->mcr = val & 0x1f;
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break;
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case 5: |
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break;
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case 6: |
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break;
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case 7: |
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s->scr = val; |
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break;
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} |
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} |
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static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
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{ |
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SerialState *s = opaque; |
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uint32_t ret; |
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addr &= 7;
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switch(addr) {
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default:
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case 0: |
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if (s->lcr & UART_LCR_DLAB) {
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ret = s->divider & 0xff;
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} else {
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ret = s->rbr; |
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s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
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serial_update_irq(s); |
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if (!(s->mcr & UART_MCR_LOOP)) {
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/* in loopback mode, don't receive any data */
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qemu_chr_accept_input(s->chr); |
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} |
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} |
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break;
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case 1: |
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if (s->lcr & UART_LCR_DLAB) {
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ret = (s->divider >> 8) & 0xff; |
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} else {
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ret = s->ier; |
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} |
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break;
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case 2: |
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ret = s->iir; |
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/* reset THR pending bit */
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if ((ret & 0x7) == UART_IIR_THRI) |
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s->thr_ipending = 0;
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serial_update_irq(s); |
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break;
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case 3: |
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ret = s->lcr; |
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break;
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case 4: |
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ret = s->mcr; |
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break;
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case 5: |
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ret = s->lsr; |
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break;
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case 6: |
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback, the modem output pins are connected to the
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inputs */
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ret = (s->mcr & 0x0c) << 4; |
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ret |= (s->mcr & 0x02) << 3; |
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ret |= (s->mcr & 0x01) << 5; |
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} else {
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ret = s->msr; |
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} |
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break;
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case 7: |
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ret = s->scr; |
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break;
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} |
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#ifdef DEBUG_SERIAL
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printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
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#endif
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return ret;
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} |
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static int serial_can_receive(SerialState *s) |
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{ |
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return !(s->lsr & UART_LSR_DR);
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} |
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static void serial_receive_byte(SerialState *s, int ch) |
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{ |
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s->rbr = ch; |
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s->lsr |= UART_LSR_DR; |
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serial_update_irq(s); |
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} |
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static void serial_receive_break(SerialState *s) |
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{ |
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s->rbr = 0;
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s->lsr |= UART_LSR_BI | UART_LSR_DR; |
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serial_update_irq(s); |
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} |
339 |
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static int serial_can_receive1(void *opaque) |
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{ |
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SerialState *s = opaque; |
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return serial_can_receive(s);
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} |
345 |
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static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
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{ |
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SerialState *s = opaque; |
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serial_receive_byte(s, buf[0]);
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} |
351 |
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static void serial_event(void *opaque, int event) |
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{ |
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SerialState *s = opaque; |
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if (event == CHR_EVENT_BREAK)
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serial_receive_break(s); |
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} |
358 |
|
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static void serial_save(QEMUFile *f, void *opaque) |
360 |
{ |
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SerialState *s = opaque; |
362 |
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qemu_put_be16s(f,&s->divider); |
364 |
qemu_put_8s(f,&s->rbr); |
365 |
qemu_put_8s(f,&s->ier); |
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qemu_put_8s(f,&s->iir); |
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qemu_put_8s(f,&s->lcr); |
368 |
qemu_put_8s(f,&s->mcr); |
369 |
qemu_put_8s(f,&s->lsr); |
370 |
qemu_put_8s(f,&s->msr); |
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qemu_put_8s(f,&s->scr); |
372 |
} |
373 |
|
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static int serial_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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SerialState *s = opaque; |
377 |
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if(version_id > 2) |
379 |
return -EINVAL;
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|
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if (version_id >= 2) |
382 |
qemu_get_be16s(f, &s->divider); |
383 |
else
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s->divider = qemu_get_byte(f); |
385 |
qemu_get_8s(f,&s->rbr); |
386 |
qemu_get_8s(f,&s->ier); |
387 |
qemu_get_8s(f,&s->iir); |
388 |
qemu_get_8s(f,&s->lcr); |
389 |
qemu_get_8s(f,&s->mcr); |
390 |
qemu_get_8s(f,&s->lsr); |
391 |
qemu_get_8s(f,&s->msr); |
392 |
qemu_get_8s(f,&s->scr); |
393 |
|
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return 0; |
395 |
} |
396 |
|
397 |
static void serial_reset(void *opaque) |
398 |
{ |
399 |
SerialState *s = opaque; |
400 |
|
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s->divider = 0;
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402 |
s->rbr = 0;
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403 |
s->ier = 0;
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404 |
s->iir = UART_IIR_NO_INT; |
405 |
s->lcr = 0;
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406 |
s->mcr = 0;
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407 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
408 |
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
409 |
s->scr = 0;
|
410 |
|
411 |
s->thr_ipending = 0;
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412 |
s->last_break_enable = 0;
|
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qemu_irq_lower(s->irq); |
414 |
} |
415 |
|
416 |
/* If fd is zero, it means that the serial device uses the console */
|
417 |
SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
418 |
CharDriverState *chr) |
419 |
{ |
420 |
SerialState *s; |
421 |
|
422 |
s = qemu_mallocz(sizeof(SerialState));
|
423 |
if (!s)
|
424 |
return NULL; |
425 |
s->irq = irq; |
426 |
s->baudbase = baudbase; |
427 |
|
428 |
s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s); |
429 |
if (!s->tx_timer)
|
430 |
return NULL; |
431 |
|
432 |
qemu_register_reset(serial_reset, s); |
433 |
serial_reset(s); |
434 |
|
435 |
register_savevm("serial", base, 2, serial_save, serial_load, s); |
436 |
|
437 |
register_ioport_write(base, 8, 1, serial_ioport_write, s); |
438 |
register_ioport_read(base, 8, 1, serial_ioport_read, s); |
439 |
s->chr = chr; |
440 |
qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
441 |
serial_event, s); |
442 |
return s;
|
443 |
} |
444 |
|
445 |
/* Memory mapped interface */
|
446 |
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
|
447 |
{ |
448 |
SerialState *s = opaque; |
449 |
|
450 |
return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; |
451 |
} |
452 |
|
453 |
void serial_mm_writeb (void *opaque, |
454 |
target_phys_addr_t addr, uint32_t value) |
455 |
{ |
456 |
SerialState *s = opaque; |
457 |
|
458 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
|
459 |
} |
460 |
|
461 |
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
|
462 |
{ |
463 |
SerialState *s = opaque; |
464 |
uint32_t val; |
465 |
|
466 |
val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
|
467 |
#ifdef TARGET_WORDS_BIGENDIAN
|
468 |
val = bswap16(val); |
469 |
#endif
|
470 |
return val;
|
471 |
} |
472 |
|
473 |
void serial_mm_writew (void *opaque, |
474 |
target_phys_addr_t addr, uint32_t value) |
475 |
{ |
476 |
SerialState *s = opaque; |
477 |
#ifdef TARGET_WORDS_BIGENDIAN
|
478 |
value = bswap16(value); |
479 |
#endif
|
480 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
|
481 |
} |
482 |
|
483 |
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
|
484 |
{ |
485 |
SerialState *s = opaque; |
486 |
uint32_t val; |
487 |
|
488 |
val = serial_ioport_read(s, (addr - s->base) >> s->it_shift); |
489 |
#ifdef TARGET_WORDS_BIGENDIAN
|
490 |
val = bswap32(val); |
491 |
#endif
|
492 |
return val;
|
493 |
} |
494 |
|
495 |
void serial_mm_writel (void *opaque, |
496 |
target_phys_addr_t addr, uint32_t value) |
497 |
{ |
498 |
SerialState *s = opaque; |
499 |
#ifdef TARGET_WORDS_BIGENDIAN
|
500 |
value = bswap32(value); |
501 |
#endif
|
502 |
serial_ioport_write(s, (addr - s->base) >> s->it_shift, value); |
503 |
} |
504 |
|
505 |
static CPUReadMemoryFunc *serial_mm_read[] = {
|
506 |
&serial_mm_readb, |
507 |
&serial_mm_readw, |
508 |
&serial_mm_readl, |
509 |
}; |
510 |
|
511 |
static CPUWriteMemoryFunc *serial_mm_write[] = {
|
512 |
&serial_mm_writeb, |
513 |
&serial_mm_writew, |
514 |
&serial_mm_writel, |
515 |
}; |
516 |
|
517 |
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
518 |
qemu_irq irq, int baudbase,
|
519 |
CharDriverState *chr, int ioregister)
|
520 |
{ |
521 |
SerialState *s; |
522 |
int s_io_memory;
|
523 |
|
524 |
s = qemu_mallocz(sizeof(SerialState));
|
525 |
if (!s)
|
526 |
return NULL; |
527 |
s->irq = irq; |
528 |
s->base = base; |
529 |
s->it_shift = it_shift; |
530 |
s->baudbase= baudbase; |
531 |
|
532 |
s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s); |
533 |
if (!s->tx_timer)
|
534 |
return NULL; |
535 |
|
536 |
qemu_register_reset(serial_reset, s); |
537 |
serial_reset(s); |
538 |
|
539 |
register_savevm("serial", base, 2, serial_save, serial_load, s); |
540 |
|
541 |
if (ioregister) {
|
542 |
s_io_memory = cpu_register_io_memory(0, serial_mm_read,
|
543 |
serial_mm_write, s); |
544 |
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
|
545 |
} |
546 |
s->chr = chr; |
547 |
qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
548 |
serial_event, s); |
549 |
return s;
|
550 |
} |