Revision 2065061e target-sparc/op_helper.c

b/target-sparc/op_helper.c
1 1
#include "exec.h"
2 2
#include "host-utils.h"
3 3
#include "helper.h"
4
#if !defined(CONFIG_USER_ONLY)
5
#include "softmmu_exec.h"
6
#endif /* !defined(CONFIG_USER_ONLY) */
7 4

  
8 5
//#define DEBUG_MMU
9 6
//#define DEBUG_MXCC
......
2142 2139
    switch (asi) {
2143 2140
    case 0x82: // Primary no-fault
2144 2141
    case 0x8a: // Primary no-fault LE
2145
        if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
2142
    case 0x83: // Secondary no-fault
2143
    case 0x8b: // Secondary no-fault LE
2144
        {
2145
            /* secondary space access has lowest asi bit equal to 1 */
2146
            int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX
2147
                                             : MMU_KERNEL_SECONDARY_IDX;
2148

  
2149
            if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) {
2146 2150
#ifdef DEBUG_ASI
2147
            dump_asi("read ", last_addr, asi, size, ret);
2151
                dump_asi("read ", last_addr, asi, size, ret);
2148 2152
#endif
2149
            return 0;
2153
                return 0;
2154
            }
2150 2155
        }
2151 2156
        // Fall through
2152 2157
    case 0x10: // As if user primary
2158
    case 0x11: // As if user secondary
2153 2159
    case 0x18: // As if user primary LE
2160
    case 0x19: // As if user secondary LE
2154 2161
    case 0x80: // Primary
2162
    case 0x81: // Secondary
2155 2163
    case 0x88: // Primary LE
2164
    case 0x89: // Secondary LE
2156 2165
    case 0xe2: // UA2007 Primary block init
2157 2166
    case 0xe3: // UA2007 Secondary block init
2158 2167
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
......
2174 2183
                    break;
2175 2184
                }
2176 2185
            } else {
2186
                /* secondary space access has lowest asi bit equal to 1 */
2187
                if (asi & 1) {
2188
                    switch(size) {
2189
                    case 1:
2190
                        ret = ldub_kernel_secondary(addr);
2191
                        break;
2192
                    case 2:
2193
                        ret = lduw_kernel_secondary(addr);
2194
                        break;
2195
                    case 4:
2196
                        ret = ldl_kernel_secondary(addr);
2197
                        break;
2198
                    default:
2199
                    case 8:
2200
                        ret = ldq_kernel_secondary(addr);
2201
                        break;
2202
                    }
2203
                } else {
2204
                    switch(size) {
2205
                    case 1:
2206
                        ret = ldub_kernel(addr);
2207
                        break;
2208
                    case 2:
2209
                        ret = lduw_kernel(addr);
2210
                        break;
2211
                    case 4:
2212
                        ret = ldl_kernel(addr);
2213
                        break;
2214
                    default:
2215
                    case 8:
2216
                        ret = ldq_kernel(addr);
2217
                        break;
2218
                    }
2219
                }
2220
            }
2221
        } else {
2222
            /* secondary space access has lowest asi bit equal to 1 */
2223
            if (asi & 1) {
2177 2224
                switch(size) {
2178 2225
                case 1:
2179
                    ret = ldub_kernel(addr);
2226
                    ret = ldub_user_secondary(addr);
2180 2227
                    break;
2181 2228
                case 2:
2182
                    ret = lduw_kernel(addr);
2229
                    ret = lduw_user_secondary(addr);
2183 2230
                    break;
2184 2231
                case 4:
2185
                    ret = ldl_kernel(addr);
2232
                    ret = ldl_user_secondary(addr);
2186 2233
                    break;
2187 2234
                default:
2188 2235
                case 8:
2189
                    ret = ldq_kernel(addr);
2236
                    ret = ldq_user_secondary(addr);
2237
                    break;
2238
                }
2239
            } else {
2240
                switch(size) {
2241
                case 1:
2242
                    ret = ldub_user(addr);
2243
                    break;
2244
                case 2:
2245
                    ret = lduw_user(addr);
2246
                    break;
2247
                case 4:
2248
                    ret = ldl_user(addr);
2249
                    break;
2250
                default:
2251
                case 8:
2252
                    ret = ldq_user(addr);
2190 2253
                    break;
2191 2254
                }
2192
            }
2193
        } else {
2194
            switch(size) {
2195
            case 1:
2196
                ret = ldub_user(addr);
2197
                break;
2198
            case 2:
2199
                ret = lduw_user(addr);
2200
                break;
2201
            case 4:
2202
                ret = ldl_user(addr);
2203
                break;
2204
            default:
2205
            case 8:
2206
                ret = ldq_user(addr);
2207
                break;
2208 2255
            }
2209 2256
        }
2210 2257
        break;
......
2235 2282
        //  Only ldda allowed
2236 2283
        raise_exception(TT_ILL_INSN);
2237 2284
        return 0;
2238
    case 0x83: // Secondary no-fault
2239
    case 0x8b: // Secondary no-fault LE
2240
        if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
2241
#ifdef DEBUG_ASI
2242
            dump_asi("read ", last_addr, asi, size, ret);
2243
#endif
2244
            return 0;
2245
        }
2246
        // Fall through
2247 2285
    case 0x04: // Nucleus
2248 2286
    case 0x0c: // Nucleus Little Endian (LE)
2249
    case 0x11: // As if user secondary
2250
    case 0x19: // As if user secondary LE
2287
    {
2288
        switch(size) {
2289
        case 1:
2290
            ret = ldub_nucleus(addr);
2291
            break;
2292
        case 2:
2293
            ret = lduw_nucleus(addr);
2294
            break;
2295
        case 4:
2296
            ret = ldl_nucleus(addr);
2297
            break;
2298
        default:
2299
        case 8:
2300
            ret = ldq_nucleus(addr);
2301
            break;
2302
        }
2303
        break;
2304
    }
2251 2305
    case 0x4a: // UPA config
2252
    case 0x81: // Secondary
2253
    case 0x89: // Secondary LE
2254 2306
        // XXX
2255 2307
        break;
2256 2308
    case 0x45: // LSU
......
2464 2516

  
2465 2517
    switch(asi) {
2466 2518
    case 0x10: // As if user primary
2519
    case 0x11: // As if user secondary
2467 2520
    case 0x18: // As if user primary LE
2521
    case 0x19: // As if user secondary LE
2468 2522
    case 0x80: // Primary
2523
    case 0x81: // Secondary
2469 2524
    case 0x88: // Primary LE
2525
    case 0x89: // Secondary LE
2470 2526
    case 0xe2: // UA2007 Primary block init
2471 2527
    case 0xe3: // UA2007 Secondary block init
2472 2528
        if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
......
2488 2544
                    break;
2489 2545
                }
2490 2546
            } else {
2547
                /* secondary space access has lowest asi bit equal to 1 */
2548
                if (asi & 1) {
2549
                    switch(size) {
2550
                    case 1:
2551
                        stb_kernel_secondary(addr, val);
2552
                        break;
2553
                    case 2:
2554
                        stw_kernel_secondary(addr, val);
2555
                        break;
2556
                    case 4:
2557
                        stl_kernel_secondary(addr, val);
2558
                        break;
2559
                    case 8:
2560
                    default:
2561
                        stq_kernel_secondary(addr, val);
2562
                        break;
2563
                    }
2564
                } else {
2565
                    switch(size) {
2566
                    case 1:
2567
                        stb_kernel(addr, val);
2568
                        break;
2569
                    case 2:
2570
                        stw_kernel(addr, val);
2571
                        break;
2572
                    case 4:
2573
                        stl_kernel(addr, val);
2574
                        break;
2575
                    case 8:
2576
                    default:
2577
                        stq_kernel(addr, val);
2578
                        break;
2579
                    }
2580
                }
2581
            }
2582
        } else {
2583
            /* secondary space access has lowest asi bit equal to 1 */
2584
            if (asi & 1) {
2491 2585
                switch(size) {
2492 2586
                case 1:
2493
                    stb_kernel(addr, val);
2587
                    stb_user_secondary(addr, val);
2494 2588
                    break;
2495 2589
                case 2:
2496
                    stw_kernel(addr, val);
2590
                    stw_user_secondary(addr, val);
2497 2591
                    break;
2498 2592
                case 4:
2499
                    stl_kernel(addr, val);
2593
                    stl_user_secondary(addr, val);
2500 2594
                    break;
2501 2595
                case 8:
2502 2596
                default:
2503
                    stq_kernel(addr, val);
2597
                    stq_user_secondary(addr, val);
2598
                    break;
2599
                }
2600
            } else {
2601
                switch(size) {
2602
                case 1:
2603
                    stb_user(addr, val);
2604
                    break;
2605
                case 2:
2606
                    stw_user(addr, val);
2607
                    break;
2608
                case 4:
2609
                    stl_user(addr, val);
2610
                    break;
2611
                case 8:
2612
                default:
2613
                    stq_user(addr, val);
2504 2614
                    break;
2505 2615
                }
2506
            }
2507
        } else {
2508
            switch(size) {
2509
            case 1:
2510
                stb_user(addr, val);
2511
                break;
2512
            case 2:
2513
                stw_user(addr, val);
2514
                break;
2515
            case 4:
2516
                stl_user(addr, val);
2517
                break;
2518
            case 8:
2519
            default:
2520
                stq_user(addr, val);
2521
                break;
2522 2616
            }
2523 2617
        }
2524 2618
        break;
......
2551 2645
        return;
2552 2646
    case 0x04: // Nucleus
2553 2647
    case 0x0c: // Nucleus Little Endian (LE)
2554
    case 0x11: // As if user secondary
2555
    case 0x19: // As if user secondary LE
2648
    {
2649
        switch(size) {
2650
        case 1:
2651
            stb_nucleus(addr, val);
2652
            break;
2653
        case 2:
2654
            stw_nucleus(addr, val);
2655
            break;
2656
        case 4:
2657
            stl_nucleus(addr, val);
2658
            break;
2659
        default:
2660
        case 8:
2661
            stq_nucleus(addr, val);
2662
            break;
2663
        }
2664
        break;
2665
    }
2666

  
2556 2667
    case 0x4a: // UPA config
2557
    case 0x81: // Secondary
2558
    case 0x89: // Secondary LE
2559 2668
        // XXX
2560 2669
        return;
2561 2670
    case 0x45: // LSU

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