Revision 210914e2

b/hw/dma/xilinx_axidma.c
276 276
        stream_desc_load(s, s->regs[R_CURDESC]);
277 277

  
278 278
        if (s->desc.status & SDESC_STATUS_COMPLETE) {
279
            s->regs[R_DMASR] |= DMASR_IDLE;
279
            s->regs[R_DMASR] |= DMASR_HALTED;
280 280
            break;
281 281
        }
282 282

  
......
331 331
        stream_desc_load(s, s->regs[R_CURDESC]);
332 332

  
333 333
        if (s->desc.status & SDESC_STATUS_COMPLETE) {
334
            s->regs[R_DMASR] |= DMASR_IDLE;
334
            s->regs[R_DMASR] |= DMASR_HALTED;
335 335
            break;
336 336
        }
337 337

  

Also available in: Unified diff