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1 | 450d4ff5 | ths | /* cris.h -- Header file for CRIS opcode and register tables.
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2 | 450d4ff5 | ths | Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
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3 | 450d4ff5 | ths | Contributed by Axis Communications AB, Lund, Sweden.
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4 | 450d4ff5 | ths | Originally written for GAS 1.38.1 by Mikael Asker.
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5 | 450d4ff5 | ths | Updated, BFDized and GNUified by Hans-Peter Nilsson.
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6 | 450d4ff5 | ths | |
7 | 450d4ff5 | ths | This file is part of GAS, GDB and the GNU binutils.
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8 | 450d4ff5 | ths | |
9 | 450d4ff5 | ths | GAS, GDB, and GNU binutils is free software; you can redistribute it
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10 | 450d4ff5 | ths | and/or modify it under the terms of the GNU General Public License as
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11 | 450d4ff5 | ths | published by the Free Software Foundation; either version 2, or (at your
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12 | 450d4ff5 | ths | option) any later version.
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13 | 450d4ff5 | ths | |
14 | 450d4ff5 | ths | GAS, GDB, and GNU binutils are distributed in the hope that they will be
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15 | 450d4ff5 | ths | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 450d4ff5 | ths | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 | 450d4ff5 | ths | GNU General Public License for more details.
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18 | 450d4ff5 | ths | |
19 | 450d4ff5 | ths | You should have received a copy of the GNU General Public License
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20 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
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21 | 450d4ff5 | ths | |
22 | 450d4ff5 | ths | #ifndef __CRIS_H_INCLUDED_
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23 | 450d4ff5 | ths | #define __CRIS_H_INCLUDED_
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24 | 450d4ff5 | ths | |
25 | 450d4ff5 | ths | #if !defined(__STDC__) && !defined(const) |
26 | 450d4ff5 | ths | #define const |
27 | 450d4ff5 | ths | #endif
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28 | 450d4ff5 | ths | |
29 | 450d4ff5 | ths | |
30 | 450d4ff5 | ths | /* Registers. */
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31 | 450d4ff5 | ths | #define MAX_REG (15) |
32 | 450d4ff5 | ths | #define REG_SP (14) |
33 | 450d4ff5 | ths | #define REG_PC (15) |
34 | 450d4ff5 | ths | |
35 | 450d4ff5 | ths | /* CPU version control of disassembly and assembly of instructions.
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36 | 450d4ff5 | ths | May affect how the instruction is assembled, at least the size of
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37 | 450d4ff5 | ths | immediate operands. */
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38 | 450d4ff5 | ths | enum cris_insn_version_usage
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39 | 450d4ff5 | ths | { |
40 | 450d4ff5 | ths | /* Any version. */
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41 | 450d4ff5 | ths | cris_ver_version_all=0,
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42 | 450d4ff5 | ths | |
43 | 450d4ff5 | ths | /* Indeterminate (intended for disassembly only, or obsolete). */
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44 | 450d4ff5 | ths | cris_ver_warning, |
45 | 450d4ff5 | ths | |
46 | 450d4ff5 | ths | /* Only for v0..3 (Etrax 1..4). */
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47 | 450d4ff5 | ths | cris_ver_v0_3, |
48 | 450d4ff5 | ths | |
49 | 450d4ff5 | ths | /* Only for v3 or higher (ETRAX 4 and beyond). */
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50 | 450d4ff5 | ths | cris_ver_v3p, |
51 | 450d4ff5 | ths | |
52 | 450d4ff5 | ths | /* Only for v8 (Etrax 100). */
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53 | 450d4ff5 | ths | cris_ver_v8, |
54 | 450d4ff5 | ths | |
55 | 450d4ff5 | ths | /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */
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56 | 450d4ff5 | ths | cris_ver_v8p, |
57 | 450d4ff5 | ths | |
58 | 450d4ff5 | ths | /* Only for v0..10. FIXME: Not sure what to do with this. */
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59 | 450d4ff5 | ths | cris_ver_sim_v0_10, |
60 | 450d4ff5 | ths | |
61 | 450d4ff5 | ths | /* Only for v0..10. */
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62 | 450d4ff5 | ths | cris_ver_v0_10, |
63 | 450d4ff5 | ths | |
64 | 450d4ff5 | ths | /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */
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65 | 450d4ff5 | ths | cris_ver_v3_10, |
66 | 450d4ff5 | ths | |
67 | 450d4ff5 | ths | /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */
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68 | 450d4ff5 | ths | cris_ver_v8_10, |
69 | 450d4ff5 | ths | |
70 | 450d4ff5 | ths | /* Only for v10 (ETRAX 100 LX) and same series. */
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71 | 450d4ff5 | ths | cris_ver_v10, |
72 | 450d4ff5 | ths | |
73 | 450d4ff5 | ths | /* Only for v10 (ETRAX 100 LX) and same series. */
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74 | 450d4ff5 | ths | cris_ver_v10p, |
75 | 450d4ff5 | ths | |
76 | 450d4ff5 | ths | /* Only for v32 or higher (codename GUINNESS).
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77 | 450d4ff5 | ths | Of course some or all these of may change to cris_ver_v32p if/when
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78 | 450d4ff5 | ths | there's a new revision. */
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79 | 450d4ff5 | ths | cris_ver_v32p |
80 | 450d4ff5 | ths | }; |
81 | 450d4ff5 | ths | |
82 | 450d4ff5 | ths | |
83 | 450d4ff5 | ths | /* Special registers. */
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84 | 450d4ff5 | ths | struct cris_spec_reg
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85 | 450d4ff5 | ths | { |
86 | 450d4ff5 | ths | const char *const name; |
87 | 450d4ff5 | ths | unsigned int number; |
88 | 450d4ff5 | ths | |
89 | 450d4ff5 | ths | /* The size of the register. */
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90 | 450d4ff5 | ths | unsigned int reg_size; |
91 | 450d4ff5 | ths | |
92 | 450d4ff5 | ths | /* What CPU version the special register of that name is implemented
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93 | 450d4ff5 | ths | in. If cris_ver_warning, emit an unimplemented-warning. */
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94 | 450d4ff5 | ths | enum cris_insn_version_usage applicable_version;
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95 | 450d4ff5 | ths | |
96 | 450d4ff5 | ths | /* There might be a specific warning for using a special register
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97 | 450d4ff5 | ths | here. */
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98 | 450d4ff5 | ths | const char *const warning; |
99 | 450d4ff5 | ths | }; |
100 | 450d4ff5 | ths | extern const struct cris_spec_reg cris_spec_regs[]; |
101 | 450d4ff5 | ths | |
102 | 450d4ff5 | ths | |
103 | 450d4ff5 | ths | /* Support registers (kind of special too, but not named as such). */
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104 | 450d4ff5 | ths | struct cris_support_reg
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105 | 450d4ff5 | ths | { |
106 | 450d4ff5 | ths | const char *const name; |
107 | 450d4ff5 | ths | unsigned int number; |
108 | 450d4ff5 | ths | }; |
109 | 450d4ff5 | ths | extern const struct cris_support_reg cris_support_regs[]; |
110 | 450d4ff5 | ths | |
111 | 450d4ff5 | ths | struct cris_cond15
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112 | 450d4ff5 | ths | { |
113 | 450d4ff5 | ths | /* The name of the condition. */
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114 | 450d4ff5 | ths | const char *const name; |
115 | 450d4ff5 | ths | |
116 | 450d4ff5 | ths | /* What CPU version this condition name applies to. */
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117 | 450d4ff5 | ths | enum cris_insn_version_usage applicable_version;
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118 | 450d4ff5 | ths | }; |
119 | 450d4ff5 | ths | extern const struct cris_cond15 cris_conds15[]; |
120 | 450d4ff5 | ths | |
121 | 450d4ff5 | ths | /* Opcode-dependent constants. */
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122 | 450d4ff5 | ths | #define AUTOINCR_BIT (0x04) |
123 | 450d4ff5 | ths | |
124 | 450d4ff5 | ths | /* Prefixes. */
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125 | 450d4ff5 | ths | #define BDAP_QUICK_OPCODE (0x0100) |
126 | 450d4ff5 | ths | #define BDAP_QUICK_Z_BITS (0x0e00) |
127 | 450d4ff5 | ths | |
128 | 450d4ff5 | ths | #define BIAP_OPCODE (0x0540) |
129 | 450d4ff5 | ths | #define BIAP_Z_BITS (0x0a80) |
130 | 450d4ff5 | ths | |
131 | 450d4ff5 | ths | #define DIP_OPCODE (0x0970) |
132 | 450d4ff5 | ths | #define DIP_Z_BITS (0xf280) |
133 | 450d4ff5 | ths | |
134 | 450d4ff5 | ths | #define BDAP_INDIR_LOW (0x40) |
135 | 450d4ff5 | ths | #define BDAP_INDIR_LOW_Z (0x80) |
136 | 450d4ff5 | ths | #define BDAP_INDIR_HIGH (0x09) |
137 | 450d4ff5 | ths | #define BDAP_INDIR_HIGH_Z (0x02) |
138 | 450d4ff5 | ths | |
139 | 450d4ff5 | ths | #define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) |
140 | 450d4ff5 | ths | #define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) |
141 | 450d4ff5 | ths | #define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC)
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142 | 450d4ff5 | ths | #define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT)
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143 | 450d4ff5 | ths | |
144 | 450d4ff5 | ths | /* No prefix must have this code for its "match" bits in the
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145 | 450d4ff5 | ths | opcode-table. "BCC .+2" will do nicely. */
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146 | 450d4ff5 | ths | #define NO_CRIS_PREFIX 0 |
147 | 450d4ff5 | ths | |
148 | 450d4ff5 | ths | /* Definitions for condition codes. */
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149 | 450d4ff5 | ths | #define CC_CC 0x0 |
150 | 450d4ff5 | ths | #define CC_HS 0x0 |
151 | 450d4ff5 | ths | #define CC_CS 0x1 |
152 | 450d4ff5 | ths | #define CC_LO 0x1 |
153 | 450d4ff5 | ths | #define CC_NE 0x2 |
154 | 450d4ff5 | ths | #define CC_EQ 0x3 |
155 | 450d4ff5 | ths | #define CC_VC 0x4 |
156 | 450d4ff5 | ths | #define CC_VS 0x5 |
157 | 450d4ff5 | ths | #define CC_PL 0x6 |
158 | 450d4ff5 | ths | #define CC_MI 0x7 |
159 | 450d4ff5 | ths | #define CC_LS 0x8 |
160 | 450d4ff5 | ths | #define CC_HI 0x9 |
161 | 450d4ff5 | ths | #define CC_GE 0xA |
162 | 450d4ff5 | ths | #define CC_LT 0xB |
163 | 450d4ff5 | ths | #define CC_GT 0xC |
164 | 450d4ff5 | ths | #define CC_LE 0xD |
165 | 450d4ff5 | ths | #define CC_A 0xE |
166 | 450d4ff5 | ths | #define CC_EXT 0xF |
167 | 450d4ff5 | ths | |
168 | 450d4ff5 | ths | /* A table of strings "cc", "cs"... indexed with condition code
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169 | 450d4ff5 | ths | values as above. */
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170 | 450d4ff5 | ths | extern const char *const cris_cc_strings[]; |
171 | 450d4ff5 | ths | |
172 | 450d4ff5 | ths | /* Bcc quick. */
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173 | 450d4ff5 | ths | #define BRANCH_QUICK_LOW (0) |
174 | 450d4ff5 | ths | #define BRANCH_QUICK_HIGH (0) |
175 | 450d4ff5 | ths | #define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) |
176 | 450d4ff5 | ths | #define BRANCH_QUICK_Z_BITS (0x0F00) |
177 | 450d4ff5 | ths | |
178 | 450d4ff5 | ths | /* BA quick. */
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179 | 450d4ff5 | ths | #define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) |
180 | 450d4ff5 | ths | #define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) |
181 | 450d4ff5 | ths | |
182 | 450d4ff5 | ths | /* Bcc [PC+]. */
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183 | 450d4ff5 | ths | #define BRANCH_PC_LOW (0xFF) |
184 | 450d4ff5 | ths | #define BRANCH_INCR_HIGH (0x0D) |
185 | 450d4ff5 | ths | #define BA_PC_INCR_OPCODE \
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186 | 450d4ff5 | ths | ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) |
187 | 450d4ff5 | ths | |
188 | 450d4ff5 | ths | /* Jump. */
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189 | 450d4ff5 | ths | /* Note that old versions generated special register 8 (in high bits)
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190 | 450d4ff5 | ths | and not-that-old versions recognized it as a jump-instruction.
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191 | 450d4ff5 | ths | That opcode now belongs to JUMPU. */
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192 | 450d4ff5 | ths | #define JUMP_INDIR_OPCODE (0x0930) |
193 | 450d4ff5 | ths | #define JUMP_INDIR_Z_BITS (0xf2c0) |
194 | 450d4ff5 | ths | #define JUMP_PC_INCR_OPCODE \
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195 | 450d4ff5 | ths | (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
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196 | 450d4ff5 | ths | |
197 | 450d4ff5 | ths | #define MOVE_M_TO_PREG_OPCODE 0x0a30 |
198 | 450d4ff5 | ths | #define MOVE_M_TO_PREG_ZBITS 0x01c0 |
199 | 450d4ff5 | ths | |
200 | 450d4ff5 | ths | /* BDAP.D N,PC. */
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201 | 450d4ff5 | ths | #define MOVE_PC_INCR_OPCODE_PREFIX \
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202 | 450d4ff5 | ths | (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4)) |
203 | 450d4ff5 | ths | #define MOVE_PC_INCR_OPCODE_SUFFIX \
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204 | 450d4ff5 | ths | (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
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205 | 450d4ff5 | ths | |
206 | 450d4ff5 | ths | #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF) |
207 | 450d4ff5 | ths | |
208 | 450d4ff5 | ths | /* BA DWORD (V32). */
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209 | 450d4ff5 | ths | #define BA_DWORD_OPCODE (0x0EBF) |
210 | 450d4ff5 | ths | |
211 | 450d4ff5 | ths | /* Nop. */
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212 | 450d4ff5 | ths | #define NOP_OPCODE (0x050F) |
213 | 450d4ff5 | ths | #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE) |
214 | 450d4ff5 | ths | |
215 | 450d4ff5 | ths | #define NOP_OPCODE_V32 (0x05B0) |
216 | 450d4ff5 | ths | #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32) |
217 | 450d4ff5 | ths | |
218 | 450d4ff5 | ths | /* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect
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219 | 450d4ff5 | ths | registers or flags. Unfortunately shuts off interrupts for one cycle
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220 | 450d4ff5 | ths | for < v32, but there doesn't seem to be any alternative without that
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221 | 450d4ff5 | ths | effect. */
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222 | 450d4ff5 | ths | #define NOP_OPCODE_COMMON (0x630) |
223 | 450d4ff5 | ths | #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON) |
224 | 450d4ff5 | ths | |
225 | 450d4ff5 | ths | /* LAPC.D */
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226 | 450d4ff5 | ths | #define LAPC_DWORD_OPCODE (0x0D7F) |
227 | 450d4ff5 | ths | #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE) |
228 | 450d4ff5 | ths | |
229 | 450d4ff5 | ths | /* Structure of an opcode table entry. */
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230 | 450d4ff5 | ths | enum cris_imm_oprnd_size_type
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231 | 450d4ff5 | ths | { |
232 | 450d4ff5 | ths | /* No size is applicable. */
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233 | 450d4ff5 | ths | SIZE_NONE, |
234 | 450d4ff5 | ths | |
235 | 450d4ff5 | ths | /* Always 32 bits. */
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236 | 450d4ff5 | ths | SIZE_FIX_32, |
237 | 450d4ff5 | ths | |
238 | 450d4ff5 | ths | /* Indicated by size of special register. */
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239 | 450d4ff5 | ths | SIZE_SPEC_REG, |
240 | 450d4ff5 | ths | |
241 | 450d4ff5 | ths | /* Indicated by size field, signed. */
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242 | 450d4ff5 | ths | SIZE_FIELD_SIGNED, |
243 | 450d4ff5 | ths | |
244 | 450d4ff5 | ths | /* Indicated by size field, unsigned. */
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245 | 450d4ff5 | ths | SIZE_FIELD_UNSIGNED, |
246 | 450d4ff5 | ths | |
247 | 450d4ff5 | ths | /* Indicated by size field, no sign implied. */
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248 | 450d4ff5 | ths | SIZE_FIELD |
249 | 450d4ff5 | ths | }; |
250 | 450d4ff5 | ths | |
251 | 450d4ff5 | ths | /* For GDB. FIXME: Is this the best way to handle opcode
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252 | 450d4ff5 | ths | interpretation? */
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253 | 450d4ff5 | ths | enum cris_op_type
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254 | 450d4ff5 | ths | { |
255 | 450d4ff5 | ths | cris_not_implemented_op = 0,
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256 | 450d4ff5 | ths | cris_abs_op, |
257 | 450d4ff5 | ths | cris_addi_op, |
258 | 450d4ff5 | ths | cris_asr_op, |
259 | 450d4ff5 | ths | cris_asrq_op, |
260 | 450d4ff5 | ths | cris_ax_ei_setf_op, |
261 | 450d4ff5 | ths | cris_bdap_prefix, |
262 | 450d4ff5 | ths | cris_biap_prefix, |
263 | 450d4ff5 | ths | cris_break_op, |
264 | 450d4ff5 | ths | cris_btst_nop_op, |
265 | 450d4ff5 | ths | cris_clearf_di_op, |
266 | 450d4ff5 | ths | cris_dip_prefix, |
267 | 450d4ff5 | ths | cris_dstep_logshift_mstep_neg_not_op, |
268 | 450d4ff5 | ths | cris_eight_bit_offset_branch_op, |
269 | 450d4ff5 | ths | cris_move_mem_to_reg_movem_op, |
270 | 450d4ff5 | ths | cris_move_reg_to_mem_movem_op, |
271 | 450d4ff5 | ths | cris_move_to_preg_op, |
272 | 450d4ff5 | ths | cris_muls_op, |
273 | 450d4ff5 | ths | cris_mulu_op, |
274 | 450d4ff5 | ths | cris_none_reg_mode_add_sub_cmp_and_or_move_op, |
275 | 450d4ff5 | ths | cris_none_reg_mode_clear_test_op, |
276 | 450d4ff5 | ths | cris_none_reg_mode_jump_op, |
277 | 450d4ff5 | ths | cris_none_reg_mode_move_from_preg_op, |
278 | 450d4ff5 | ths | cris_quick_mode_add_sub_op, |
279 | 450d4ff5 | ths | cris_quick_mode_and_cmp_move_or_op, |
280 | 450d4ff5 | ths | cris_quick_mode_bdap_prefix, |
281 | 450d4ff5 | ths | cris_reg_mode_add_sub_cmp_and_or_move_op, |
282 | 450d4ff5 | ths | cris_reg_mode_clear_op, |
283 | 450d4ff5 | ths | cris_reg_mode_jump_op, |
284 | 450d4ff5 | ths | cris_reg_mode_move_from_preg_op, |
285 | 450d4ff5 | ths | cris_reg_mode_test_op, |
286 | 450d4ff5 | ths | cris_scc_op, |
287 | 450d4ff5 | ths | cris_sixteen_bit_offset_branch_op, |
288 | 450d4ff5 | ths | cris_three_operand_add_sub_cmp_and_or_op, |
289 | 450d4ff5 | ths | cris_three_operand_bound_op, |
290 | 450d4ff5 | ths | cris_two_operand_bound_op, |
291 | 450d4ff5 | ths | cris_xor_op |
292 | 450d4ff5 | ths | }; |
293 | 450d4ff5 | ths | |
294 | 450d4ff5 | ths | struct cris_opcode
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295 | 450d4ff5 | ths | { |
296 | 450d4ff5 | ths | /* The name of the insn. */
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297 | 450d4ff5 | ths | const char *name; |
298 | 450d4ff5 | ths | |
299 | 450d4ff5 | ths | /* Bits that must be 1 for a match. */
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300 | 450d4ff5 | ths | unsigned int match; |
301 | 450d4ff5 | ths | |
302 | 450d4ff5 | ths | /* Bits that must be 0 for a match. */
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303 | 450d4ff5 | ths | unsigned int lose; |
304 | 450d4ff5 | ths | |
305 | 450d4ff5 | ths | /* See the table in "opcodes/cris-opc.c". */
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306 | 450d4ff5 | ths | const char *args; |
307 | 450d4ff5 | ths | |
308 | 450d4ff5 | ths | /* Nonzero if this is a delayed branch instruction. */
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309 | 450d4ff5 | ths | char delayed;
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310 | 450d4ff5 | ths | |
311 | 450d4ff5 | ths | /* Size of immediate operands. */
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312 | 450d4ff5 | ths | enum cris_imm_oprnd_size_type imm_oprnd_size;
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313 | 450d4ff5 | ths | |
314 | 450d4ff5 | ths | /* Indicates which version this insn was first implemented in. */
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315 | 450d4ff5 | ths | enum cris_insn_version_usage applicable_version;
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316 | 450d4ff5 | ths | |
317 | 450d4ff5 | ths | /* What kind of operation this is. */
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318 | 450d4ff5 | ths | enum cris_op_type op;
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319 | 450d4ff5 | ths | }; |
320 | 450d4ff5 | ths | extern const struct cris_opcode cris_opcodes[]; |
321 | 450d4ff5 | ths | |
322 | 450d4ff5 | ths | |
323 | 450d4ff5 | ths | /* These macros are for the target-specific flags in disassemble_info
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324 | 450d4ff5 | ths | used at disassembly. */
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325 | 450d4ff5 | ths | |
326 | 450d4ff5 | ths | /* This insn accesses memory. This flag is more trustworthy than
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327 | 450d4ff5 | ths | checking insn_type for "dis_dref" which does not work for
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328 | 450d4ff5 | ths | e.g. "JSR [foo]". */
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329 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEMREF (1 << 0) |
330 | 450d4ff5 | ths | |
331 | 450d4ff5 | ths | /* The "target" field holds a register number. */
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332 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) |
333 | 450d4ff5 | ths | |
334 | 450d4ff5 | ths | /* The "target2" field holds a register number; add it to "target". */
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335 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) |
336 | 450d4ff5 | ths | |
337 | 450d4ff5 | ths | /* Yet another add-on: the register in "target2" must be multiplied
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338 | 450d4ff5 | ths | by 2 before adding to "target". */
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339 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) |
340 | 450d4ff5 | ths | |
341 | 450d4ff5 | ths | /* Yet another add-on: the register in "target2" must be multiplied
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342 | 450d4ff5 | ths | by 4 (mutually exclusive with .._MULT2). */
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343 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) |
344 | 450d4ff5 | ths | |
345 | 450d4ff5 | ths | /* The register in "target2" is an indirect memory reference (of the
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346 | 450d4ff5 | ths | register there), add to "target". Assumed size is dword (mutually
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347 | 450d4ff5 | ths | exclusive with .._MULT[24]). */
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348 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) |
349 | 450d4ff5 | ths | |
350 | 450d4ff5 | ths | /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
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351 | 450d4ff5 | ths | sign-extended before adding to "target". */
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352 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) |
353 | 450d4ff5 | ths | |
354 | 450d4ff5 | ths | /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
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355 | 450d4ff5 | ths | sign-extended before adding to "target". */
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356 | 450d4ff5 | ths | #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) |
357 | 450d4ff5 | ths | |
358 | 450d4ff5 | ths | #endif /* __CRIS_H_INCLUDED_ */ |
359 | 450d4ff5 | ths | |
360 | 450d4ff5 | ths | /*
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361 | 450d4ff5 | ths | * Local variables:
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362 | 450d4ff5 | ths | * eval: (c-set-style "gnu")
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363 | 450d4ff5 | ths | * indent-tabs-mode: t
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364 | 450d4ff5 | ths | * End:
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365 | 450d4ff5 | ths | */ |