root / hw / m48t59.c @ 215cf0be
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1 | a541f297 | bellard | /*
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2 | 819385c5 | bellard | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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3 | a541f297 | bellard | *
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4 | 819385c5 | bellard | * Copyright (c) 2003-2005 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | a541f297 | bellard | #include "vl.h" |
25 | c5df018e | bellard | #include "m48t59.h" |
26 | a541f297 | bellard | |
27 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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28 | a541f297 | bellard | |
29 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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30 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
31 | a541f297 | bellard | #else
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32 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { } while (0) |
33 | a541f297 | bellard | #endif
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34 | a541f297 | bellard | |
35 | 819385c5 | bellard | /*
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36 | 819385c5 | bellard | * The M48T08 and M48T59 chips are very similar. The newer '59 has
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37 | 819385c5 | bellard | * alarm and a watchdog timer and related control registers. In the
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38 | 819385c5 | bellard | * PPC platform there is also a nvram lock function.
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39 | 819385c5 | bellard | */
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40 | c5df018e | bellard | struct m48t59_t {
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41 | 819385c5 | bellard | /* Model parameters */
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42 | 819385c5 | bellard | int type; // 8 = m48t08, 59 = m48t59 |
43 | a541f297 | bellard | /* Hardware parameters */
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44 | a541f297 | bellard | int IRQ;
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45 | e1bb04f7 | bellard | int mem_index;
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46 | e1bb04f7 | bellard | uint32_t mem_base; |
47 | a541f297 | bellard | uint32_t io_base; |
48 | a541f297 | bellard | uint16_t size; |
49 | a541f297 | bellard | /* RTC management */
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50 | a541f297 | bellard | time_t time_offset; |
51 | a541f297 | bellard | time_t stop_time; |
52 | a541f297 | bellard | /* Alarm & watchdog */
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53 | a541f297 | bellard | time_t alarm; |
54 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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55 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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56 | a541f297 | bellard | /* NVRAM storage */
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57 | 13ab5daa | bellard | uint8_t lock; |
58 | a541f297 | bellard | uint16_t addr; |
59 | a541f297 | bellard | uint8_t *buffer; |
60 | c5df018e | bellard | }; |
61 | a541f297 | bellard | |
62 | a541f297 | bellard | /* Fake timer functions */
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63 | a541f297 | bellard | /* Generic helpers for BCD */
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64 | a541f297 | bellard | static inline uint8_t toBCD (uint8_t value) |
65 | a541f297 | bellard | { |
66 | a541f297 | bellard | return (((value / 10) % 10) << 4) | (value % 10); |
67 | a541f297 | bellard | } |
68 | a541f297 | bellard | |
69 | a541f297 | bellard | static inline uint8_t fromBCD (uint8_t BCD) |
70 | a541f297 | bellard | { |
71 | a541f297 | bellard | return ((BCD >> 4) * 10) + (BCD & 0x0F); |
72 | a541f297 | bellard | } |
73 | a541f297 | bellard | |
74 | a541f297 | bellard | /* RTC management helpers */
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75 | a541f297 | bellard | static void get_time (m48t59_t *NVRAM, struct tm *tm) |
76 | a541f297 | bellard | { |
77 | a541f297 | bellard | time_t t; |
78 | a541f297 | bellard | |
79 | a541f297 | bellard | t = time(NULL) + NVRAM->time_offset;
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80 | d157e205 | bellard | #ifdef _WIN32
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81 | d157e205 | bellard | memcpy(tm,localtime(&t),sizeof(*tm));
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82 | d157e205 | bellard | #else
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83 | d157e205 | bellard | localtime_r (&t, tm) ; |
84 | d157e205 | bellard | #endif
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85 | a541f297 | bellard | } |
86 | a541f297 | bellard | |
87 | a541f297 | bellard | static void set_time (m48t59_t *NVRAM, struct tm *tm) |
88 | a541f297 | bellard | { |
89 | a541f297 | bellard | time_t now, new_time; |
90 | a541f297 | bellard | |
91 | a541f297 | bellard | new_time = mktime(tm); |
92 | a541f297 | bellard | now = time(NULL);
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93 | a541f297 | bellard | NVRAM->time_offset = new_time - now; |
94 | a541f297 | bellard | } |
95 | a541f297 | bellard | |
96 | a541f297 | bellard | /* Alarm management */
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97 | a541f297 | bellard | static void alarm_cb (void *opaque) |
98 | a541f297 | bellard | { |
99 | a541f297 | bellard | struct tm tm, tm_now;
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100 | a541f297 | bellard | uint64_t next_time; |
101 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
102 | a541f297 | bellard | |
103 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 1);
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104 | a541f297 | bellard | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
105 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
106 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
107 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
108 | a541f297 | bellard | /* Repeat once a month */
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109 | a541f297 | bellard | get_time(NVRAM, &tm_now); |
110 | a541f297 | bellard | memcpy(&tm, &tm_now, sizeof(struct tm)); |
111 | a541f297 | bellard | tm.tm_mon++; |
112 | a541f297 | bellard | if (tm.tm_mon == 13) { |
113 | a541f297 | bellard | tm.tm_mon = 1;
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114 | a541f297 | bellard | tm.tm_year++; |
115 | a541f297 | bellard | } |
116 | a541f297 | bellard | next_time = mktime(&tm); |
117 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
118 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
119 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
120 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
121 | a541f297 | bellard | /* Repeat once a day */
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122 | a541f297 | bellard | next_time = 24 * 60 * 60 + mktime(&tm_now); |
123 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
124 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
125 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
126 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
127 | a541f297 | bellard | /* Repeat once an hour */
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128 | a541f297 | bellard | next_time = 60 * 60 + mktime(&tm_now); |
129 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
130 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
131 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
132 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
133 | a541f297 | bellard | /* Repeat once a minute */
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134 | a541f297 | bellard | next_time = 60 + mktime(&tm_now);
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135 | a541f297 | bellard | } else {
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136 | a541f297 | bellard | /* Repeat once a second */
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137 | a541f297 | bellard | next_time = 1 + mktime(&tm_now);
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138 | a541f297 | bellard | } |
139 | a541f297 | bellard | qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
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140 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 0);
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141 | a541f297 | bellard | } |
142 | a541f297 | bellard | |
143 | a541f297 | bellard | |
144 | a541f297 | bellard | static void get_alarm (m48t59_t *NVRAM, struct tm *tm) |
145 | a541f297 | bellard | { |
146 | d157e205 | bellard | #ifdef _WIN32
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147 | d157e205 | bellard | memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
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148 | d157e205 | bellard | #else
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149 | d157e205 | bellard | localtime_r (&NVRAM->alarm, tm); |
150 | d157e205 | bellard | #endif
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151 | a541f297 | bellard | } |
152 | a541f297 | bellard | |
153 | a541f297 | bellard | static void set_alarm (m48t59_t *NVRAM, struct tm *tm) |
154 | a541f297 | bellard | { |
155 | a541f297 | bellard | NVRAM->alarm = mktime(tm); |
156 | a541f297 | bellard | if (NVRAM->alrm_timer != NULL) { |
157 | a541f297 | bellard | qemu_del_timer(NVRAM->alrm_timer); |
158 | a541f297 | bellard | NVRAM->alrm_timer = NULL;
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159 | a541f297 | bellard | } |
160 | a541f297 | bellard | if (NVRAM->alarm - time(NULL) > 0) |
161 | a541f297 | bellard | qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
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162 | a541f297 | bellard | } |
163 | a541f297 | bellard | |
164 | a541f297 | bellard | /* Watchdog management */
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165 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
166 | a541f297 | bellard | { |
167 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
168 | a541f297 | bellard | |
169 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
170 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
171 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
172 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
173 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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174 | d7d02e3c | bellard | qemu_system_reset_request(); |
175 | a541f297 | bellard | } else {
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176 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 1);
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177 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 0);
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178 | a541f297 | bellard | } |
179 | a541f297 | bellard | } |
180 | a541f297 | bellard | |
181 | a541f297 | bellard | static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
182 | a541f297 | bellard | { |
183 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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184 | a541f297 | bellard | |
185 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
186 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
187 | a541f297 | bellard | NVRAM->wd_timer = NULL;
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188 | a541f297 | bellard | } |
189 | a541f297 | bellard | NVRAM->buffer[0x1FF0] &= ~0x80; |
190 | a541f297 | bellard | if (value != 0) { |
191 | a541f297 | bellard | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
192 | a541f297 | bellard | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
193 | a541f297 | bellard | ((interval * 1000) >> 4)); |
194 | a541f297 | bellard | } |
195 | a541f297 | bellard | } |
196 | a541f297 | bellard | |
197 | a541f297 | bellard | /* Direct access to NVRAM */
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198 | 819385c5 | bellard | void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val)
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199 | a541f297 | bellard | { |
200 | a541f297 | bellard | struct tm tm;
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201 | a541f297 | bellard | int tmp;
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202 | a541f297 | bellard | |
203 | 819385c5 | bellard | if (addr > 0x1FF8 && addr < 0x2000) |
204 | 819385c5 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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205 | 819385c5 | bellard | if (NVRAM->type == 8 && |
206 | 819385c5 | bellard | (addr >= 0x1ff0 && addr <= 0x1ff7)) |
207 | 819385c5 | bellard | goto do_write;
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208 | 819385c5 | bellard | switch (addr) {
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209 | a541f297 | bellard | case 0x1FF0: |
210 | a541f297 | bellard | /* flags register : read-only */
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211 | a541f297 | bellard | break;
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212 | a541f297 | bellard | case 0x1FF1: |
213 | a541f297 | bellard | /* unused */
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214 | a541f297 | bellard | break;
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215 | a541f297 | bellard | case 0x1FF2: |
216 | a541f297 | bellard | /* alarm seconds */
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217 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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218 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
219 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
220 | 819385c5 | bellard | tm.tm_sec = tmp; |
221 | 819385c5 | bellard | NVRAM->buffer[0x1FF2] = val;
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222 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
223 | 819385c5 | bellard | } |
224 | a541f297 | bellard | break;
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225 | a541f297 | bellard | case 0x1FF3: |
226 | a541f297 | bellard | /* alarm minutes */
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227 | 819385c5 | bellard | tmp = fromBCD(val & 0x7F);
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228 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 59) { |
229 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
230 | 819385c5 | bellard | tm.tm_min = tmp; |
231 | 819385c5 | bellard | NVRAM->buffer[0x1FF3] = val;
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232 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
233 | 819385c5 | bellard | } |
234 | a541f297 | bellard | break;
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235 | a541f297 | bellard | case 0x1FF4: |
236 | a541f297 | bellard | /* alarm hours */
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237 | 819385c5 | bellard | tmp = fromBCD(val & 0x3F);
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238 | 819385c5 | bellard | if (tmp >= 0 && tmp <= 23) { |
239 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
240 | 819385c5 | bellard | tm.tm_hour = tmp; |
241 | 819385c5 | bellard | NVRAM->buffer[0x1FF4] = val;
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242 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
243 | 819385c5 | bellard | } |
244 | a541f297 | bellard | break;
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245 | a541f297 | bellard | case 0x1FF5: |
246 | a541f297 | bellard | /* alarm date */
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247 | 819385c5 | bellard | tmp = fromBCD(val & 0x1F);
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248 | 819385c5 | bellard | if (tmp != 0) { |
249 | 819385c5 | bellard | get_alarm(NVRAM, &tm); |
250 | 819385c5 | bellard | tm.tm_mday = tmp; |
251 | 819385c5 | bellard | NVRAM->buffer[0x1FF5] = val;
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252 | 819385c5 | bellard | set_alarm(NVRAM, &tm); |
253 | 819385c5 | bellard | } |
254 | a541f297 | bellard | break;
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255 | a541f297 | bellard | case 0x1FF6: |
256 | a541f297 | bellard | /* interrupts */
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257 | 819385c5 | bellard | NVRAM->buffer[0x1FF6] = val;
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258 | a541f297 | bellard | break;
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259 | a541f297 | bellard | case 0x1FF7: |
260 | a541f297 | bellard | /* watchdog */
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261 | 819385c5 | bellard | NVRAM->buffer[0x1FF7] = val;
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262 | 819385c5 | bellard | set_up_watchdog(NVRAM, val); |
263 | a541f297 | bellard | break;
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264 | a541f297 | bellard | case 0x1FF8: |
265 | a541f297 | bellard | /* control */
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266 | a541f297 | bellard | NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90; |
267 | a541f297 | bellard | break;
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268 | a541f297 | bellard | case 0x1FF9: |
269 | a541f297 | bellard | /* seconds (BCD) */
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270 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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271 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
272 | a541f297 | bellard | get_time(NVRAM, &tm); |
273 | a541f297 | bellard | tm.tm_sec = tmp; |
274 | a541f297 | bellard | set_time(NVRAM, &tm); |
275 | a541f297 | bellard | } |
276 | a541f297 | bellard | if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) { |
277 | a541f297 | bellard | if (val & 0x80) { |
278 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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279 | a541f297 | bellard | } else {
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280 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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281 | a541f297 | bellard | NVRAM->stop_time = 0;
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282 | a541f297 | bellard | } |
283 | a541f297 | bellard | } |
284 | a541f297 | bellard | NVRAM->buffer[0x1FF9] = val & 0x80; |
285 | a541f297 | bellard | break;
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286 | a541f297 | bellard | case 0x1FFA: |
287 | a541f297 | bellard | /* minutes (BCD) */
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288 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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289 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
290 | a541f297 | bellard | get_time(NVRAM, &tm); |
291 | a541f297 | bellard | tm.tm_min = tmp; |
292 | a541f297 | bellard | set_time(NVRAM, &tm); |
293 | a541f297 | bellard | } |
294 | a541f297 | bellard | break;
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295 | a541f297 | bellard | case 0x1FFB: |
296 | a541f297 | bellard | /* hours (BCD) */
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297 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
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298 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
299 | a541f297 | bellard | get_time(NVRAM, &tm); |
300 | a541f297 | bellard | tm.tm_hour = tmp; |
301 | a541f297 | bellard | set_time(NVRAM, &tm); |
302 | a541f297 | bellard | } |
303 | a541f297 | bellard | break;
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304 | a541f297 | bellard | case 0x1FFC: |
305 | a541f297 | bellard | /* day of the week / century */
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306 | a541f297 | bellard | tmp = fromBCD(val & 0x07);
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307 | a541f297 | bellard | get_time(NVRAM, &tm); |
308 | a541f297 | bellard | tm.tm_wday = tmp; |
309 | a541f297 | bellard | set_time(NVRAM, &tm); |
310 | a541f297 | bellard | NVRAM->buffer[0x1FFC] = val & 0x40; |
311 | a541f297 | bellard | break;
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312 | a541f297 | bellard | case 0x1FFD: |
313 | a541f297 | bellard | /* date */
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314 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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315 | a541f297 | bellard | if (tmp != 0) { |
316 | a541f297 | bellard | get_time(NVRAM, &tm); |
317 | a541f297 | bellard | tm.tm_mday = tmp; |
318 | a541f297 | bellard | set_time(NVRAM, &tm); |
319 | a541f297 | bellard | } |
320 | a541f297 | bellard | break;
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321 | a541f297 | bellard | case 0x1FFE: |
322 | a541f297 | bellard | /* month */
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323 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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324 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
325 | a541f297 | bellard | get_time(NVRAM, &tm); |
326 | a541f297 | bellard | tm.tm_mon = tmp - 1;
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327 | a541f297 | bellard | set_time(NVRAM, &tm); |
328 | a541f297 | bellard | } |
329 | a541f297 | bellard | break;
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330 | a541f297 | bellard | case 0x1FFF: |
331 | a541f297 | bellard | /* year */
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332 | a541f297 | bellard | tmp = fromBCD(val); |
333 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
334 | a541f297 | bellard | get_time(NVRAM, &tm); |
335 | a541f297 | bellard | tm.tm_year = fromBCD(val); |
336 | a541f297 | bellard | set_time(NVRAM, &tm); |
337 | a541f297 | bellard | } |
338 | a541f297 | bellard | break;
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339 | a541f297 | bellard | default:
|
340 | 13ab5daa | bellard | /* Check lock registers state */
|
341 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
342 | 13ab5daa | bellard | break;
|
343 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
344 | 13ab5daa | bellard | break;
|
345 | 819385c5 | bellard | do_write:
|
346 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
347 | 819385c5 | bellard | NVRAM->buffer[addr] = val & 0xFF;
|
348 | a541f297 | bellard | } |
349 | a541f297 | bellard | break;
|
350 | a541f297 | bellard | } |
351 | a541f297 | bellard | } |
352 | a541f297 | bellard | |
353 | 819385c5 | bellard | uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr) |
354 | a541f297 | bellard | { |
355 | a541f297 | bellard | struct tm tm;
|
356 | a541f297 | bellard | uint32_t retval = 0xFF;
|
357 | a541f297 | bellard | |
358 | 819385c5 | bellard | if (NVRAM->type == 8 && |
359 | 819385c5 | bellard | (addr >= 0x1ff0 && addr <= 0x1ff7)) |
360 | 819385c5 | bellard | goto do_read;
|
361 | 819385c5 | bellard | switch (addr) {
|
362 | a541f297 | bellard | case 0x1FF0: |
363 | a541f297 | bellard | /* flags register */
|
364 | a541f297 | bellard | goto do_read;
|
365 | a541f297 | bellard | case 0x1FF1: |
366 | a541f297 | bellard | /* unused */
|
367 | a541f297 | bellard | retval = 0;
|
368 | a541f297 | bellard | break;
|
369 | a541f297 | bellard | case 0x1FF2: |
370 | a541f297 | bellard | /* alarm seconds */
|
371 | a541f297 | bellard | goto do_read;
|
372 | a541f297 | bellard | case 0x1FF3: |
373 | a541f297 | bellard | /* alarm minutes */
|
374 | a541f297 | bellard | goto do_read;
|
375 | a541f297 | bellard | case 0x1FF4: |
376 | a541f297 | bellard | /* alarm hours */
|
377 | a541f297 | bellard | goto do_read;
|
378 | a541f297 | bellard | case 0x1FF5: |
379 | a541f297 | bellard | /* alarm date */
|
380 | a541f297 | bellard | goto do_read;
|
381 | a541f297 | bellard | case 0x1FF6: |
382 | a541f297 | bellard | /* interrupts */
|
383 | a541f297 | bellard | goto do_read;
|
384 | a541f297 | bellard | case 0x1FF7: |
385 | a541f297 | bellard | /* A read resets the watchdog */
|
386 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
387 | a541f297 | bellard | goto do_read;
|
388 | a541f297 | bellard | case 0x1FF8: |
389 | a541f297 | bellard | /* control */
|
390 | a541f297 | bellard | goto do_read;
|
391 | a541f297 | bellard | case 0x1FF9: |
392 | a541f297 | bellard | /* seconds (BCD) */
|
393 | a541f297 | bellard | get_time(NVRAM, &tm); |
394 | a541f297 | bellard | retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec); |
395 | a541f297 | bellard | break;
|
396 | a541f297 | bellard | case 0x1FFA: |
397 | a541f297 | bellard | /* minutes (BCD) */
|
398 | a541f297 | bellard | get_time(NVRAM, &tm); |
399 | a541f297 | bellard | retval = toBCD(tm.tm_min); |
400 | a541f297 | bellard | break;
|
401 | a541f297 | bellard | case 0x1FFB: |
402 | a541f297 | bellard | /* hours (BCD) */
|
403 | a541f297 | bellard | get_time(NVRAM, &tm); |
404 | a541f297 | bellard | retval = toBCD(tm.tm_hour); |
405 | a541f297 | bellard | break;
|
406 | a541f297 | bellard | case 0x1FFC: |
407 | a541f297 | bellard | /* day of the week / century */
|
408 | a541f297 | bellard | get_time(NVRAM, &tm); |
409 | a541f297 | bellard | retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
|
410 | a541f297 | bellard | break;
|
411 | a541f297 | bellard | case 0x1FFD: |
412 | a541f297 | bellard | /* date */
|
413 | a541f297 | bellard | get_time(NVRAM, &tm); |
414 | a541f297 | bellard | retval = toBCD(tm.tm_mday); |
415 | a541f297 | bellard | break;
|
416 | a541f297 | bellard | case 0x1FFE: |
417 | a541f297 | bellard | /* month */
|
418 | a541f297 | bellard | get_time(NVRAM, &tm); |
419 | a541f297 | bellard | retval = toBCD(tm.tm_mon + 1);
|
420 | a541f297 | bellard | break;
|
421 | a541f297 | bellard | case 0x1FFF: |
422 | a541f297 | bellard | /* year */
|
423 | a541f297 | bellard | get_time(NVRAM, &tm); |
424 | a541f297 | bellard | retval = toBCD(tm.tm_year); |
425 | a541f297 | bellard | break;
|
426 | a541f297 | bellard | default:
|
427 | 13ab5daa | bellard | /* Check lock registers state */
|
428 | 819385c5 | bellard | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
429 | 13ab5daa | bellard | break;
|
430 | 819385c5 | bellard | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
431 | 13ab5daa | bellard | break;
|
432 | 819385c5 | bellard | do_read:
|
433 | 819385c5 | bellard | if (addr < NVRAM->size) {
|
434 | 819385c5 | bellard | retval = NVRAM->buffer[addr]; |
435 | a541f297 | bellard | } |
436 | a541f297 | bellard | break;
|
437 | a541f297 | bellard | } |
438 | 819385c5 | bellard | if (addr > 0x1FF9 && addr < 0x2000) |
439 | 819385c5 | bellard | NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
440 | a541f297 | bellard | |
441 | a541f297 | bellard | return retval;
|
442 | a541f297 | bellard | } |
443 | a541f297 | bellard | |
444 | c5df018e | bellard | void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
|
445 | a541f297 | bellard | { |
446 | a541f297 | bellard | NVRAM->addr = addr; |
447 | a541f297 | bellard | } |
448 | a541f297 | bellard | |
449 | 13ab5daa | bellard | void m48t59_toggle_lock (m48t59_t *NVRAM, int lock) |
450 | 13ab5daa | bellard | { |
451 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
452 | 13ab5daa | bellard | } |
453 | 13ab5daa | bellard | |
454 | a541f297 | bellard | /* IO access to NVRAM */
|
455 | a541f297 | bellard | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
456 | a541f297 | bellard | { |
457 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
458 | a541f297 | bellard | |
459 | a541f297 | bellard | addr -= NVRAM->io_base; |
460 | 13ab5daa | bellard | NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
|
461 | a541f297 | bellard | switch (addr) {
|
462 | a541f297 | bellard | case 0: |
463 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
464 | a541f297 | bellard | NVRAM->addr |= val; |
465 | a541f297 | bellard | break;
|
466 | a541f297 | bellard | case 1: |
467 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
468 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
469 | a541f297 | bellard | break;
|
470 | a541f297 | bellard | case 3: |
471 | 819385c5 | bellard | m48t59_write(NVRAM, val, NVRAM->addr); |
472 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
473 | a541f297 | bellard | break;
|
474 | a541f297 | bellard | default:
|
475 | a541f297 | bellard | break;
|
476 | a541f297 | bellard | } |
477 | a541f297 | bellard | } |
478 | a541f297 | bellard | |
479 | a541f297 | bellard | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
480 | a541f297 | bellard | { |
481 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
482 | 13ab5daa | bellard | uint32_t retval; |
483 | a541f297 | bellard | |
484 | 13ab5daa | bellard | addr -= NVRAM->io_base; |
485 | 13ab5daa | bellard | switch (addr) {
|
486 | 13ab5daa | bellard | case 3: |
487 | 819385c5 | bellard | retval = m48t59_read(NVRAM, NVRAM->addr); |
488 | 13ab5daa | bellard | break;
|
489 | 13ab5daa | bellard | default:
|
490 | 13ab5daa | bellard | retval = -1;
|
491 | 13ab5daa | bellard | break;
|
492 | 13ab5daa | bellard | } |
493 | 13ab5daa | bellard | NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
494 | a541f297 | bellard | |
495 | 13ab5daa | bellard | return retval;
|
496 | a541f297 | bellard | } |
497 | a541f297 | bellard | |
498 | e1bb04f7 | bellard | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
499 | e1bb04f7 | bellard | { |
500 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
501 | e1bb04f7 | bellard | |
502 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
503 | 819385c5 | bellard | m48t59_write(NVRAM, addr, value & 0xff);
|
504 | e1bb04f7 | bellard | } |
505 | e1bb04f7 | bellard | |
506 | e1bb04f7 | bellard | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
507 | e1bb04f7 | bellard | { |
508 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
509 | e1bb04f7 | bellard | |
510 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
511 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
512 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, value & 0xff); |
513 | e1bb04f7 | bellard | } |
514 | e1bb04f7 | bellard | |
515 | e1bb04f7 | bellard | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
516 | e1bb04f7 | bellard | { |
517 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
518 | e1bb04f7 | bellard | |
519 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
520 | 819385c5 | bellard | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
521 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
522 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
523 | 819385c5 | bellard | m48t59_write(NVRAM, addr + 3, value & 0xff); |
524 | e1bb04f7 | bellard | } |
525 | e1bb04f7 | bellard | |
526 | e1bb04f7 | bellard | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
527 | e1bb04f7 | bellard | { |
528 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
529 | 819385c5 | bellard | uint32_t retval; |
530 | e1bb04f7 | bellard | |
531 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
532 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr); |
533 | e1bb04f7 | bellard | return retval;
|
534 | e1bb04f7 | bellard | } |
535 | e1bb04f7 | bellard | |
536 | e1bb04f7 | bellard | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
537 | e1bb04f7 | bellard | { |
538 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
539 | 819385c5 | bellard | uint32_t retval; |
540 | e1bb04f7 | bellard | |
541 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
542 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 8;
|
543 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1);
|
544 | e1bb04f7 | bellard | return retval;
|
545 | e1bb04f7 | bellard | } |
546 | e1bb04f7 | bellard | |
547 | e1bb04f7 | bellard | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
548 | e1bb04f7 | bellard | { |
549 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
550 | 819385c5 | bellard | uint32_t retval; |
551 | e1bb04f7 | bellard | |
552 | 819385c5 | bellard | addr -= NVRAM->mem_base; |
553 | 819385c5 | bellard | retval = m48t59_read(NVRAM, addr) << 24;
|
554 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
555 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
556 | 819385c5 | bellard | retval |= m48t59_read(NVRAM, addr + 3);
|
557 | e1bb04f7 | bellard | return retval;
|
558 | e1bb04f7 | bellard | } |
559 | e1bb04f7 | bellard | |
560 | e1bb04f7 | bellard | static CPUWriteMemoryFunc *nvram_write[] = {
|
561 | e1bb04f7 | bellard | &nvram_writeb, |
562 | e1bb04f7 | bellard | &nvram_writew, |
563 | e1bb04f7 | bellard | &nvram_writel, |
564 | e1bb04f7 | bellard | }; |
565 | e1bb04f7 | bellard | |
566 | e1bb04f7 | bellard | static CPUReadMemoryFunc *nvram_read[] = {
|
567 | e1bb04f7 | bellard | &nvram_readb, |
568 | e1bb04f7 | bellard | &nvram_readw, |
569 | e1bb04f7 | bellard | &nvram_readl, |
570 | e1bb04f7 | bellard | }; |
571 | 819385c5 | bellard | |
572 | a541f297 | bellard | /* Initialisation routine */
|
573 | 819385c5 | bellard | m48t59_t *m48t59_init (int IRQ, target_ulong mem_base,
|
574 | 819385c5 | bellard | uint32_t io_base, uint16_t size, |
575 | 819385c5 | bellard | int type)
|
576 | a541f297 | bellard | { |
577 | c5df018e | bellard | m48t59_t *s; |
578 | a541f297 | bellard | |
579 | c5df018e | bellard | s = qemu_mallocz(sizeof(m48t59_t));
|
580 | c5df018e | bellard | if (!s)
|
581 | a541f297 | bellard | return NULL; |
582 | c5df018e | bellard | s->buffer = qemu_mallocz(size); |
583 | c5df018e | bellard | if (!s->buffer) {
|
584 | c5df018e | bellard | qemu_free(s); |
585 | c5df018e | bellard | return NULL; |
586 | c5df018e | bellard | } |
587 | c5df018e | bellard | s->IRQ = IRQ; |
588 | c5df018e | bellard | s->size = size; |
589 | e1bb04f7 | bellard | s->mem_base = mem_base; |
590 | c5df018e | bellard | s->io_base = io_base; |
591 | c5df018e | bellard | s->addr = 0;
|
592 | 819385c5 | bellard | s->type = type; |
593 | 819385c5 | bellard | if (io_base != 0) { |
594 | 819385c5 | bellard | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
595 | 819385c5 | bellard | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
596 | 819385c5 | bellard | } |
597 | e1bb04f7 | bellard | if (mem_base != 0) { |
598 | e1bb04f7 | bellard | s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
599 | e1bb04f7 | bellard | cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
|
600 | e1bb04f7 | bellard | } |
601 | 819385c5 | bellard | if (type == 59) { |
602 | 819385c5 | bellard | s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
603 | 819385c5 | bellard | s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
604 | 819385c5 | bellard | } |
605 | 13ab5daa | bellard | s->lock = 0;
|
606 | 13ab5daa | bellard | |
607 | c5df018e | bellard | return s;
|
608 | a541f297 | bellard | } |