Archipelago » qemu

/*

 * QEMU PCI bus manager

 *

 * Copyright (c) 2004 Fabrice Bellard

 * 

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "vl.h"

//#define DEBUG_PCI

#define PCI_VENDOR_ID                0x00        /* 16 bits */

#define PCI_DEVICE_ID                0x02        /* 16 bits */

#define PCI_COMMAND                0x04        /* 16 bits */

#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */

#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */

#define PCI_CLASS_DEVICE        0x0a    /* Device class */

#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */

#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */

#define PCI_MIN_GNT                0x3e        /* 8 bits */

#define PCI_MAX_LAT                0x3f        /* 8 bits */

/* just used for simpler irq handling. */

#define PCI_DEVICES_MAX 64

#define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)

struct PCIBus {

    int bus_num;

    int devfn_min;

    void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);

    uint32_t config_reg; /* XXX: suppress */

    /* low level pic */

    SetIRQFunc *low_set_irq;

    void *irq_opaque;

    PCIDevice *devices[256];

};

target_phys_addr_t pci_mem_base;

static int pci_irq_index;

static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];

static PCIBus *first_bus;

static PCIBus *pci_register_bus(void)

{

    PCIBus *bus;

    bus = qemu_mallocz(sizeof(PCIBus));

    first_bus = bus;

    return bus;

}

void generic_pci_save(QEMUFile* f, void *opaque)

{

    PCIDevice* s=(PCIDevice*)opaque;

    qemu_put_buffer(f, s->config, 256);

}

int generic_pci_load(QEMUFile* f, void *opaque, int version_id)

{

    PCIDevice* s=(PCIDevice*)opaque;

    if (version_id != 1)

        return -EINVAL;

    qemu_get_buffer(f, s->config, 256);

    return 0;

}

/* -1 for devfn means auto assign */

PCIDevice *pci_register_device(PCIBus *bus, const char *name, 

                               int instance_size, int devfn,

                               PCIConfigReadFunc *config_read, 

                               PCIConfigWriteFunc *config_write)

{

    PCIDevice *pci_dev;

    if (pci_irq_index >= PCI_DEVICES_MAX)

        return NULL;

    if (devfn < 0) {

        for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {

            if (!bus->devices[devfn])

                goto found;

        }

        return NULL;

    found: ;

    }

    pci_dev = qemu_mallocz(instance_size);

    if (!pci_dev)

        return NULL;

    pci_dev->bus = bus;

    pci_dev->devfn = devfn;

    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);

    if (!config_read)

        config_read = pci_default_read_config;

    if (!config_write)

        config_write = pci_default_write_config;

    pci_dev->config_read = config_read;

    pci_dev->config_write = config_write;

    pci_dev->irq_index = pci_irq_index++;

    bus->devices[devfn] = pci_dev;

    return pci_dev;

}

void pci_register_io_region(PCIDevice *pci_dev, int region_num, 

                            uint32_t size, int type, 

                            PCIMapIORegionFunc *map_func)

{

    PCIIORegion *r;

    uint32_t addr;

    if ((unsigned int)region_num >= PCI_NUM_REGIONS)

        return;

    r = &pci_dev->io_regions[region_num];

    r->addr = -1;

    r->size = size;

    r->type = type;

    r->map_func = map_func;

    if (region_num == PCI_ROM_SLOT) {

        addr = 0x30;

    } else {

        addr = 0x10 + region_num * 4;

    }

    *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);

}

static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)

{

    PCIBus *s = opaque;

    s->config_reg = val;

}

static uint32_t pci_addr_readl(void* opaque, uint32_t addr)

{

    PCIBus *s = opaque;

    return s->config_reg;

}

static void pci_update_mappings(PCIDevice *d)

{

    PCIIORegion *r;

    int cmd, i;

    uint32_t last_addr, new_addr, config_ofs;

    cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));

    for(i = 0; i < PCI_NUM_REGIONS; i++) {

        r = &d->io_regions[i];

        if (i == PCI_ROM_SLOT) {

            config_ofs = 0x30;

        } else {

            config_ofs = 0x10 + i * 4;

        }

        if (r->size != 0) {

            if (r->type & PCI_ADDRESS_SPACE_IO) {

                if (cmd & PCI_COMMAND_IO) {

                    new_addr = le32_to_cpu(*(uint32_t *)(d->config + 

                                                         config_ofs));

                    new_addr = new_addr & ~(r->size - 1);

                    last_addr = new_addr + r->size - 1;

                    /* NOTE: we have only 64K ioports on PC */

                    if (last_addr <= new_addr || new_addr == 0 ||

                        last_addr >= 0x10000) {

                        new_addr = -1;

                    }

                } else {

                    new_addr = -1;

                }

            } else {

                if (cmd & PCI_COMMAND_MEMORY) {

                    new_addr = le32_to_cpu(*(uint32_t *)(d->config + 

                                                         config_ofs));

                    /* the ROM slot has a specific enable bit */

                    if (i == PCI_ROM_SLOT && !(new_addr & 1))

                        goto no_mem_map;

                    new_addr = new_addr & ~(r->size - 1);

                    last_addr = new_addr + r->size - 1;

                    /* NOTE: we do not support wrapping */

                    /* XXX: as we cannot support really dynamic

                       mappings, we handle specific values as invalid

                       mappings. */

                    if (last_addr <= new_addr || new_addr == 0 ||

                        last_addr == -1) {

                        new_addr = -1;

                    }

                } else {

                no_mem_map:

                    new_addr = -1;

                }

            }

            /* now do the real mapping */

            if (new_addr != r->addr) {

                if (r->addr != -1) {

                    if (r->type & PCI_ADDRESS_SPACE_IO) {

                        int class;

                        /* NOTE: specific hack for IDE in PC case:

                           only one byte must be mapped. */

                        class = d->config[0x0a] | (d->config[0x0b] << 8);

                        if (class == 0x0101 && r->size == 4) {

                            isa_unassign_ioport(r->addr + 2, 1);

                        } else {

                            isa_unassign_ioport(r->addr, r->size);

                        }

                    } else {

                        cpu_register_physical_memory(r->addr + pci_mem_base, 

                                                     r->size, 

                                                     IO_MEM_UNASSIGNED);

                    }

                }

                r->addr = new_addr;

                if (r->addr != -1) {

                    r->map_func(d, i, r->addr, r->size, r->type);

                }

            }

        }

    }

}

uint32_t pci_default_read_config(PCIDevice *d, 

                                 uint32_t address, int len)

{

    uint32_t val;

    switch(len) {

    case 1:

        val = d->config[address];

        break;

    case 2:

        val = le16_to_cpu(*(uint16_t *)(d->config + address));

        break;

    default:

    case 4:

        val = le32_to_cpu(*(uint32_t *)(d->config + address));

        break;

    }

    return val;

}

void pci_default_write_config(PCIDevice *d, 

                              uint32_t address, uint32_t val, int len)

{

    int can_write, i;

    uint32_t end, addr;

    if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || 

                     (address >= 0x30 && address < 0x34))) {

        PCIIORegion *r;

        int reg;

        if ( address >= 0x30 ) {

            reg = PCI_ROM_SLOT;

        }else{

            reg = (address - 0x10) >> 2;

        }

        r = &d->io_regions[reg];

        if (r->size == 0)

            goto default_config;

        /* compute the stored value */

        if (reg == PCI_ROM_SLOT) {

            /* keep ROM enable bit */

            val &= (~(r->size - 1)) | 1;

        } else {

            val &= ~(r->size - 1);

            val |= r->type;

        }

        *(uint32_t *)(d->config + address) = cpu_to_le32(val);

        pci_update_mappings(d);

        return;

    }

 default_config:

    /* not efficient, but simple */

    addr = address;

    for(i = 0; i < len; i++) {

        /* default read/write accesses */

        switch(d->config[0x0e]) {

        case 0x00:

        case 0x80:

            switch(addr) {

            case 0x00:

            case 0x01:

            case 0x02:

            case 0x03:

            case 0x08:

            case 0x09:

            case 0x0a:

            case 0x0b:

            case 0x0e:

            case 0x10 ... 0x27: /* base */

            case 0x30 ... 0x33: /* rom */

            case 0x3d:

                can_write = 0;

                break;

            default:

                can_write = 1;

                break;

            }

            break;

        default:

        case 0x01:

            switch(addr) {

            case 0x00:

            case 0x01:

            case 0x02:

            case 0x03:

            case 0x08:

            case 0x09:

            case 0x0a:

            case 0x0b:

            case 0x0e:

            case 0x38 ... 0x3b: /* rom */

            case 0x3d:

                can_write = 0;

                break;

            default:

                can_write = 1;

                break;

            }

            break;

        }

        if (can_write) {

            d->config[addr] = val;

        }

        addr++;

        val >>= 8;

    }

    end = address + len;

    if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {

        /* if the command register is modified, we must modify the mappings */

        pci_update_mappings(d);

    }

}

static void pci_data_write(void *opaque, uint32_t addr, 

                           uint32_t val, int len)

{

    PCIBus *s = opaque;

    PCIDevice *pci_dev;

    int config_addr, bus_num;

#if defined(DEBUG_PCI) && 0

    printf("pci_data_write: addr=%08x val=%08x len=%d\n",

           s->config_reg, val, len);

#endif

    if (!(s->config_reg & (1 << 31))) {

        return;

    }

    bus_num = (s->config_reg >> 16) & 0xff;

    if (bus_num != 0)

        return;

    pci_dev = s->devices[(s->config_reg >> 8) & 0xff];

    if (!pci_dev)

        return;

    config_addr = (s->config_reg & 0xfc) | (addr & 3);

#if defined(DEBUG_PCI)

    printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",

           pci_dev->name, config_addr, val, len);

#endif

    pci_dev->config_write(pci_dev, config_addr, val, len);

}

static uint32_t pci_data_read(void *opaque, uint32_t addr, 

                              int len)

{

    PCIBus *s = opaque;

    PCIDevice *pci_dev;

    int config_addr, bus_num;

    uint32_t val;

    if (!(s->config_reg & (1 << 31)))

        goto fail;

    bus_num = (s->config_reg >> 16) & 0xff;

    if (bus_num != 0)

        goto fail;

    pci_dev = s->devices[(s->config_reg >> 8) & 0xff];

    if (!pci_dev) {

    fail:

        switch(len) {

        case 1:

            val = 0xff;

            break;

        case 2:

            val = 0xffff;

            break;

        default:

        case 4:

            val = 0xffffffff;

            break;

        }

        goto the_end;

    }

    config_addr = (s->config_reg & 0xfc) | (addr & 3);

    val = pci_dev->config_read(pci_dev, config_addr, len);

#if defined(DEBUG_PCI)

    printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",

           pci_dev->name, config_addr, val, len);

#endif

 the_end:

#if defined(DEBUG_PCI) && 0

    printf("pci_data_read: addr=%08x val=%08x len=%d\n",

           s->config_reg, val, len);

#endif

    return val;

}

static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)

{

    pci_data_write(opaque, addr, val, 1);

}

static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)

{

    pci_data_write(opaque, addr, val, 2);

}

static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)

{

    pci_data_write(opaque, addr, val, 4);

}

static uint32_t pci_data_readb(void* opaque, uint32_t addr)

{

    return pci_data_read(opaque, addr, 1);

}

static uint32_t pci_data_readw(void* opaque, uint32_t addr)

{

    return pci_data_read(opaque, addr, 2);

}

static uint32_t pci_data_readl(void* opaque, uint32_t addr)

{

    return pci_data_read(opaque, addr, 4);

}

/* i440FX PCI bridge */

static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);

PCIBus *i440fx_init(void)

{

    PCIBus *s;

    PCIDevice *d;

    s = pci_register_bus();

    s->set_irq = piix3_set_irq;

    register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);

    register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);

    register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);

    register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);

    register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);

    register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);

    register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);

    register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);

    d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0, 

                            NULL, NULL);

    d->config[0x00] = 0x86; // vendor_id

    d->config[0x01] = 0x80;

    d->config[0x02] = 0x37; // device_id

    d->config[0x03] = 0x12;

    d->config[0x08] = 0x02; // revision

    d->config[0x0a] = 0x00; // class_sub = host2pci

    d->config[0x0b] = 0x06; // class_base = PCI_bridge

    d->config[0x0e] = 0x00; // header_type

    return s;

}

/* PIIX3 PCI to ISA bridge */

typedef struct PIIX3State {

    PCIDevice dev;

} PIIX3State;

PIIX3State *piix3_state;

/* return the global irq number corresponding to a given device irq

   pin. We could also use the bus number to have a more precise

   mapping. */

static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)

{

    int slot_addend;

    slot_addend = (pci_dev->devfn >> 3) - 1;

    return (irq_num + slot_addend) & 3;

}

static inline int get_pci_irq_level(int irq_num)

{

    int pic_level;

#if (PCI_IRQ_WORDS == 2)

    pic_level = ((pci_irq_levels[irq_num][0] | 

                  pci_irq_levels[irq_num][1]) != 0);

#else

    {

        int i;

        pic_level = 0;

        for(i = 0; i < PCI_IRQ_WORDS; i++) {

            if (pci_irq_levels[irq_num][i]) {

                pic_level = 1;

                break;

            }

        }

    }

#endif

    return pic_level;

}

static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)

{

    int irq_index, shift, pic_irq, pic_level;

    uint32_t *p;

    irq_num = pci_slot_get_pirq(pci_dev, irq_num);

    irq_index = pci_dev->irq_index;

    p = &pci_irq_levels[irq_num][irq_index >> 5];

    shift = (irq_index & 0x1f);

    *p = (*p & ~(1 << shift)) | (level << shift);

    /* now we change the pic irq level according to the piix irq mappings */

    /* XXX: optimize */

    pic_irq = piix3_state->dev.config[0x60 + irq_num];

    if (pic_irq < 16) {

        /* the pic level is the logical OR of all the PCI irqs mapped

           to it */

        pic_level = 0;

        if (pic_irq == piix3_state->dev.config[0x60])

            pic_level |= get_pci_irq_level(0);

        if (pic_irq == piix3_state->dev.config[0x61])

            pic_level |= get_pci_irq_level(1);

        if (pic_irq == piix3_state->dev.config[0x62])

            pic_level |= get_pci_irq_level(2);

        if (pic_irq == piix3_state->dev.config[0x63])

            pic_level |= get_pci_irq_level(3);

        pic_set_irq(pic_irq, pic_level);

    }

}

static void piix3_reset(PIIX3State *d)

{

    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; // master, memory and I/O

    pci_conf[0x05] = 0x00;

    pci_conf[0x06] = 0x00;

    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium

    pci_conf[0x4c] = 0x4d;

    pci_conf[0x4e] = 0x03;

    pci_conf[0x4f] = 0x00;

    pci_conf[0x60] = 0x80;

    pci_conf[0x69] = 0x02;

    pci_conf[0x70] = 0x80;

    pci_conf[0x76] = 0x0c;

    pci_conf[0x77] = 0x0c;

    pci_conf[0x78] = 0x02;

    pci_conf[0x79] = 0x00;

    pci_conf[0x80] = 0x00;

    pci_conf[0x82] = 0x00;

    pci_conf[0xa0] = 0x08;

    pci_conf[0xa0] = 0x08;

    pci_conf[0xa2] = 0x00;

    pci_conf[0xa3] = 0x00;

    pci_conf[0xa4] = 0x00;

    pci_conf[0xa5] = 0x00;

    pci_conf[0xa6] = 0x00;

    pci_conf[0xa7] = 0x00;

    pci_conf[0xa8] = 0x0f;

    pci_conf[0xaa] = 0x00;

    pci_conf[0xab] = 0x00;

    pci_conf[0xac] = 0x00;

    pci_conf[0xae] = 0x00;

}

void piix3_init(PCIBus *bus)

{

    PIIX3State *d;

    uint8_t *pci_conf;

    d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),

                                          -1, NULL, NULL);

    register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);

    piix3_state = d;

    pci_conf = d->dev.config;

    pci_conf[0x00] = 0x86; // Intel

    pci_conf[0x01] = 0x80;

    pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)

    pci_conf[0x03] = 0x70;

    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA

    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge

    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic

    piix3_reset(d);

}

/* PREP pci init */

static inline void set_config(PCIBus *s, target_phys_addr_t addr)

{

    int devfn, i;

    for(i = 0; i < 11; i++) {

        if ((addr & (1 << (11 + i))) != 0)

            break;

    }

    devfn = ((addr >> 8) & 7) | (i << 3);

    s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);

}

static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)

{

    PCIBus *s = opaque;

    set_config(s, addr);

    pci_data_write(s, addr, val, 1);

}

static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)

{

    PCIBus *s = opaque;

    set_config(s, addr);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap16(val);

#endif

    pci_data_write(s, addr, val, 2);

}

static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)

{

    PCIBus *s = opaque;

    set_config(s, addr);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    pci_data_write(s, addr, val, 4);

}

static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)

{

    PCIBus *s = opaque;

    uint32_t val;

    set_config(s, addr);

    val = pci_data_read(s, addr, 1);

    return val;

}

static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)

{

    PCIBus *s = opaque;

    uint32_t val;

    set_config(s, addr);

    val = pci_data_read(s, addr, 2);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap16(val);

#endif

    return val;

}

static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)

{

    PCIBus *s = opaque;

    uint32_t val;

    set_config(s, addr);

    val = pci_data_read(s, addr, 4);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    return val;

}

static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {

    &PPC_PCIIO_writeb,

    &PPC_PCIIO_writew,

    &PPC_PCIIO_writel,

};

static CPUReadMemoryFunc *PPC_PCIIO_read[] = {

    &PPC_PCIIO_readb,

    &PPC_PCIIO_readw,

    &PPC_PCIIO_readl,

};

static void prep_set_irq(PCIDevice *d, int irq_num, int level)

{

    /* XXX: we do not simulate the hardware - we rely on the BIOS to

       set correctly for irq line field */

    pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);

}

PCIBus *pci_prep_init(void)

{

    PCIBus *s;

    PCIDevice *d;

    int PPC_io_memory;

    s = pci_register_bus();

    s->set_irq = prep_set_irq;

    register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);

    register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);

    register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);

    register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);

    register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);

    register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);

    register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);

    register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);

    PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, 

                                           PPC_PCIIO_write, s);

    cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);

    /* PCI host bridge */ 

    d = pci_register_device(s, "PREP Host Bridge - Motorola Raven", 

                            sizeof(PCIDevice), 0, NULL, NULL);

    d->config[0x00] = 0x57; // vendor_id : Motorola

    d->config[0x01] = 0x10;

    d->config[0x02] = 0x01; // device_id : Raven

    d->config[0x03] = 0x48;

    d->config[0x08] = 0x00; // revision

    d->config[0x0A] = 0x00; // class_sub = pci host

    d->config[0x0B] = 0x06; // class_base = PCI_bridge

    d->config[0x0C] = 0x08; // cache_line_size

    d->config[0x0D] = 0x10; // latency_timer

    d->config[0x0E] = 0x00; // header_type

    d->config[0x34] = 0x00; // capabilities_pointer

    return s;

}

/* Grackle PCI host */

static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,

                                       uint32_t val)

{

    PCIBus *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    s->config_reg = val;

}

static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)

{

    PCIBus *s = opaque;

    uint32_t val;

    val = s->config_reg;

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    return val;

}

static CPUWriteMemoryFunc *pci_grackle_config_write[] = {

    &pci_grackle_config_writel,

    &pci_grackle_config_writel,

    &pci_grackle_config_writel,

};

static CPUReadMemoryFunc *pci_grackle_config_read[] = {

    &pci_grackle_config_readl,

    &pci_grackle_config_readl,

    &pci_grackle_config_readl,

};

static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,

                                uint32_t val)

{

    PCIBus *s = opaque;

    pci_data_write(s, addr, val, 1);

}

static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,

                                uint32_t val)

{

    PCIBus *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap16(val);

#endif

    pci_data_write(s, addr, val, 2);

}

static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,

                                uint32_t val)

{

    PCIBus *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    pci_data_write(s, addr, val, 4);

}

static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)

{

    PCIBus *s = opaque;

    uint32_t val;

    val = pci_data_read(s, addr, 1);

    return val;

}

static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)

{

    PCIBus *s = opaque;

    uint32_t val;

    val = pci_data_read(s, addr, 2);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap16(val);

#endif

    return val;

}

static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)

{

    PCIBus *s = opaque;

    uint32_t val;

    val = pci_data_read(s, addr, 4);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    return val;

}

static CPUWriteMemoryFunc *pci_grackle_write[] = {

    &pci_grackle_writeb,

    &pci_grackle_writew,

    &pci_grackle_writel,

};

static CPUReadMemoryFunc *pci_grackle_read[] = {

    &pci_grackle_readb,

    &pci_grackle_readw,

    &pci_grackle_readl,

};

void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque)

{

    bus->low_set_irq = set_irq;

    bus->irq_opaque = irq_opaque;

}

/* XXX: we do not simulate the hardware - we rely on the BIOS to

   set correctly for irq line field */

static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level)

{

    PCIBus *s = d->bus;

    s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level);

}

PCIBus *pci_grackle_init(uint32_t base)

{

    PCIBus *s;

    PCIDevice *d;

    int pci_mem_config, pci_mem_data;

    s = pci_register_bus();

    s->set_irq = pci_set_irq_simple;

    pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, 

                                            pci_grackle_config_write, s);

    pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,

                                          pci_grackle_write, s);

    cpu_register_physical_memory(base, 0x1000, pci_mem_config);

    cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);

    d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice), 

                            0, NULL, NULL);