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1 | 008ff9d7 | j_mayer | /*
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2 | 008ff9d7 | j_mayer | * QEMU PowerPC 4xx embedded processors shared devices emulation
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3 | 008ff9d7 | j_mayer | *
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4 | 008ff9d7 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 008ff9d7 | j_mayer | *
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6 | 008ff9d7 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 008ff9d7 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 008ff9d7 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 008ff9d7 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 008ff9d7 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 008ff9d7 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 008ff9d7 | j_mayer | *
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13 | 008ff9d7 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 008ff9d7 | j_mayer | * all copies or substantial portions of the Software.
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15 | 008ff9d7 | j_mayer | *
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16 | 008ff9d7 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 008ff9d7 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 008ff9d7 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 008ff9d7 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 008ff9d7 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 008ff9d7 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 008ff9d7 | j_mayer | * THE SOFTWARE.
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23 | 008ff9d7 | j_mayer | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 008ff9d7 | j_mayer | #include "ppc4xx.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
29 | 008ff9d7 | j_mayer | |
30 | 008ff9d7 | j_mayer | //#define DEBUG_MMIO
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31 | aae9366a | j_mayer | //#define DEBUG_UNASSIGNED
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32 | 008ff9d7 | j_mayer | #define DEBUG_UIC
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33 | 008ff9d7 | j_mayer | |
34 | 008ff9d7 | j_mayer | /*****************************************************************************/
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35 | 008ff9d7 | j_mayer | /* Generic PowerPC 4xx processor instanciation */
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36 | b55266b5 | blueswir1 | CPUState *ppc4xx_init (const char *cpu_model, |
37 | 008ff9d7 | j_mayer | clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
38 | 008ff9d7 | j_mayer | uint32_t sysclk) |
39 | 008ff9d7 | j_mayer | { |
40 | 008ff9d7 | j_mayer | CPUState *env; |
41 | 008ff9d7 | j_mayer | |
42 | 008ff9d7 | j_mayer | /* init CPUs */
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43 | aaed909a | bellard | env = cpu_init(cpu_model); |
44 | aaed909a | bellard | if (!env) {
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45 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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46 | aaed909a | bellard | cpu_model); |
47 | aaed909a | bellard | exit(1);
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48 | 008ff9d7 | j_mayer | } |
49 | 008ff9d7 | j_mayer | cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
50 | 008ff9d7 | j_mayer | cpu_clk->opaque = env; |
51 | 008ff9d7 | j_mayer | /* Set time-base frequency to sysclk */
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52 | 008ff9d7 | j_mayer | tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
53 | 008ff9d7 | j_mayer | tb_clk->opaque = env; |
54 | 008ff9d7 | j_mayer | ppc_dcr_init(env, NULL, NULL); |
55 | 008ff9d7 | j_mayer | /* Register qemu callbacks */
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56 | 008ff9d7 | j_mayer | qemu_register_reset(&cpu_ppc_reset, env); |
57 | 008ff9d7 | j_mayer | |
58 | 008ff9d7 | j_mayer | return env;
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59 | 008ff9d7 | j_mayer | } |
60 | 008ff9d7 | j_mayer | |
61 | 008ff9d7 | j_mayer | /*****************************************************************************/
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62 | 008ff9d7 | j_mayer | /* Fake device used to map multiple devices in a single memory page */
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63 | 008ff9d7 | j_mayer | #define MMIO_AREA_BITS 8 |
64 | 008ff9d7 | j_mayer | #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS) |
65 | 008ff9d7 | j_mayer | #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS)) |
66 | 008ff9d7 | j_mayer | #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1)) |
67 | 008ff9d7 | j_mayer | struct ppc4xx_mmio_t {
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68 | 008ff9d7 | j_mayer | target_phys_addr_t base; |
69 | 008ff9d7 | j_mayer | CPUReadMemoryFunc **mem_read[MMIO_AREA_NB]; |
70 | 008ff9d7 | j_mayer | CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB]; |
71 | 008ff9d7 | j_mayer | void *opaque[MMIO_AREA_NB];
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72 | 008ff9d7 | j_mayer | }; |
73 | 008ff9d7 | j_mayer | |
74 | 008ff9d7 | j_mayer | static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr) |
75 | 008ff9d7 | j_mayer | { |
76 | 008ff9d7 | j_mayer | #ifdef DEBUG_UNASSIGNED
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77 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *mmio; |
78 | 008ff9d7 | j_mayer | |
79 | 008ff9d7 | j_mayer | mmio = opaque; |
80 | 008ff9d7 | j_mayer | printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n", |
81 | 008ff9d7 | j_mayer | addr, mmio->base); |
82 | 008ff9d7 | j_mayer | #endif
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83 | 008ff9d7 | j_mayer | |
84 | 008ff9d7 | j_mayer | return 0; |
85 | 008ff9d7 | j_mayer | } |
86 | 008ff9d7 | j_mayer | |
87 | 008ff9d7 | j_mayer | static void unassigned_mmio_writeb (void *opaque, |
88 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t val) |
89 | 008ff9d7 | j_mayer | { |
90 | 008ff9d7 | j_mayer | #ifdef DEBUG_UNASSIGNED
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91 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *mmio; |
92 | 008ff9d7 | j_mayer | |
93 | 008ff9d7 | j_mayer | mmio = opaque; |
94 | 008ff9d7 | j_mayer | printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n", |
95 | 008ff9d7 | j_mayer | addr, val, mmio->base); |
96 | 008ff9d7 | j_mayer | #endif
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97 | 008ff9d7 | j_mayer | } |
98 | 008ff9d7 | j_mayer | |
99 | 008ff9d7 | j_mayer | static CPUReadMemoryFunc *unassigned_mmio_read[3] = { |
100 | 008ff9d7 | j_mayer | unassigned_mmio_readb, |
101 | 008ff9d7 | j_mayer | unassigned_mmio_readb, |
102 | 008ff9d7 | j_mayer | unassigned_mmio_readb, |
103 | 008ff9d7 | j_mayer | }; |
104 | 008ff9d7 | j_mayer | |
105 | 008ff9d7 | j_mayer | static CPUWriteMemoryFunc *unassigned_mmio_write[3] = { |
106 | 008ff9d7 | j_mayer | unassigned_mmio_writeb, |
107 | 008ff9d7 | j_mayer | unassigned_mmio_writeb, |
108 | 008ff9d7 | j_mayer | unassigned_mmio_writeb, |
109 | 008ff9d7 | j_mayer | }; |
110 | 008ff9d7 | j_mayer | |
111 | 008ff9d7 | j_mayer | static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
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112 | 008ff9d7 | j_mayer | target_phys_addr_t addr, int len)
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113 | 008ff9d7 | j_mayer | { |
114 | 008ff9d7 | j_mayer | CPUReadMemoryFunc **mem_read; |
115 | 008ff9d7 | j_mayer | uint32_t ret; |
116 | 008ff9d7 | j_mayer | int idx;
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117 | 008ff9d7 | j_mayer | |
118 | 008ff9d7 | j_mayer | idx = MMIO_IDX(addr - mmio->base); |
119 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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120 | 008ff9d7 | j_mayer | printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__, |
121 | 008ff9d7 | j_mayer | mmio, len, addr, idx); |
122 | 008ff9d7 | j_mayer | #endif
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123 | 008ff9d7 | j_mayer | mem_read = mmio->mem_read[idx]; |
124 | 008ff9d7 | j_mayer | ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base); |
125 | 008ff9d7 | j_mayer | |
126 | 008ff9d7 | j_mayer | return ret;
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127 | 008ff9d7 | j_mayer | } |
128 | 008ff9d7 | j_mayer | |
129 | 008ff9d7 | j_mayer | static void mmio_writelen (ppc4xx_mmio_t *mmio, |
130 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value, int len)
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131 | 008ff9d7 | j_mayer | { |
132 | 008ff9d7 | j_mayer | CPUWriteMemoryFunc **mem_write; |
133 | 008ff9d7 | j_mayer | int idx;
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134 | 008ff9d7 | j_mayer | |
135 | 008ff9d7 | j_mayer | idx = MMIO_IDX(addr - mmio->base); |
136 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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137 | aae9366a | j_mayer | printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n", |
138 | aae9366a | j_mayer | __func__, mmio, len, addr, idx, value); |
139 | 008ff9d7 | j_mayer | #endif
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140 | 008ff9d7 | j_mayer | mem_write = mmio->mem_write[idx]; |
141 | 008ff9d7 | j_mayer | (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value); |
142 | 008ff9d7 | j_mayer | } |
143 | 008ff9d7 | j_mayer | |
144 | 008ff9d7 | j_mayer | static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr) |
145 | 008ff9d7 | j_mayer | { |
146 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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147 | 008ff9d7 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
148 | 008ff9d7 | j_mayer | #endif
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149 | 008ff9d7 | j_mayer | |
150 | 008ff9d7 | j_mayer | return mmio_readlen(opaque, addr, 0); |
151 | 008ff9d7 | j_mayer | } |
152 | 008ff9d7 | j_mayer | |
153 | 008ff9d7 | j_mayer | static void mmio_writeb (void *opaque, |
154 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value) |
155 | 008ff9d7 | j_mayer | { |
156 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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157 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
158 | 008ff9d7 | j_mayer | #endif
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159 | 008ff9d7 | j_mayer | mmio_writelen(opaque, addr, value, 0);
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160 | 008ff9d7 | j_mayer | } |
161 | 008ff9d7 | j_mayer | |
162 | 008ff9d7 | j_mayer | static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr) |
163 | 008ff9d7 | j_mayer | { |
164 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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165 | 008ff9d7 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
166 | 008ff9d7 | j_mayer | #endif
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167 | 008ff9d7 | j_mayer | |
168 | 008ff9d7 | j_mayer | return mmio_readlen(opaque, addr, 1); |
169 | 008ff9d7 | j_mayer | } |
170 | 008ff9d7 | j_mayer | |
171 | 008ff9d7 | j_mayer | static void mmio_writew (void *opaque, |
172 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value) |
173 | 008ff9d7 | j_mayer | { |
174 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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175 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
176 | 008ff9d7 | j_mayer | #endif
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177 | 008ff9d7 | j_mayer | mmio_writelen(opaque, addr, value, 1);
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178 | 008ff9d7 | j_mayer | } |
179 | 008ff9d7 | j_mayer | |
180 | 008ff9d7 | j_mayer | static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr) |
181 | 008ff9d7 | j_mayer | { |
182 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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183 | 008ff9d7 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
184 | 008ff9d7 | j_mayer | #endif
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185 | 008ff9d7 | j_mayer | |
186 | 008ff9d7 | j_mayer | return mmio_readlen(opaque, addr, 2); |
187 | 008ff9d7 | j_mayer | } |
188 | 008ff9d7 | j_mayer | |
189 | 008ff9d7 | j_mayer | static void mmio_writel (void *opaque, |
190 | 008ff9d7 | j_mayer | target_phys_addr_t addr, uint32_t value) |
191 | 008ff9d7 | j_mayer | { |
192 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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193 | aae9366a | j_mayer | printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); |
194 | 008ff9d7 | j_mayer | #endif
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195 | 008ff9d7 | j_mayer | mmio_writelen(opaque, addr, value, 2);
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196 | 008ff9d7 | j_mayer | } |
197 | 008ff9d7 | j_mayer | |
198 | 008ff9d7 | j_mayer | static CPUReadMemoryFunc *mmio_read[] = {
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199 | 008ff9d7 | j_mayer | &mmio_readb, |
200 | 008ff9d7 | j_mayer | &mmio_readw, |
201 | 008ff9d7 | j_mayer | &mmio_readl, |
202 | 008ff9d7 | j_mayer | }; |
203 | 008ff9d7 | j_mayer | |
204 | 008ff9d7 | j_mayer | static CPUWriteMemoryFunc *mmio_write[] = {
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205 | 008ff9d7 | j_mayer | &mmio_writeb, |
206 | 008ff9d7 | j_mayer | &mmio_writew, |
207 | 008ff9d7 | j_mayer | &mmio_writel, |
208 | 008ff9d7 | j_mayer | }; |
209 | 008ff9d7 | j_mayer | |
210 | 008ff9d7 | j_mayer | int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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211 | 008ff9d7 | j_mayer | target_phys_addr_t offset, uint32_t len, |
212 | 008ff9d7 | j_mayer | CPUReadMemoryFunc **mem_read, |
213 | 008ff9d7 | j_mayer | CPUWriteMemoryFunc **mem_write, void *opaque)
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214 | 008ff9d7 | j_mayer | { |
215 | aae9366a | j_mayer | target_phys_addr_t end; |
216 | 008ff9d7 | j_mayer | int idx, eidx;
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217 | 008ff9d7 | j_mayer | |
218 | 008ff9d7 | j_mayer | if ((offset + len) > TARGET_PAGE_SIZE)
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219 | 008ff9d7 | j_mayer | return -1; |
220 | 008ff9d7 | j_mayer | idx = MMIO_IDX(offset); |
221 | 008ff9d7 | j_mayer | end = offset + len - 1;
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222 | 008ff9d7 | j_mayer | eidx = MMIO_IDX(end); |
223 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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224 | aae9366a | j_mayer | printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n", |
225 | aae9366a | j_mayer | __func__, offset, len, end, idx, eidx); |
226 | 008ff9d7 | j_mayer | #endif
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227 | 008ff9d7 | j_mayer | for (; idx <= eidx; idx++) {
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228 | 008ff9d7 | j_mayer | mmio->mem_read[idx] = mem_read; |
229 | 008ff9d7 | j_mayer | mmio->mem_write[idx] = mem_write; |
230 | 008ff9d7 | j_mayer | mmio->opaque[idx] = opaque; |
231 | 008ff9d7 | j_mayer | } |
232 | 008ff9d7 | j_mayer | |
233 | 008ff9d7 | j_mayer | return 0; |
234 | 008ff9d7 | j_mayer | } |
235 | 008ff9d7 | j_mayer | |
236 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) |
237 | 008ff9d7 | j_mayer | { |
238 | 008ff9d7 | j_mayer | ppc4xx_mmio_t *mmio; |
239 | 008ff9d7 | j_mayer | int mmio_memory;
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240 | 008ff9d7 | j_mayer | |
241 | 008ff9d7 | j_mayer | mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
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242 | 008ff9d7 | j_mayer | if (mmio != NULL) { |
243 | 008ff9d7 | j_mayer | mmio->base = base; |
244 | 008ff9d7 | j_mayer | mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
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245 | 008ff9d7 | j_mayer | #if defined(DEBUG_MMIO)
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246 | aae9366a | j_mayer | printf("%s: base " PADDRX " len %08x %d\n", __func__, |
247 | aae9366a | j_mayer | base, TARGET_PAGE_SIZE, mmio_memory); |
248 | 008ff9d7 | j_mayer | #endif
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249 | 008ff9d7 | j_mayer | cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
250 | 008ff9d7 | j_mayer | ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
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251 | 008ff9d7 | j_mayer | unassigned_mmio_read, unassigned_mmio_write, |
252 | 008ff9d7 | j_mayer | mmio); |
253 | 008ff9d7 | j_mayer | } |
254 | 008ff9d7 | j_mayer | |
255 | 008ff9d7 | j_mayer | return mmio;
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256 | 008ff9d7 | j_mayer | } |
257 | 008ff9d7 | j_mayer | |
258 | 008ff9d7 | j_mayer | /*****************************************************************************/
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259 | 008ff9d7 | j_mayer | /* "Universal" Interrupt controller */
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260 | 008ff9d7 | j_mayer | enum {
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261 | 008ff9d7 | j_mayer | DCR_UICSR = 0x000,
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262 | 008ff9d7 | j_mayer | DCR_UICSRS = 0x001,
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263 | 008ff9d7 | j_mayer | DCR_UICER = 0x002,
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264 | 008ff9d7 | j_mayer | DCR_UICCR = 0x003,
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265 | 008ff9d7 | j_mayer | DCR_UICPR = 0x004,
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266 | 008ff9d7 | j_mayer | DCR_UICTR = 0x005,
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267 | 008ff9d7 | j_mayer | DCR_UICMSR = 0x006,
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268 | 008ff9d7 | j_mayer | DCR_UICVR = 0x007,
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269 | 008ff9d7 | j_mayer | DCR_UICVCR = 0x008,
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270 | 008ff9d7 | j_mayer | DCR_UICMAX = 0x009,
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271 | 008ff9d7 | j_mayer | }; |
272 | 008ff9d7 | j_mayer | |
273 | 008ff9d7 | j_mayer | #define UIC_MAX_IRQ 32 |
274 | 008ff9d7 | j_mayer | typedef struct ppcuic_t ppcuic_t; |
275 | 008ff9d7 | j_mayer | struct ppcuic_t {
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276 | 008ff9d7 | j_mayer | uint32_t dcr_base; |
277 | 008ff9d7 | j_mayer | int use_vectors;
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278 | 4c54e875 | aurel32 | uint32_t level; /* Remembers the state of level-triggered interrupts. */
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279 | 008ff9d7 | j_mayer | uint32_t uicsr; /* Status register */
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280 | 008ff9d7 | j_mayer | uint32_t uicer; /* Enable register */
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281 | 008ff9d7 | j_mayer | uint32_t uiccr; /* Critical register */
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282 | 008ff9d7 | j_mayer | uint32_t uicpr; /* Polarity register */
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283 | 008ff9d7 | j_mayer | uint32_t uictr; /* Triggering register */
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284 | 008ff9d7 | j_mayer | uint32_t uicvcr; /* Vector configuration register */
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285 | 008ff9d7 | j_mayer | uint32_t uicvr; |
286 | 008ff9d7 | j_mayer | qemu_irq *irqs; |
287 | 008ff9d7 | j_mayer | }; |
288 | 008ff9d7 | j_mayer | |
289 | 008ff9d7 | j_mayer | static void ppcuic_trigger_irq (ppcuic_t *uic) |
290 | 008ff9d7 | j_mayer | { |
291 | 008ff9d7 | j_mayer | uint32_t ir, cr; |
292 | 008ff9d7 | j_mayer | int start, end, inc, i;
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293 | 008ff9d7 | j_mayer | |
294 | 008ff9d7 | j_mayer | /* Trigger interrupt if any is pending */
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295 | 008ff9d7 | j_mayer | ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
296 | 008ff9d7 | j_mayer | cr = uic->uicsr & uic->uicer & uic->uiccr; |
297 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
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298 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
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299 | aae9366a | j_mayer | fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
300 | aae9366a | j_mayer | " uiccr %08" PRIx32 "\n" |
301 | aae9366a | j_mayer | " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", |
302 | aae9366a | j_mayer | __func__, uic->uicsr, uic->uicer, uic->uiccr, |
303 | 008ff9d7 | j_mayer | uic->uicsr & uic->uicer, ir, cr); |
304 | 008ff9d7 | j_mayer | } |
305 | 008ff9d7 | j_mayer | #endif
|
306 | 008ff9d7 | j_mayer | if (ir != 0x0000000) { |
307 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
|
308 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
309 | 008ff9d7 | j_mayer | fprintf(logfile, "Raise UIC interrupt\n");
|
310 | 008ff9d7 | j_mayer | } |
311 | 008ff9d7 | j_mayer | #endif
|
312 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
313 | 008ff9d7 | j_mayer | } else {
|
314 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
|
315 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
316 | 008ff9d7 | j_mayer | fprintf(logfile, "Lower UIC interrupt\n");
|
317 | 008ff9d7 | j_mayer | } |
318 | 008ff9d7 | j_mayer | #endif
|
319 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
320 | 008ff9d7 | j_mayer | } |
321 | 008ff9d7 | j_mayer | /* Trigger critical interrupt if any is pending and update vector */
|
322 | 008ff9d7 | j_mayer | if (cr != 0x0000000) { |
323 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
324 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
|
325 | 008ff9d7 | j_mayer | /* Compute critical IRQ vector */
|
326 | 008ff9d7 | j_mayer | if (uic->uicvcr & 1) { |
327 | 008ff9d7 | j_mayer | start = 31;
|
328 | 008ff9d7 | j_mayer | end = 0;
|
329 | 008ff9d7 | j_mayer | inc = -1;
|
330 | 008ff9d7 | j_mayer | } else {
|
331 | 008ff9d7 | j_mayer | start = 0;
|
332 | 008ff9d7 | j_mayer | end = 31;
|
333 | 008ff9d7 | j_mayer | inc = 1;
|
334 | 008ff9d7 | j_mayer | } |
335 | 008ff9d7 | j_mayer | uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
|
336 | 008ff9d7 | j_mayer | for (i = start; i <= end; i += inc) {
|
337 | 008ff9d7 | j_mayer | if (cr & (1 << i)) { |
338 | 008ff9d7 | j_mayer | uic->uicvr += (i - start) * 512 * inc;
|
339 | 008ff9d7 | j_mayer | break;
|
340 | 008ff9d7 | j_mayer | } |
341 | 008ff9d7 | j_mayer | } |
342 | 008ff9d7 | j_mayer | } |
343 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
|
344 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
345 | aae9366a | j_mayer | fprintf(logfile, "Raise UIC critical interrupt - "
|
346 | aae9366a | j_mayer | "vector %08" PRIx32 "\n", uic->uicvr); |
347 | 008ff9d7 | j_mayer | } |
348 | 008ff9d7 | j_mayer | #endif
|
349 | 008ff9d7 | j_mayer | } else {
|
350 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
|
351 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
352 | 008ff9d7 | j_mayer | fprintf(logfile, "Lower UIC critical interrupt\n");
|
353 | 008ff9d7 | j_mayer | } |
354 | 008ff9d7 | j_mayer | #endif
|
355 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
356 | 008ff9d7 | j_mayer | uic->uicvr = 0x00000000;
|
357 | 008ff9d7 | j_mayer | } |
358 | 008ff9d7 | j_mayer | } |
359 | 008ff9d7 | j_mayer | |
360 | 008ff9d7 | j_mayer | static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
361 | 008ff9d7 | j_mayer | { |
362 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
363 | 008ff9d7 | j_mayer | uint32_t mask, sr; |
364 | 008ff9d7 | j_mayer | |
365 | 008ff9d7 | j_mayer | uic = opaque; |
366 | 923e5e33 | aurel32 | mask = 1 << (31-irq_num); |
367 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
|
368 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
369 | aae9366a | j_mayer | fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
|
370 | aae9366a | j_mayer | " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
371 | aae9366a | j_mayer | __func__, irq_num, level, |
372 | 008ff9d7 | j_mayer | uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
373 | 008ff9d7 | j_mayer | } |
374 | 008ff9d7 | j_mayer | #endif
|
375 | 008ff9d7 | j_mayer | if (irq_num < 0 || irq_num > 31) |
376 | 008ff9d7 | j_mayer | return;
|
377 | 008ff9d7 | j_mayer | sr = uic->uicsr; |
378 | 50bf72b3 | aurel32 | |
379 | 008ff9d7 | j_mayer | /* Update status register */
|
380 | 008ff9d7 | j_mayer | if (uic->uictr & mask) {
|
381 | 008ff9d7 | j_mayer | /* Edge sensitive interrupt */
|
382 | 008ff9d7 | j_mayer | if (level == 1) |
383 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
384 | 008ff9d7 | j_mayer | } else {
|
385 | 008ff9d7 | j_mayer | /* Level sensitive interrupt */
|
386 | 4c54e875 | aurel32 | if (level == 1) { |
387 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
388 | 4c54e875 | aurel32 | uic->level |= mask; |
389 | 4c54e875 | aurel32 | } else {
|
390 | 008ff9d7 | j_mayer | uic->uicsr &= ~mask; |
391 | 4c54e875 | aurel32 | uic->level &= ~mask; |
392 | 4c54e875 | aurel32 | } |
393 | 008ff9d7 | j_mayer | } |
394 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
|
395 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
396 | aae9366a | j_mayer | fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => " |
397 | aae9366a | j_mayer | "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
398 | 008ff9d7 | j_mayer | } |
399 | 008ff9d7 | j_mayer | #endif
|
400 | 008ff9d7 | j_mayer | if (sr != uic->uicsr)
|
401 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
402 | 008ff9d7 | j_mayer | } |
403 | 008ff9d7 | j_mayer | |
404 | 008ff9d7 | j_mayer | static target_ulong dcr_read_uic (void *opaque, int dcrn) |
405 | 008ff9d7 | j_mayer | { |
406 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
407 | 008ff9d7 | j_mayer | target_ulong ret; |
408 | 008ff9d7 | j_mayer | |
409 | 008ff9d7 | j_mayer | uic = opaque; |
410 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
411 | 008ff9d7 | j_mayer | switch (dcrn) {
|
412 | 008ff9d7 | j_mayer | case DCR_UICSR:
|
413 | 008ff9d7 | j_mayer | case DCR_UICSRS:
|
414 | 008ff9d7 | j_mayer | ret = uic->uicsr; |
415 | 008ff9d7 | j_mayer | break;
|
416 | 008ff9d7 | j_mayer | case DCR_UICER:
|
417 | 008ff9d7 | j_mayer | ret = uic->uicer; |
418 | 008ff9d7 | j_mayer | break;
|
419 | 008ff9d7 | j_mayer | case DCR_UICCR:
|
420 | 008ff9d7 | j_mayer | ret = uic->uiccr; |
421 | 008ff9d7 | j_mayer | break;
|
422 | 008ff9d7 | j_mayer | case DCR_UICPR:
|
423 | 008ff9d7 | j_mayer | ret = uic->uicpr; |
424 | 008ff9d7 | j_mayer | break;
|
425 | 008ff9d7 | j_mayer | case DCR_UICTR:
|
426 | 008ff9d7 | j_mayer | ret = uic->uictr; |
427 | 008ff9d7 | j_mayer | break;
|
428 | 008ff9d7 | j_mayer | case DCR_UICMSR:
|
429 | 008ff9d7 | j_mayer | ret = uic->uicsr & uic->uicer; |
430 | 008ff9d7 | j_mayer | break;
|
431 | 008ff9d7 | j_mayer | case DCR_UICVR:
|
432 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
|
433 | 008ff9d7 | j_mayer | goto no_read;
|
434 | 008ff9d7 | j_mayer | ret = uic->uicvr; |
435 | 008ff9d7 | j_mayer | break;
|
436 | 008ff9d7 | j_mayer | case DCR_UICVCR:
|
437 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
|
438 | 008ff9d7 | j_mayer | goto no_read;
|
439 | 008ff9d7 | j_mayer | ret = uic->uicvcr; |
440 | 008ff9d7 | j_mayer | break;
|
441 | 008ff9d7 | j_mayer | default:
|
442 | 008ff9d7 | j_mayer | no_read:
|
443 | 008ff9d7 | j_mayer | ret = 0x00000000;
|
444 | 008ff9d7 | j_mayer | break;
|
445 | 008ff9d7 | j_mayer | } |
446 | 008ff9d7 | j_mayer | |
447 | 008ff9d7 | j_mayer | return ret;
|
448 | 008ff9d7 | j_mayer | } |
449 | 008ff9d7 | j_mayer | |
450 | 008ff9d7 | j_mayer | static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
451 | 008ff9d7 | j_mayer | { |
452 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
453 | 008ff9d7 | j_mayer | |
454 | 008ff9d7 | j_mayer | uic = opaque; |
455 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
456 | 008ff9d7 | j_mayer | #ifdef DEBUG_UIC
|
457 | 008ff9d7 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
458 | 008ff9d7 | j_mayer | fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
459 | 008ff9d7 | j_mayer | } |
460 | 008ff9d7 | j_mayer | #endif
|
461 | 008ff9d7 | j_mayer | switch (dcrn) {
|
462 | 008ff9d7 | j_mayer | case DCR_UICSR:
|
463 | 008ff9d7 | j_mayer | uic->uicsr &= ~val; |
464 | 4c54e875 | aurel32 | uic->uicsr |= uic->level; |
465 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
466 | 008ff9d7 | j_mayer | break;
|
467 | 008ff9d7 | j_mayer | case DCR_UICSRS:
|
468 | 008ff9d7 | j_mayer | uic->uicsr |= val; |
469 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
470 | 008ff9d7 | j_mayer | break;
|
471 | 008ff9d7 | j_mayer | case DCR_UICER:
|
472 | 008ff9d7 | j_mayer | uic->uicer = val; |
473 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
474 | 008ff9d7 | j_mayer | break;
|
475 | 008ff9d7 | j_mayer | case DCR_UICCR:
|
476 | 008ff9d7 | j_mayer | uic->uiccr = val; |
477 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
478 | 008ff9d7 | j_mayer | break;
|
479 | 008ff9d7 | j_mayer | case DCR_UICPR:
|
480 | 008ff9d7 | j_mayer | uic->uicpr = val; |
481 | 008ff9d7 | j_mayer | break;
|
482 | 008ff9d7 | j_mayer | case DCR_UICTR:
|
483 | 008ff9d7 | j_mayer | uic->uictr = val; |
484 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
485 | 008ff9d7 | j_mayer | break;
|
486 | 008ff9d7 | j_mayer | case DCR_UICMSR:
|
487 | 008ff9d7 | j_mayer | break;
|
488 | 008ff9d7 | j_mayer | case DCR_UICVR:
|
489 | 008ff9d7 | j_mayer | break;
|
490 | 008ff9d7 | j_mayer | case DCR_UICVCR:
|
491 | 008ff9d7 | j_mayer | uic->uicvcr = val & 0xFFFFFFFD;
|
492 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
493 | 008ff9d7 | j_mayer | break;
|
494 | 008ff9d7 | j_mayer | } |
495 | 008ff9d7 | j_mayer | } |
496 | 008ff9d7 | j_mayer | |
497 | 008ff9d7 | j_mayer | static void ppcuic_reset (void *opaque) |
498 | 008ff9d7 | j_mayer | { |
499 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
500 | 008ff9d7 | j_mayer | |
501 | 008ff9d7 | j_mayer | uic = opaque; |
502 | 008ff9d7 | j_mayer | uic->uiccr = 0x00000000;
|
503 | 008ff9d7 | j_mayer | uic->uicer = 0x00000000;
|
504 | 008ff9d7 | j_mayer | uic->uicpr = 0x00000000;
|
505 | 008ff9d7 | j_mayer | uic->uicsr = 0x00000000;
|
506 | 008ff9d7 | j_mayer | uic->uictr = 0x00000000;
|
507 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
|
508 | 008ff9d7 | j_mayer | uic->uicvcr = 0x00000000;
|
509 | 008ff9d7 | j_mayer | uic->uicvr = 0x0000000;
|
510 | 008ff9d7 | j_mayer | } |
511 | 008ff9d7 | j_mayer | } |
512 | 008ff9d7 | j_mayer | |
513 | 008ff9d7 | j_mayer | qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
514 | 008ff9d7 | j_mayer | uint32_t dcr_base, int has_ssr, int has_vr) |
515 | 008ff9d7 | j_mayer | { |
516 | 008ff9d7 | j_mayer | ppcuic_t *uic; |
517 | 008ff9d7 | j_mayer | int i;
|
518 | 008ff9d7 | j_mayer | |
519 | 008ff9d7 | j_mayer | uic = qemu_mallocz(sizeof(ppcuic_t));
|
520 | 008ff9d7 | j_mayer | if (uic != NULL) { |
521 | 008ff9d7 | j_mayer | uic->dcr_base = dcr_base; |
522 | 008ff9d7 | j_mayer | uic->irqs = irqs; |
523 | 008ff9d7 | j_mayer | if (has_vr)
|
524 | 008ff9d7 | j_mayer | uic->use_vectors = 1;
|
525 | 008ff9d7 | j_mayer | for (i = 0; i < DCR_UICMAX; i++) { |
526 | 008ff9d7 | j_mayer | ppc_dcr_register(env, dcr_base + i, uic, |
527 | 008ff9d7 | j_mayer | &dcr_read_uic, &dcr_write_uic); |
528 | 008ff9d7 | j_mayer | } |
529 | 008ff9d7 | j_mayer | qemu_register_reset(ppcuic_reset, uic); |
530 | 008ff9d7 | j_mayer | ppcuic_reset(uic); |
531 | 008ff9d7 | j_mayer | } |
532 | 008ff9d7 | j_mayer | |
533 | 008ff9d7 | j_mayer | return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
534 | 008ff9d7 | j_mayer | } |