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/*
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 * QEMU PowerPC 4xx embedded processors shared devices emulation
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 *
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 * Copyright (c) 2007 Jocelyn Mayer
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "ppc.h"
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#include "ppc4xx.h"
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#include "sysemu.h"
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#include "qemu-log.h"
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//#define DEBUG_MMIO
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//#define DEBUG_UNASSIGNED
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#define DEBUG_UIC
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/*****************************************************************************/
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/* Generic PowerPC 4xx processor instanciation */
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CPUState *ppc4xx_init (const char *cpu_model,
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                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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                       uint32_t sysclk)
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{
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    CPUState *env;
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    /* init CPUs */
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    env = cpu_init(cpu_model);
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    if (!env) {
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        fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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                cpu_model);
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        exit(1);
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    }
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    cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
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    cpu_clk->opaque = env;
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    /* Set time-base frequency to sysclk */
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    tb_clk->cb = ppc_emb_timers_init(env, sysclk);
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    tb_clk->opaque = env;
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    ppc_dcr_init(env, NULL, NULL);
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    /* Register qemu callbacks */
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    qemu_register_reset(&cpu_ppc_reset, env);
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    return env;
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}
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/*****************************************************************************/
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/* Fake device used to map multiple devices in a single memory page */
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#define MMIO_AREA_BITS 8
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#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
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#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
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#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
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struct ppc4xx_mmio_t {
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    target_phys_addr_t base;
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    CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
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    CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
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    void *opaque[MMIO_AREA_NB];
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};
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static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
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{
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#ifdef DEBUG_UNASSIGNED
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    ppc4xx_mmio_t *mmio;
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    mmio = opaque;
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    printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
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           addr, mmio->base);
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#endif
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    return 0;
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}
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static void unassigned_mmio_writeb (void *opaque,
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                                    target_phys_addr_t addr, uint32_t val)
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{
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#ifdef DEBUG_UNASSIGNED
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    ppc4xx_mmio_t *mmio;
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    mmio = opaque;
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    printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
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           addr, val, mmio->base);
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#endif
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}
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static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
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    unassigned_mmio_readb,
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    unassigned_mmio_readb,
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    unassigned_mmio_readb,
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};
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static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
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    unassigned_mmio_writeb,
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    unassigned_mmio_writeb,
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    unassigned_mmio_writeb,
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};
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static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
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                              target_phys_addr_t addr, int len)
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{
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    CPUReadMemoryFunc **mem_read;
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    uint32_t ret;
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    int idx;
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    idx = MMIO_IDX(addr - mmio->base);
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#if defined(DEBUG_MMIO)
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    printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
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           mmio, len, addr, idx);
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#endif
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    mem_read = mmio->mem_read[idx];
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    ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
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    return ret;
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}
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static void mmio_writelen (ppc4xx_mmio_t *mmio,
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                           target_phys_addr_t addr, uint32_t value, int len)
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{
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    CPUWriteMemoryFunc **mem_write;
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    int idx;
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    idx = MMIO_IDX(addr - mmio->base);
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#if defined(DEBUG_MMIO)
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    printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
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           __func__, mmio, len, addr, idx, value);
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#endif
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    mem_write = mmio->mem_write[idx];
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    (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
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}
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static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
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{
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#if defined(DEBUG_MMIO)
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    printf("%s: addr " PADDRX "\n", __func__, addr);
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#endif
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    return mmio_readlen(opaque, addr, 0);
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}
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static void mmio_writeb (void *opaque,
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                         target_phys_addr_t addr, uint32_t value)
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{
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#if defined(DEBUG_MMIO)
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    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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#endif
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    mmio_writelen(opaque, addr, value, 0);
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}
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static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
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{
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#if defined(DEBUG_MMIO)
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    printf("%s: addr " PADDRX "\n", __func__, addr);
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#endif
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    return mmio_readlen(opaque, addr, 1);
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}
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static void mmio_writew (void *opaque,
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                         target_phys_addr_t addr, uint32_t value)
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{
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#if defined(DEBUG_MMIO)
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    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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#endif
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    mmio_writelen(opaque, addr, value, 1);
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}
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static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
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{
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#if defined(DEBUG_MMIO)
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    printf("%s: addr " PADDRX "\n", __func__, addr);
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#endif
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    return mmio_readlen(opaque, addr, 2);
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}
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static void mmio_writel (void *opaque,
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                         target_phys_addr_t addr, uint32_t value)
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{
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#if defined(DEBUG_MMIO)
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    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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#endif
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    mmio_writelen(opaque, addr, value, 2);
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}
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static CPUReadMemoryFunc *mmio_read[] = {
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    &mmio_readb,
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    &mmio_readw,
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    &mmio_readl,
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};
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static CPUWriteMemoryFunc *mmio_write[] = {
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    &mmio_writeb,
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    &mmio_writew,
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    &mmio_writel,
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};
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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                          target_phys_addr_t offset, uint32_t len,
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                          CPUReadMemoryFunc **mem_read,
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                          CPUWriteMemoryFunc **mem_write, void *opaque)
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{
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    target_phys_addr_t end;
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    int idx, eidx;
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    if ((offset + len) > TARGET_PAGE_SIZE)
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        return -1;
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    idx = MMIO_IDX(offset);
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    end = offset + len - 1;
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    eidx = MMIO_IDX(end);
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#if defined(DEBUG_MMIO)
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    printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
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           __func__, offset, len, end, idx, eidx);
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#endif
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    for (; idx <= eidx; idx++) {
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        mmio->mem_read[idx] = mem_read;
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        mmio->mem_write[idx] = mem_write;
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        mmio->opaque[idx] = opaque;
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    }
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    return 0;
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}
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ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
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{
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    ppc4xx_mmio_t *mmio;
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    int mmio_memory;
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    mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
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    if (mmio != NULL) {
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        mmio->base = base;
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        mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
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#if defined(DEBUG_MMIO)
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        printf("%s: base " PADDRX " len %08x %d\n", __func__,
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               base, TARGET_PAGE_SIZE, mmio_memory);
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#endif
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        cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
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        ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
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                             unassigned_mmio_read, unassigned_mmio_write,
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                             mmio);
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    }
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    return mmio;
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}
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/*****************************************************************************/
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/* "Universal" Interrupt controller */
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enum {
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    DCR_UICSR  = 0x000,
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    DCR_UICSRS = 0x001,
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    DCR_UICER  = 0x002,
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    DCR_UICCR  = 0x003,
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    DCR_UICPR  = 0x004,
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    DCR_UICTR  = 0x005,
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    DCR_UICMSR = 0x006,
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    DCR_UICVR  = 0x007,
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    DCR_UICVCR = 0x008,
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    DCR_UICMAX = 0x009,
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};
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#define UIC_MAX_IRQ 32
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typedef struct ppcuic_t ppcuic_t;
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struct ppcuic_t {
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    uint32_t dcr_base;
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    int use_vectors;
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    uint32_t level;  /* Remembers the state of level-triggered interrupts. */
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    uint32_t uicsr;  /* Status register */
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    uint32_t uicer;  /* Enable register */
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    uint32_t uiccr;  /* Critical register */
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    uint32_t uicpr;  /* Polarity register */
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    uint32_t uictr;  /* Triggering register */
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    uint32_t uicvcr; /* Vector configuration register */
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    uint32_t uicvr;
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    qemu_irq *irqs;
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};
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static void ppcuic_trigger_irq (ppcuic_t *uic)
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{
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    uint32_t ir, cr;
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    int start, end, inc, i;
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    /* Trigger interrupt if any is pending */
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    ir = uic->uicsr & uic->uicer & (~uic->uiccr);
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    cr = uic->uicsr & uic->uicer & uic->uiccr;
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#ifdef DEBUG_UIC
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    if (loglevel & CPU_LOG_INT) {
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        fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
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                " uiccr %08" PRIx32 "\n"
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                "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
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                __func__, uic->uicsr, uic->uicer, uic->uiccr,
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                uic->uicsr & uic->uicer, ir, cr);
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    }
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#endif
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    if (ir != 0x0000000) {
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#ifdef DEBUG_UIC
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        if (loglevel & CPU_LOG_INT) {
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            fprintf(logfile, "Raise UIC interrupt\n");
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        }
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#endif
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        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
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    } else {
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#ifdef DEBUG_UIC
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        if (loglevel & CPU_LOG_INT) {
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            fprintf(logfile, "Lower UIC interrupt\n");
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        }
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#endif
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        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
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    }
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    /* Trigger critical interrupt if any is pending and update vector */
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    if (cr != 0x0000000) {
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        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
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        if (uic->use_vectors) {
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            /* Compute critical IRQ vector */
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            if (uic->uicvcr & 1) {
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                start = 31;
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                end = 0;
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                inc = -1;
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            } else {
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                start = 0;
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                end = 31;
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                inc = 1;
334 008ff9d7 j_mayer
            }
335 008ff9d7 j_mayer
            uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
336 008ff9d7 j_mayer
            for (i = start; i <= end; i += inc) {
337 008ff9d7 j_mayer
                if (cr & (1 << i)) {
338 008ff9d7 j_mayer
                    uic->uicvr += (i - start) * 512 * inc;
339 008ff9d7 j_mayer
                    break;
340 008ff9d7 j_mayer
                }
341 008ff9d7 j_mayer
            }
342 008ff9d7 j_mayer
        }
343 008ff9d7 j_mayer
#ifdef DEBUG_UIC
344 008ff9d7 j_mayer
        if (loglevel & CPU_LOG_INT) {
345 aae9366a j_mayer
            fprintf(logfile, "Raise UIC critical interrupt - "
346 aae9366a j_mayer
                    "vector %08" PRIx32 "\n", uic->uicvr);
347 008ff9d7 j_mayer
        }
348 008ff9d7 j_mayer
#endif
349 008ff9d7 j_mayer
    } else {
350 008ff9d7 j_mayer
#ifdef DEBUG_UIC
351 008ff9d7 j_mayer
        if (loglevel & CPU_LOG_INT) {
352 008ff9d7 j_mayer
            fprintf(logfile, "Lower UIC critical interrupt\n");
353 008ff9d7 j_mayer
        }
354 008ff9d7 j_mayer
#endif
355 008ff9d7 j_mayer
        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
356 008ff9d7 j_mayer
        uic->uicvr = 0x00000000;
357 008ff9d7 j_mayer
    }
358 008ff9d7 j_mayer
}
359 008ff9d7 j_mayer
360 008ff9d7 j_mayer
static void ppcuic_set_irq (void *opaque, int irq_num, int level)
361 008ff9d7 j_mayer
{
362 008ff9d7 j_mayer
    ppcuic_t *uic;
363 008ff9d7 j_mayer
    uint32_t mask, sr;
364 008ff9d7 j_mayer
365 008ff9d7 j_mayer
    uic = opaque;
366 923e5e33 aurel32
    mask = 1 << (31-irq_num);
367 008ff9d7 j_mayer
#ifdef DEBUG_UIC
368 008ff9d7 j_mayer
    if (loglevel & CPU_LOG_INT) {
369 aae9366a j_mayer
        fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
370 aae9366a j_mayer
                " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
371 aae9366a j_mayer
                __func__, irq_num, level,
372 008ff9d7 j_mayer
                uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
373 008ff9d7 j_mayer
    }
374 008ff9d7 j_mayer
#endif
375 008ff9d7 j_mayer
    if (irq_num < 0 || irq_num > 31)
376 008ff9d7 j_mayer
        return;
377 008ff9d7 j_mayer
    sr = uic->uicsr;
378 50bf72b3 aurel32
379 008ff9d7 j_mayer
    /* Update status register */
380 008ff9d7 j_mayer
    if (uic->uictr & mask) {
381 008ff9d7 j_mayer
        /* Edge sensitive interrupt */
382 008ff9d7 j_mayer
        if (level == 1)
383 008ff9d7 j_mayer
            uic->uicsr |= mask;
384 008ff9d7 j_mayer
    } else {
385 008ff9d7 j_mayer
        /* Level sensitive interrupt */
386 4c54e875 aurel32
        if (level == 1) {
387 008ff9d7 j_mayer
            uic->uicsr |= mask;
388 4c54e875 aurel32
            uic->level |= mask;
389 4c54e875 aurel32
        } else {
390 008ff9d7 j_mayer
            uic->uicsr &= ~mask;
391 4c54e875 aurel32
            uic->level &= ~mask;
392 4c54e875 aurel32
        }
393 008ff9d7 j_mayer
    }
394 008ff9d7 j_mayer
#ifdef DEBUG_UIC
395 008ff9d7 j_mayer
    if (loglevel & CPU_LOG_INT) {
396 aae9366a j_mayer
        fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
397 aae9366a j_mayer
                "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
398 008ff9d7 j_mayer
    }
399 008ff9d7 j_mayer
#endif
400 008ff9d7 j_mayer
    if (sr != uic->uicsr)
401 008ff9d7 j_mayer
        ppcuic_trigger_irq(uic);
402 008ff9d7 j_mayer
}
403 008ff9d7 j_mayer
404 008ff9d7 j_mayer
static target_ulong dcr_read_uic (void *opaque, int dcrn)
405 008ff9d7 j_mayer
{
406 008ff9d7 j_mayer
    ppcuic_t *uic;
407 008ff9d7 j_mayer
    target_ulong ret;
408 008ff9d7 j_mayer
409 008ff9d7 j_mayer
    uic = opaque;
410 008ff9d7 j_mayer
    dcrn -= uic->dcr_base;
411 008ff9d7 j_mayer
    switch (dcrn) {
412 008ff9d7 j_mayer
    case DCR_UICSR:
413 008ff9d7 j_mayer
    case DCR_UICSRS:
414 008ff9d7 j_mayer
        ret = uic->uicsr;
415 008ff9d7 j_mayer
        break;
416 008ff9d7 j_mayer
    case DCR_UICER:
417 008ff9d7 j_mayer
        ret = uic->uicer;
418 008ff9d7 j_mayer
        break;
419 008ff9d7 j_mayer
    case DCR_UICCR:
420 008ff9d7 j_mayer
        ret = uic->uiccr;
421 008ff9d7 j_mayer
        break;
422 008ff9d7 j_mayer
    case DCR_UICPR:
423 008ff9d7 j_mayer
        ret = uic->uicpr;
424 008ff9d7 j_mayer
        break;
425 008ff9d7 j_mayer
    case DCR_UICTR:
426 008ff9d7 j_mayer
        ret = uic->uictr;
427 008ff9d7 j_mayer
        break;
428 008ff9d7 j_mayer
    case DCR_UICMSR:
429 008ff9d7 j_mayer
        ret = uic->uicsr & uic->uicer;
430 008ff9d7 j_mayer
        break;
431 008ff9d7 j_mayer
    case DCR_UICVR:
432 008ff9d7 j_mayer
        if (!uic->use_vectors)
433 008ff9d7 j_mayer
            goto no_read;
434 008ff9d7 j_mayer
        ret = uic->uicvr;
435 008ff9d7 j_mayer
        break;
436 008ff9d7 j_mayer
    case DCR_UICVCR:
437 008ff9d7 j_mayer
        if (!uic->use_vectors)
438 008ff9d7 j_mayer
            goto no_read;
439 008ff9d7 j_mayer
        ret = uic->uicvcr;
440 008ff9d7 j_mayer
        break;
441 008ff9d7 j_mayer
    default:
442 008ff9d7 j_mayer
    no_read:
443 008ff9d7 j_mayer
        ret = 0x00000000;
444 008ff9d7 j_mayer
        break;
445 008ff9d7 j_mayer
    }
446 008ff9d7 j_mayer
447 008ff9d7 j_mayer
    return ret;
448 008ff9d7 j_mayer
}
449 008ff9d7 j_mayer
450 008ff9d7 j_mayer
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
451 008ff9d7 j_mayer
{
452 008ff9d7 j_mayer
    ppcuic_t *uic;
453 008ff9d7 j_mayer
454 008ff9d7 j_mayer
    uic = opaque;
455 008ff9d7 j_mayer
    dcrn -= uic->dcr_base;
456 008ff9d7 j_mayer
#ifdef DEBUG_UIC
457 008ff9d7 j_mayer
    if (loglevel & CPU_LOG_INT) {
458 008ff9d7 j_mayer
        fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
459 008ff9d7 j_mayer
    }
460 008ff9d7 j_mayer
#endif
461 008ff9d7 j_mayer
    switch (dcrn) {
462 008ff9d7 j_mayer
    case DCR_UICSR:
463 008ff9d7 j_mayer
        uic->uicsr &= ~val;
464 4c54e875 aurel32
        uic->uicsr |= uic->level;
465 008ff9d7 j_mayer
        ppcuic_trigger_irq(uic);
466 008ff9d7 j_mayer
        break;
467 008ff9d7 j_mayer
    case DCR_UICSRS:
468 008ff9d7 j_mayer
        uic->uicsr |= val;
469 008ff9d7 j_mayer
        ppcuic_trigger_irq(uic);
470 008ff9d7 j_mayer
        break;
471 008ff9d7 j_mayer
    case DCR_UICER:
472 008ff9d7 j_mayer
        uic->uicer = val;
473 008ff9d7 j_mayer
        ppcuic_trigger_irq(uic);
474 008ff9d7 j_mayer
        break;
475 008ff9d7 j_mayer
    case DCR_UICCR:
476 008ff9d7 j_mayer
        uic->uiccr = val;
477 008ff9d7 j_mayer
        ppcuic_trigger_irq(uic);
478 008ff9d7 j_mayer
        break;
479 008ff9d7 j_mayer
    case DCR_UICPR:
480 008ff9d7 j_mayer
        uic->uicpr = val;
481 008ff9d7 j_mayer
        break;
482 008ff9d7 j_mayer
    case DCR_UICTR:
483 008ff9d7 j_mayer
        uic->uictr = val;
484 008ff9d7 j_mayer
        ppcuic_trigger_irq(uic);
485 008ff9d7 j_mayer
        break;
486 008ff9d7 j_mayer
    case DCR_UICMSR:
487 008ff9d7 j_mayer
        break;
488 008ff9d7 j_mayer
    case DCR_UICVR:
489 008ff9d7 j_mayer
        break;
490 008ff9d7 j_mayer
    case DCR_UICVCR:
491 008ff9d7 j_mayer
        uic->uicvcr = val & 0xFFFFFFFD;
492 008ff9d7 j_mayer
        ppcuic_trigger_irq(uic);
493 008ff9d7 j_mayer
        break;
494 008ff9d7 j_mayer
    }
495 008ff9d7 j_mayer
}
496 008ff9d7 j_mayer
497 008ff9d7 j_mayer
static void ppcuic_reset (void *opaque)
498 008ff9d7 j_mayer
{
499 008ff9d7 j_mayer
    ppcuic_t *uic;
500 008ff9d7 j_mayer
501 008ff9d7 j_mayer
    uic = opaque;
502 008ff9d7 j_mayer
    uic->uiccr = 0x00000000;
503 008ff9d7 j_mayer
    uic->uicer = 0x00000000;
504 008ff9d7 j_mayer
    uic->uicpr = 0x00000000;
505 008ff9d7 j_mayer
    uic->uicsr = 0x00000000;
506 008ff9d7 j_mayer
    uic->uictr = 0x00000000;
507 008ff9d7 j_mayer
    if (uic->use_vectors) {
508 008ff9d7 j_mayer
        uic->uicvcr = 0x00000000;
509 008ff9d7 j_mayer
        uic->uicvr = 0x0000000;
510 008ff9d7 j_mayer
    }
511 008ff9d7 j_mayer
}
512 008ff9d7 j_mayer
513 008ff9d7 j_mayer
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
514 008ff9d7 j_mayer
                       uint32_t dcr_base, int has_ssr, int has_vr)
515 008ff9d7 j_mayer
{
516 008ff9d7 j_mayer
    ppcuic_t *uic;
517 008ff9d7 j_mayer
    int i;
518 008ff9d7 j_mayer
519 008ff9d7 j_mayer
    uic = qemu_mallocz(sizeof(ppcuic_t));
520 008ff9d7 j_mayer
    if (uic != NULL) {
521 008ff9d7 j_mayer
        uic->dcr_base = dcr_base;
522 008ff9d7 j_mayer
        uic->irqs = irqs;
523 008ff9d7 j_mayer
        if (has_vr)
524 008ff9d7 j_mayer
            uic->use_vectors = 1;
525 008ff9d7 j_mayer
        for (i = 0; i < DCR_UICMAX; i++) {
526 008ff9d7 j_mayer
            ppc_dcr_register(env, dcr_base + i, uic,
527 008ff9d7 j_mayer
                             &dcr_read_uic, &dcr_write_uic);
528 008ff9d7 j_mayer
        }
529 008ff9d7 j_mayer
        qemu_register_reset(ppcuic_reset, uic);
530 008ff9d7 j_mayer
        ppcuic_reset(uic);
531 008ff9d7 j_mayer
    }
532 008ff9d7 j_mayer
533 008ff9d7 j_mayer
    return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
534 008ff9d7 j_mayer
}