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/*
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* Arm PrimeCell PL011 UART
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "qemu-char.h" |
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#include "primecell.h" |
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typedef struct { |
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uint32_t base; |
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uint32_t readbuff; |
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uint32_t flags; |
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uint32_t lcr; |
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uint32_t cr; |
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uint32_t dmacr; |
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uint32_t int_enabled; |
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uint32_t int_level; |
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uint32_t read_fifo[16];
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uint32_t ilpr; |
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uint32_t ibrd; |
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uint32_t fbrd; |
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uint32_t ifl; |
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int read_pos;
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int read_count;
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int read_trigger;
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CharDriverState *chr; |
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qemu_irq irq; |
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enum pl011_type type;
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} pl011_state; |
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#define PL011_INT_TX 0x20 |
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#define PL011_INT_RX 0x10 |
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#define PL011_FLAG_TXFE 0x80 |
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#define PL011_FLAG_RXFF 0x40 |
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#define PL011_FLAG_TXFF 0x20 |
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#define PL011_FLAG_RXFE 0x10 |
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static const unsigned char pl011_id[2][8] = { |
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{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_ARM */ |
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{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_LUMINARY */ |
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}; |
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static void pl011_update(pl011_state *s) |
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{ |
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uint32_t flags; |
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flags = s->int_level & s->int_enabled; |
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qemu_set_irq(s->irq, flags != 0);
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} |
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static uint32_t pl011_read(void *opaque, target_phys_addr_t offset) |
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{ |
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pl011_state *s = (pl011_state *)opaque; |
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uint32_t c; |
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offset -= s->base; |
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if (offset >= 0xfe0 && offset < 0x1000) { |
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return pl011_id[s->type][(offset - 0xfe0) >> 2]; |
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} |
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switch (offset >> 2) { |
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case 0: /* UARTDR */ |
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s->flags &= ~PL011_FLAG_RXFF; |
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c = s->read_fifo[s->read_pos]; |
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if (s->read_count > 0) { |
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s->read_count--; |
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if (++s->read_pos == 16) |
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s->read_pos = 0;
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} |
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if (s->read_count == 0) { |
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s->flags |= PL011_FLAG_RXFE; |
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} |
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if (s->read_count == s->read_trigger - 1) |
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s->int_level &= ~ PL011_INT_RX; |
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pl011_update(s); |
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qemu_chr_accept_input(s->chr); |
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return c;
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case 1: /* UARTCR */ |
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return 0; |
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case 6: /* UARTFR */ |
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return s->flags;
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case 8: /* UARTILPR */ |
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return s->ilpr;
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case 9: /* UARTIBRD */ |
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return s->ibrd;
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case 10: /* UARTFBRD */ |
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return s->fbrd;
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case 11: /* UARTLCR_H */ |
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return s->lcr;
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case 12: /* UARTCR */ |
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return s->cr;
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case 13: /* UARTIFLS */ |
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return s->ifl;
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case 14: /* UARTIMSC */ |
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return s->int_enabled;
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case 15: /* UARTRIS */ |
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return s->int_level;
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case 16: /* UARTMIS */ |
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return s->int_level & s->int_enabled;
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case 18: /* UARTDMACR */ |
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return s->dmacr;
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default:
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cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset); |
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return 0; |
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} |
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} |
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static void pl011_set_read_trigger(pl011_state *s) |
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{ |
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#if 0
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/* The docs say the RX interrupt is triggered when the FIFO exceeds
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the threshold. However linux only reads the FIFO in response to an
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interrupt. Triggering the interrupt when the FIFO is non-empty seems
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to make things work. */
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if (s->lcr & 0x10)
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s->read_trigger = (s->ifl >> 1) & 0x1c;
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else
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#endif
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s->read_trigger = 1;
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} |
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static void pl011_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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pl011_state *s = (pl011_state *)opaque; |
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unsigned char ch; |
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offset -= s->base; |
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switch (offset >> 2) { |
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case 0: /* UARTDR */ |
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/* ??? Check if transmitter is enabled. */
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ch = value; |
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if (s->chr)
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qemu_chr_write(s->chr, &ch, 1);
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s->int_level |= PL011_INT_TX; |
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pl011_update(s); |
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break;
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case 1: /* UARTCR */ |
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s->cr = value; |
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break;
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case 6: /* UARTFR */ |
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/* Writes to Flag register are ignored. */
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break;
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case 8: /* UARTUARTILPR */ |
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s->ilpr = value; |
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break;
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case 9: /* UARTIBRD */ |
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s->ibrd = value; |
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break;
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case 10: /* UARTFBRD */ |
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s->fbrd = value; |
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break;
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case 11: /* UARTLCR_H */ |
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s->lcr = value; |
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pl011_set_read_trigger(s); |
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break;
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case 12: /* UARTCR */ |
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/* ??? Need to implement the enable and loopback bits. */
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s->cr = value; |
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break;
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case 13: /* UARTIFS */ |
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s->ifl = value; |
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pl011_set_read_trigger(s); |
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break;
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case 14: /* UARTIMSC */ |
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s->int_enabled = value; |
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pl011_update(s); |
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break;
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case 17: /* UARTICR */ |
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s->int_level &= ~value; |
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pl011_update(s); |
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break;
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case 18: /* UARTDMACR */ |
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s->dmacr = value; |
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if (value & 3) |
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cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
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break;
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default:
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cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset); |
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} |
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} |
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static int pl011_can_receive(void *opaque) |
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{ |
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pl011_state *s = (pl011_state *)opaque; |
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if (s->lcr & 0x10) |
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return s->read_count < 16; |
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else
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return s->read_count < 1; |
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} |
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static void pl011_put_fifo(void *opaque, uint32_t value) |
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{ |
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pl011_state *s = (pl011_state *)opaque; |
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int slot;
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slot = s->read_pos + s->read_count; |
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if (slot >= 16) |
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slot -= 16;
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s->read_fifo[slot] = value; |
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s->read_count++; |
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s->flags &= ~PL011_FLAG_RXFE; |
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if (s->cr & 0x10 || s->read_count == 16) { |
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s->flags |= PL011_FLAG_RXFF; |
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} |
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if (s->read_count == s->read_trigger) {
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s->int_level |= PL011_INT_RX; |
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pl011_update(s); |
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} |
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} |
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static void pl011_receive(void *opaque, const uint8_t *buf, int size) |
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{ |
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pl011_put_fifo(opaque, *buf); |
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} |
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static void pl011_event(void *opaque, int event) |
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{ |
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if (event == CHR_EVENT_BREAK)
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pl011_put_fifo(opaque, 0x400);
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} |
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static CPUReadMemoryFunc *pl011_readfn[] = {
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pl011_read, |
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pl011_read, |
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pl011_read |
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}; |
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static CPUWriteMemoryFunc *pl011_writefn[] = {
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pl011_write, |
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pl011_write, |
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pl011_write |
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}; |
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static void pl011_save(QEMUFile *f, void *opaque) |
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{ |
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pl011_state *s = (pl011_state *)opaque; |
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int i;
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qemu_put_be32(f, s->readbuff); |
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qemu_put_be32(f, s->flags); |
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qemu_put_be32(f, s->lcr); |
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qemu_put_be32(f, s->cr); |
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qemu_put_be32(f, s->dmacr); |
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qemu_put_be32(f, s->int_enabled); |
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qemu_put_be32(f, s->int_level); |
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for (i = 0; i < 16; i++) |
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qemu_put_be32(f, s->read_fifo[i]); |
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qemu_put_be32(f, s->ilpr); |
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qemu_put_be32(f, s->ibrd); |
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qemu_put_be32(f, s->fbrd); |
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qemu_put_be32(f, s->ifl); |
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qemu_put_be32(f, s->read_pos); |
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qemu_put_be32(f, s->read_count); |
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qemu_put_be32(f, s->read_trigger); |
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} |
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static int pl011_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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pl011_state *s = (pl011_state *)opaque; |
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int i;
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if (version_id != 1) |
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return -EINVAL;
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s->readbuff = qemu_get_be32(f); |
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s->flags = qemu_get_be32(f); |
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s->lcr = qemu_get_be32(f); |
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s->cr = qemu_get_be32(f); |
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s->dmacr = qemu_get_be32(f); |
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s->int_enabled = qemu_get_be32(f); |
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s->int_level = qemu_get_be32(f); |
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for (i = 0; i < 16; i++) |
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s->read_fifo[i] = qemu_get_be32(f); |
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s->ilpr = qemu_get_be32(f); |
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s->ibrd = qemu_get_be32(f); |
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s->fbrd = qemu_get_be32(f); |
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s->ifl = qemu_get_be32(f); |
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s->read_pos = qemu_get_be32(f); |
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s->read_count = qemu_get_be32(f); |
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s->read_trigger = qemu_get_be32(f); |
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return 0; |
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} |
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void pl011_init(uint32_t base, qemu_irq irq,
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CharDriverState *chr, enum pl011_type type)
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{ |
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int iomemtype;
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pl011_state *s; |
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s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
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iomemtype = cpu_register_io_memory(0, pl011_readfn,
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pl011_writefn, s); |
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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s->base = base; |
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s->irq = irq; |
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s->type = type; |
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s->chr = chr; |
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s->read_trigger = 1;
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s->ifl = 0x12;
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s->cr = 0x300;
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s->flags = 0x90;
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if (chr){
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qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive, |
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pl011_event, s); |
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} |
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register_savevm("pl011_uart", -1, 1, pl011_save, pl011_load, s); |
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} |
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