root / hw / axis_dev88.c @ 21eea4b3
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1 | 10c144e2 | edgar_igl | /*
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2 | 10c144e2 | edgar_igl | * QEMU model for the AXIS devboard 88.
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3 | 10c144e2 | edgar_igl | *
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4 | 10c144e2 | edgar_igl | * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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5 | 10c144e2 | edgar_igl | *
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6 | 10c144e2 | edgar_igl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 10c144e2 | edgar_igl | * of this software and associated documentation files (the "Software"), to deal
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8 | 10c144e2 | edgar_igl | * in the Software without restriction, including without limitation the rights
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9 | 10c144e2 | edgar_igl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 10c144e2 | edgar_igl | * copies of the Software, and to permit persons to whom the Software is
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11 | 10c144e2 | edgar_igl | * furnished to do so, subject to the following conditions:
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12 | 10c144e2 | edgar_igl | *
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13 | 10c144e2 | edgar_igl | * The above copyright notice and this permission notice shall be included in
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14 | 10c144e2 | edgar_igl | * all copies or substantial portions of the Software.
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15 | 10c144e2 | edgar_igl | *
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16 | 10c144e2 | edgar_igl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 10c144e2 | edgar_igl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 10c144e2 | edgar_igl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 10c144e2 | edgar_igl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 10c144e2 | edgar_igl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 10c144e2 | edgar_igl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 10c144e2 | edgar_igl | * THE SOFTWARE.
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23 | 10c144e2 | edgar_igl | */
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24 | 4b816985 | Edgar E. Iglesias | |
25 | 4b816985 | Edgar E. Iglesias | #include "sysbus.h" |
26 | 10c144e2 | edgar_igl | #include "net.h" |
27 | 10c144e2 | edgar_igl | #include "flash.h" |
28 | 10c144e2 | edgar_igl | #include "boards.h" |
29 | 4b816985 | Edgar E. Iglesias | #include "sysemu.h" |
30 | 10c144e2 | edgar_igl | #include "etraxfs.h" |
31 | ca20cf32 | Blue Swirl | #include "loader.h" |
32 | ca20cf32 | Blue Swirl | #include "elf.h" |
33 | 10c144e2 | edgar_igl | |
34 | 10c144e2 | edgar_igl | #define D(x)
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35 | 10c144e2 | edgar_igl | #define DNAND(x)
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36 | 10c144e2 | edgar_igl | |
37 | 10c144e2 | edgar_igl | struct nand_state_t
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38 | 10c144e2 | edgar_igl | { |
39 | bc24a225 | Paul Brook | NANDFlashState *nand; |
40 | 10c144e2 | edgar_igl | unsigned int rdy:1; |
41 | 10c144e2 | edgar_igl | unsigned int ale:1; |
42 | 10c144e2 | edgar_igl | unsigned int cle:1; |
43 | 10c144e2 | edgar_igl | unsigned int ce:1; |
44 | 10c144e2 | edgar_igl | }; |
45 | 10c144e2 | edgar_igl | |
46 | 10c144e2 | edgar_igl | static struct nand_state_t nand_state; |
47 | c227f099 | Anthony Liguori | static uint32_t nand_readl (void *opaque, target_phys_addr_t addr) |
48 | 10c144e2 | edgar_igl | { |
49 | 10c144e2 | edgar_igl | struct nand_state_t *s = opaque;
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50 | 10c144e2 | edgar_igl | uint32_t r; |
51 | 10c144e2 | edgar_igl | int rdy;
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52 | 10c144e2 | edgar_igl | |
53 | 10c144e2 | edgar_igl | r = nand_getio(s->nand); |
54 | 10c144e2 | edgar_igl | nand_getpins(s->nand, &rdy); |
55 | 10c144e2 | edgar_igl | s->rdy = rdy; |
56 | 10c144e2 | edgar_igl | |
57 | 10c144e2 | edgar_igl | DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
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58 | 10c144e2 | edgar_igl | return r;
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59 | 10c144e2 | edgar_igl | } |
60 | 10c144e2 | edgar_igl | |
61 | 10c144e2 | edgar_igl | static void |
62 | c227f099 | Anthony Liguori | nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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63 | 10c144e2 | edgar_igl | { |
64 | 10c144e2 | edgar_igl | struct nand_state_t *s = opaque;
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65 | 10c144e2 | edgar_igl | int rdy;
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66 | 10c144e2 | edgar_igl | |
67 | 10c144e2 | edgar_igl | DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
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68 | 10c144e2 | edgar_igl | nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0); |
69 | 10c144e2 | edgar_igl | nand_setio(s->nand, value); |
70 | 10c144e2 | edgar_igl | nand_getpins(s->nand, &rdy); |
71 | 10c144e2 | edgar_igl | s->rdy = rdy; |
72 | 10c144e2 | edgar_igl | } |
73 | 10c144e2 | edgar_igl | |
74 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const nand_read[] = { |
75 | 10c144e2 | edgar_igl | &nand_readl, |
76 | 10c144e2 | edgar_igl | &nand_readl, |
77 | 10c144e2 | edgar_igl | &nand_readl, |
78 | 10c144e2 | edgar_igl | }; |
79 | 10c144e2 | edgar_igl | |
80 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const nand_write[] = { |
81 | 10c144e2 | edgar_igl | &nand_writel, |
82 | 10c144e2 | edgar_igl | &nand_writel, |
83 | 10c144e2 | edgar_igl | &nand_writel, |
84 | 10c144e2 | edgar_igl | }; |
85 | 10c144e2 | edgar_igl | |
86 | 4a1e6bea | edgar_igl | |
87 | 4a1e6bea | edgar_igl | struct tempsensor_t
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88 | 4a1e6bea | edgar_igl | { |
89 | 4a1e6bea | edgar_igl | unsigned int shiftreg; |
90 | 4a1e6bea | edgar_igl | unsigned int count; |
91 | 4a1e6bea | edgar_igl | enum {
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92 | 4a1e6bea | edgar_igl | ST_OUT, ST_IN, ST_Z |
93 | 4a1e6bea | edgar_igl | } state; |
94 | 4a1e6bea | edgar_igl | |
95 | 4a1e6bea | edgar_igl | uint16_t regs[3];
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96 | 4a1e6bea | edgar_igl | }; |
97 | 4a1e6bea | edgar_igl | |
98 | 4a1e6bea | edgar_igl | static void tempsensor_clkedge(struct tempsensor_t *s, |
99 | 4a1e6bea | edgar_igl | unsigned int clk, unsigned int data_in) |
100 | 4a1e6bea | edgar_igl | { |
101 | 4a1e6bea | edgar_igl | D(printf("%s clk=%d state=%d sr=%x\n", __func__,
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102 | 4a1e6bea | edgar_igl | clk, s->state, s->shiftreg)); |
103 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
104 | 4a1e6bea | edgar_igl | s->count = 16;
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105 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
106 | 4a1e6bea | edgar_igl | } |
107 | 4a1e6bea | edgar_igl | switch (s->state) {
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108 | 4a1e6bea | edgar_igl | case ST_OUT:
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109 | 4a1e6bea | edgar_igl | /* Output reg is clocked at negedge. */
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110 | 4a1e6bea | edgar_igl | if (!clk) {
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111 | 4a1e6bea | edgar_igl | s->count--; |
112 | 4a1e6bea | edgar_igl | s->shiftreg <<= 1;
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113 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
114 | 4a1e6bea | edgar_igl | s->shiftreg = 0;
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115 | 4a1e6bea | edgar_igl | s->state = ST_IN; |
116 | 4a1e6bea | edgar_igl | s->count = 16;
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117 | 4a1e6bea | edgar_igl | } |
118 | 4a1e6bea | edgar_igl | } |
119 | 4a1e6bea | edgar_igl | break;
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120 | 4a1e6bea | edgar_igl | case ST_Z:
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121 | 4a1e6bea | edgar_igl | if (clk) {
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122 | 4a1e6bea | edgar_igl | s->count--; |
123 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
124 | 4a1e6bea | edgar_igl | s->shiftreg = 0;
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125 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
126 | 4a1e6bea | edgar_igl | s->count = 16;
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127 | 4a1e6bea | edgar_igl | } |
128 | 4a1e6bea | edgar_igl | } |
129 | 4a1e6bea | edgar_igl | break;
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130 | 4a1e6bea | edgar_igl | case ST_IN:
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131 | 4a1e6bea | edgar_igl | /* Indata is sampled at posedge. */
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132 | 4a1e6bea | edgar_igl | if (clk) {
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133 | 4a1e6bea | edgar_igl | s->count--; |
134 | 4a1e6bea | edgar_igl | s->shiftreg <<= 1;
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135 | 4a1e6bea | edgar_igl | s->shiftreg |= data_in & 1;
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136 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
137 | 4a1e6bea | edgar_igl | D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
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138 | 4a1e6bea | edgar_igl | s->regs[0] = s->shiftreg;
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139 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
140 | 4a1e6bea | edgar_igl | s->count = 16;
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141 | 4a1e6bea | edgar_igl | |
142 | 4a1e6bea | edgar_igl | if ((s->regs[0] & 0xff) == 0) { |
143 | 4a1e6bea | edgar_igl | /* 25 degrees celcius. */
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144 | 4a1e6bea | edgar_igl | s->shiftreg = 0x0b9f;
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145 | 4a1e6bea | edgar_igl | } else if ((s->regs[0] & 0xff) == 0xff) { |
146 | 4a1e6bea | edgar_igl | /* Sensor ID, 0x8100 LM70. */
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147 | 4a1e6bea | edgar_igl | s->shiftreg = 0x8100;
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148 | 4a1e6bea | edgar_igl | } else
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149 | 4a1e6bea | edgar_igl | printf("Invalid tempsens state %x\n", s->regs[0]); |
150 | 4a1e6bea | edgar_igl | } |
151 | 4a1e6bea | edgar_igl | } |
152 | 4a1e6bea | edgar_igl | break;
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153 | 4a1e6bea | edgar_igl | } |
154 | 4a1e6bea | edgar_igl | } |
155 | 4a1e6bea | edgar_igl | |
156 | 4a1e6bea | edgar_igl | |
157 | 4a1e6bea | edgar_igl | #define RW_PA_DOUT 0x00 |
158 | 4a1e6bea | edgar_igl | #define R_PA_DIN 0x01 |
159 | 4a1e6bea | edgar_igl | #define RW_PA_OE 0x02 |
160 | 4a1e6bea | edgar_igl | #define RW_PD_DOUT 0x10 |
161 | 4a1e6bea | edgar_igl | #define R_PD_DIN 0x11 |
162 | 4a1e6bea | edgar_igl | #define RW_PD_OE 0x12 |
163 | 4a1e6bea | edgar_igl | |
164 | 4a1e6bea | edgar_igl | static struct gpio_state_t |
165 | 10c144e2 | edgar_igl | { |
166 | 10c144e2 | edgar_igl | struct nand_state_t *nand;
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167 | 4a1e6bea | edgar_igl | struct tempsensor_t tempsensor;
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168 | 10c144e2 | edgar_igl | uint32_t regs[0x5c / 4]; |
169 | 10c144e2 | edgar_igl | } gpio_state; |
170 | 10c144e2 | edgar_igl | |
171 | c227f099 | Anthony Liguori | static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) |
172 | 10c144e2 | edgar_igl | { |
173 | 10c144e2 | edgar_igl | struct gpio_state_t *s = opaque;
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174 | 10c144e2 | edgar_igl | uint32_t r = 0;
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175 | 10c144e2 | edgar_igl | |
176 | 10c144e2 | edgar_igl | addr >>= 2;
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177 | 10c144e2 | edgar_igl | switch (addr)
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178 | 10c144e2 | edgar_igl | { |
179 | 10c144e2 | edgar_igl | case R_PA_DIN:
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180 | 10c144e2 | edgar_igl | r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE]; |
181 | 10c144e2 | edgar_igl | |
182 | 10c144e2 | edgar_igl | /* Encode pins from the nand. */
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183 | 10c144e2 | edgar_igl | r |= s->nand->rdy << 7;
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184 | 10c144e2 | edgar_igl | break;
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185 | 4a1e6bea | edgar_igl | case R_PD_DIN:
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186 | 4a1e6bea | edgar_igl | r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE]; |
187 | 4a1e6bea | edgar_igl | |
188 | 4a1e6bea | edgar_igl | /* Encode temp sensor pins. */
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189 | 4a1e6bea | edgar_igl | r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4; |
190 | 4a1e6bea | edgar_igl | break;
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191 | 4a1e6bea | edgar_igl | |
192 | 10c144e2 | edgar_igl | default:
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193 | 10c144e2 | edgar_igl | r = s->regs[addr]; |
194 | 10c144e2 | edgar_igl | break;
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195 | 10c144e2 | edgar_igl | } |
196 | 10c144e2 | edgar_igl | return r;
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197 | 10c144e2 | edgar_igl | D(printf("%s %x=%x\n", __func__, addr, r));
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198 | 10c144e2 | edgar_igl | } |
199 | 10c144e2 | edgar_igl | |
200 | c227f099 | Anthony Liguori | static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
201 | 10c144e2 | edgar_igl | { |
202 | 10c144e2 | edgar_igl | struct gpio_state_t *s = opaque;
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203 | 10c144e2 | edgar_igl | D(printf("%s %x=%x\n", __func__, addr, value));
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204 | 10c144e2 | edgar_igl | |
205 | 10c144e2 | edgar_igl | addr >>= 2;
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206 | 10c144e2 | edgar_igl | switch (addr)
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207 | 10c144e2 | edgar_igl | { |
208 | 10c144e2 | edgar_igl | case RW_PA_DOUT:
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209 | 10c144e2 | edgar_igl | /* Decode nand pins. */
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210 | 10c144e2 | edgar_igl | s->nand->ale = !!(value & (1 << 6)); |
211 | 10c144e2 | edgar_igl | s->nand->cle = !!(value & (1 << 5)); |
212 | 10c144e2 | edgar_igl | s->nand->ce = !!(value & (1 << 4)); |
213 | 10c144e2 | edgar_igl | |
214 | 10c144e2 | edgar_igl | s->regs[addr] = value; |
215 | 10c144e2 | edgar_igl | break;
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216 | 4a1e6bea | edgar_igl | |
217 | 4a1e6bea | edgar_igl | case RW_PD_DOUT:
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218 | 4a1e6bea | edgar_igl | /* Temp sensor clk. */
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219 | 4a1e6bea | edgar_igl | if ((s->regs[addr] ^ value) & 2) |
220 | 4a1e6bea | edgar_igl | tempsensor_clkedge(&s->tempsensor, !!(value & 2),
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221 | 4a1e6bea | edgar_igl | !!(value & 16));
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222 | 4a1e6bea | edgar_igl | s->regs[addr] = value; |
223 | 4a1e6bea | edgar_igl | break;
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224 | 4a1e6bea | edgar_igl | |
225 | 10c144e2 | edgar_igl | default:
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226 | 10c144e2 | edgar_igl | s->regs[addr] = value; |
227 | 10c144e2 | edgar_igl | break;
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228 | 10c144e2 | edgar_igl | } |
229 | 10c144e2 | edgar_igl | } |
230 | 10c144e2 | edgar_igl | |
231 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const gpio_read[] = { |
232 | 10c144e2 | edgar_igl | NULL, NULL, |
233 | 10c144e2 | edgar_igl | &gpio_readl, |
234 | 10c144e2 | edgar_igl | }; |
235 | 10c144e2 | edgar_igl | |
236 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const gpio_write[] = { |
237 | 10c144e2 | edgar_igl | NULL, NULL, |
238 | 10c144e2 | edgar_igl | &gpio_writel, |
239 | 10c144e2 | edgar_igl | }; |
240 | 10c144e2 | edgar_igl | |
241 | 10c144e2 | edgar_igl | #define INTMEM_SIZE (128 * 1024) |
242 | 10c144e2 | edgar_igl | |
243 | 10c144e2 | edgar_igl | static uint32_t bootstrap_pc;
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244 | 10c144e2 | edgar_igl | static void main_cpu_reset(void *opaque) |
245 | 10c144e2 | edgar_igl | { |
246 | 10c144e2 | edgar_igl | CPUState *env = opaque; |
247 | 10c144e2 | edgar_igl | cpu_reset(env); |
248 | 10c144e2 | edgar_igl | |
249 | 10c144e2 | edgar_igl | env->pc = bootstrap_pc; |
250 | 10c144e2 | edgar_igl | } |
251 | 10c144e2 | edgar_igl | |
252 | 10c144e2 | edgar_igl | static
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253 | c227f099 | Anthony Liguori | void axisdev88_init (ram_addr_t ram_size,
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254 | ef998233 | edgar_igl | const char *boot_device, |
255 | 10c144e2 | edgar_igl | const char *kernel_filename, const char *kernel_cmdline, |
256 | 10c144e2 | edgar_igl | const char *initrd_filename, const char *cpu_model) |
257 | 10c144e2 | edgar_igl | { |
258 | 10c144e2 | edgar_igl | CPUState *env; |
259 | fd6dc90b | Edgar E. Iglesias | DeviceState *dev; |
260 | fd6dc90b | Edgar E. Iglesias | SysBusDevice *s; |
261 | fd6dc90b | Edgar E. Iglesias | qemu_irq irq[30], nmi[2], *cpu_irq; |
262 | 10c144e2 | edgar_igl | void *etraxfs_dmac;
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263 | 10c144e2 | edgar_igl | struct etraxfs_dma_client *eth[2] = {NULL, NULL}; |
264 | 10c144e2 | edgar_igl | int kernel_size;
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265 | 10c144e2 | edgar_igl | int i;
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266 | 10c144e2 | edgar_igl | int nand_regs;
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267 | 10c144e2 | edgar_igl | int gpio_regs;
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268 | c227f099 | Anthony Liguori | ram_addr_t phys_ram; |
269 | c227f099 | Anthony Liguori | ram_addr_t phys_intmem; |
270 | 10c144e2 | edgar_igl | |
271 | 10c144e2 | edgar_igl | /* init CPUs */
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272 | 10c144e2 | edgar_igl | if (cpu_model == NULL) { |
273 | 10c144e2 | edgar_igl | cpu_model = "crisv32";
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274 | 10c144e2 | edgar_igl | } |
275 | 10c144e2 | edgar_igl | env = cpu_init(cpu_model); |
276 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, env); |
277 | 10c144e2 | edgar_igl | |
278 | 10c144e2 | edgar_igl | /* allocate RAM */
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279 | 10c144e2 | edgar_igl | phys_ram = qemu_ram_alloc(ram_size); |
280 | 10c144e2 | edgar_igl | cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
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281 | 10c144e2 | edgar_igl | |
282 | 10c144e2 | edgar_igl | /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
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283 | 10c144e2 | edgar_igl | internal memory. */
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284 | 10c144e2 | edgar_igl | phys_intmem = qemu_ram_alloc(INTMEM_SIZE); |
285 | 10c144e2 | edgar_igl | cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
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286 | 10c144e2 | edgar_igl | phys_intmem | IO_MEM_RAM); |
287 | 10c144e2 | edgar_igl | |
288 | 10c144e2 | edgar_igl | |
289 | 10c144e2 | edgar_igl | /* Attach a NAND flash to CS1. */
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290 | 4a1e6bea | edgar_igl | nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
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291 | 1eed09cb | Avi Kivity | nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state); |
292 | 10c144e2 | edgar_igl | cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); |
293 | 10c144e2 | edgar_igl | |
294 | 10c144e2 | edgar_igl | gpio_state.nand = &nand_state; |
295 | 1eed09cb | Avi Kivity | gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state); |
296 | 4a1e6bea | edgar_igl | cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); |
297 | 10c144e2 | edgar_igl | |
298 | 10c144e2 | edgar_igl | |
299 | fd6dc90b | Edgar E. Iglesias | cpu_irq = cris_pic_init_cpu(env); |
300 | fd6dc90b | Edgar E. Iglesias | dev = qdev_create(NULL, "etraxfs,pic"); |
301 | fd6dc90b | Edgar E. Iglesias | /* FIXME: Is there a proper way to signal vectors to the CPU core? */
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302 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
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303 | fd6dc90b | Edgar E. Iglesias | qdev_init(dev); |
304 | fd6dc90b | Edgar E. Iglesias | s = sysbus_from_qdev(dev); |
305 | fd6dc90b | Edgar E. Iglesias | sysbus_mmio_map(s, 0, 0x3001c000); |
306 | fd6dc90b | Edgar E. Iglesias | sysbus_connect_irq(s, 0, cpu_irq[0]); |
307 | fd6dc90b | Edgar E. Iglesias | sysbus_connect_irq(s, 1, cpu_irq[1]); |
308 | fd6dc90b | Edgar E. Iglesias | for (i = 0; i < 30; i++) { |
309 | 067a3ddc | Paul Brook | irq[i] = qdev_get_gpio_in(dev, i); |
310 | fd6dc90b | Edgar E. Iglesias | } |
311 | 067a3ddc | Paul Brook | nmi[0] = qdev_get_gpio_in(dev, 30); |
312 | 067a3ddc | Paul Brook | nmi[1] = qdev_get_gpio_in(dev, 31); |
313 | 73cfd29f | Edgar E. Iglesias | |
314 | ba494313 | Edgar E. Iglesias | etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10); |
315 | 10c144e2 | edgar_igl | for (i = 0; i < 10; i++) { |
316 | 10c144e2 | edgar_igl | /* On ETRAX, odd numbered channels are inputs. */
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317 | 73cfd29f | Edgar E. Iglesias | etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1); |
318 | 10c144e2 | edgar_igl | } |
319 | 10c144e2 | edgar_igl | |
320 | 10c144e2 | edgar_igl | /* Add the two ethernet blocks. */
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321 | ba494313 | Edgar E. Iglesias | eth[0] = etraxfs_eth_init(&nd_table[0], 0x30034000, 1); |
322 | 0ae18cee | aliguori | if (nb_nics > 1) |
323 | ba494313 | Edgar E. Iglesias | eth[1] = etraxfs_eth_init(&nd_table[1], 0x30036000, 2); |
324 | 10c144e2 | edgar_igl | |
325 | 10c144e2 | edgar_igl | /* The DMA Connector block is missing, hardwire things for now. */
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326 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]); |
327 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1); |
328 | 10c144e2 | edgar_igl | if (eth[1]) { |
329 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]); |
330 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1); |
331 | 10c144e2 | edgar_igl | } |
332 | 10c144e2 | edgar_igl | |
333 | 10c144e2 | edgar_igl | /* 2 timers. */
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334 | 3b1fd90e | Edgar E. Iglesias | sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL); |
335 | 3b1fd90e | Edgar E. Iglesias | sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL); |
336 | 10c144e2 | edgar_igl | |
337 | 10c144e2 | edgar_igl | for (i = 0; i < 4; i++) { |
338 | 4b816985 | Edgar E. Iglesias | sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000, |
339 | 3b1fd90e | Edgar E. Iglesias | irq[0x14 + i]);
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340 | 10c144e2 | edgar_igl | } |
341 | 10c144e2 | edgar_igl | |
342 | 10c144e2 | edgar_igl | if (kernel_filename) {
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343 | 10c144e2 | edgar_igl | uint64_t entry, high; |
344 | 10c144e2 | edgar_igl | int kcmdline_len;
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345 | 10c144e2 | edgar_igl | |
346 | 10c144e2 | edgar_igl | /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
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347 | 10c144e2 | edgar_igl | devboard SDK. */
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348 | 10c144e2 | edgar_igl | kernel_size = load_elf(kernel_filename, -0x80000000LL,
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349 | ca20cf32 | Blue Swirl | &entry, NULL, &high, 0, ELF_MACHINE, 0); |
350 | 10c144e2 | edgar_igl | bootstrap_pc = entry; |
351 | 10c144e2 | edgar_igl | if (kernel_size < 0) { |
352 | 10c144e2 | edgar_igl | /* Takes a kimage from the axis devboard SDK. */
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353 | dcac9679 | pbrook | kernel_size = load_image_targphys(kernel_filename, 0x40004000,
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354 | dcac9679 | pbrook | ram_size); |
355 | 10c144e2 | edgar_igl | bootstrap_pc = 0x40004000;
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356 | 10c144e2 | edgar_igl | env->regs[9] = 0x40004000 + kernel_size; |
357 | 10c144e2 | edgar_igl | } |
358 | 10c144e2 | edgar_igl | env->regs[8] = 0x56902387; /* RAM init magic. */ |
359 | 10c144e2 | edgar_igl | |
360 | 10c144e2 | edgar_igl | if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) {
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361 | 10c144e2 | edgar_igl | if (kcmdline_len > 256) { |
362 | 10c144e2 | edgar_igl | fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n");
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363 | 10c144e2 | edgar_igl | exit(1);
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364 | 10c144e2 | edgar_igl | } |
365 | 10c144e2 | edgar_igl | /* Let the kernel know we are modifying the cmdline. */
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366 | 10c144e2 | edgar_igl | env->regs[10] = 0x87109563; |
367 | d33fd9d1 | Edgar E. Iglesias | env->regs[11] = 0x40000000; |
368 | d33fd9d1 | Edgar E. Iglesias | pstrcpy_targphys(env->regs[11], 256, kernel_cmdline); |
369 | 10c144e2 | edgar_igl | } |
370 | 10c144e2 | edgar_igl | } |
371 | 10c144e2 | edgar_igl | env->pc = bootstrap_pc; |
372 | 10c144e2 | edgar_igl | |
373 | 10c144e2 | edgar_igl | printf ("pc =%x\n", env->pc);
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374 | 10c144e2 | edgar_igl | printf ("ram size =%ld\n", ram_size);
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375 | 10c144e2 | edgar_igl | } |
376 | 10c144e2 | edgar_igl | |
377 | f80f9ec9 | Anthony Liguori | static QEMUMachine axisdev88_machine = {
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378 | 10c144e2 | edgar_igl | .name = "axis-dev88",
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379 | 10c144e2 | edgar_igl | .desc = "AXIS devboard 88",
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380 | 10c144e2 | edgar_igl | .init = axisdev88_init, |
381 | 10c144e2 | edgar_igl | }; |
382 | f80f9ec9 | Anthony Liguori | |
383 | f80f9ec9 | Anthony Liguori | static void axisdev88_machine_init(void) |
384 | f80f9ec9 | Anthony Liguori | { |
385 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&axisdev88_machine); |
386 | f80f9ec9 | Anthony Liguori | } |
387 | f80f9ec9 | Anthony Liguori | |
388 | f80f9ec9 | Anthony Liguori | machine_init(axisdev88_machine_init); |