Revision 2206d2a6 hw/mpcore.c

b/hw/mpcore.c
41 41 
{
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    mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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    int id;
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    offset &= 0xfff;
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    offset &= 0xff;
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    if (offset < 0x100) {
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        /* SCU */
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        switch (offset) {
......
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        default:
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            goto bad_reg;
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        }
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    } else if (offset < 0x600) {
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        /* Interrupt controller.  */
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        if (offset < 0x200) {
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            id = gic_get_current_cpu();
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        } else {
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            id = (offset - 0x200) >> 8;
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            if (id >= s->num_cpu) {
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                return 0;
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            }
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        }
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        return gic_cpu_read(&s->gic, id, offset & 0xff);
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    }
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bad_reg:
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    hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
......
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                              uint64_t value, unsigned size)
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{
80 69 
    mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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    int id;
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    offset &= 0xfff;
70 
    offset &= 0xff;
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    if (offset < 0x100) {
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        /* SCU */
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        switch (offset) {
......
92 80 
        default:
93 81 
            goto bad_reg;
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        }
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    } else if (offset < 0x600) {
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        /* Interrupt controller.  */
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        if (offset < 0x200) {
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            id = gic_get_current_cpu();
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        } else {
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            id = (offset - 0x200) >> 8;
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        }
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        if (id < s->num_cpu) {
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            gic_cpu_write(&s->gic, id, offset & 0xff, value);
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        }
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    }
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    return;
107 85 
bad_reg:
......
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    SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
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    memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
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    memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv",
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                          0x1000);
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                          0x100);
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    memory_region_add_subregion(&s->container, 0, &s->iomem);
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    /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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     * at 0x200, 0x300...
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     */
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    for (i = 0; i < (s->num_cpu + 1); i++) {
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        target_phys_addr_t offset = 0x100 + (i * 0x100);
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        memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]);
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    }
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    /* Add the regions for timer and watchdog for "current CPU" and
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     * for each specific CPU.
136 121 
     */

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