Revision 22478e79
| b/target-arm/helper.c | ||
|---|---|---|
| 64 | 64 |
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; |
| 65 | 65 |
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; |
| 66 | 66 |
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); |
| 67 |
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
|
|
| 67 |
memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
|
|
| 68 | 68 |
env->cp15.c0_cachetype = 0x1dd20d2; |
| 69 | 69 |
break; |
| 70 | 70 |
case ARM_CPUID_ARM11MPCORE: |
| ... | ... | |
| 76 | 76 |
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; |
| 77 | 77 |
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; |
| 78 | 78 |
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); |
| 79 |
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
|
|
| 79 |
memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
|
|
| 80 | 80 |
env->cp15.c0_cachetype = 0x1dd20d2; |
| 81 | 81 |
break; |
| 82 | 82 |
case ARM_CPUID_CORTEXA8: |
| ... | ... | |
| 92 | 92 |
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; |
| 93 | 93 |
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; |
| 94 | 94 |
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); |
| 95 |
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
|
|
| 95 |
memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
|
|
| 96 | 96 |
env->cp15.c0_cachetype = 0x1dd20d2; |
| 97 | 97 |
break; |
| 98 | 98 |
case ARM_CPUID_CORTEXM3: |
| b/target-arm/op_helper.c | ||
|---|---|---|
| 185 | 185 |
int32_t top; |
| 186 | 186 |
uint32_t mask; |
| 187 | 187 |
|
| 188 |
shift = PARAM1; |
|
| 189 | 188 |
top = val >> shift; |
| 190 | 189 |
mask = (1u << shift) - 1; |
| 191 | 190 |
if (top > 0) {
|
| ... | ... | |
| 203 | 202 |
{
|
| 204 | 203 |
uint32_t max; |
| 205 | 204 |
|
| 206 |
shift = PARAM1; |
|
| 207 | 205 |
max = (1u << shift) - 1; |
| 208 | 206 |
if (val < 0) {
|
| 209 | 207 |
env->QF = 1; |
| b/target-arm/translate.c | ||
|---|---|---|
| 250 | 250 |
{
|
| 251 | 251 |
TCGv tmp1 = new_tmp(); |
| 252 | 252 |
TCGv tmp2 = new_tmp(); |
| 253 |
tcg_gen_ext8s_i32(tmp1, a);
|
|
| 254 |
tcg_gen_ext8s_i32(tmp2, b);
|
|
| 253 |
tcg_gen_ext16s_i32(tmp1, a);
|
|
| 254 |
tcg_gen_ext16s_i32(tmp2, b);
|
|
| 255 | 255 |
tcg_gen_mul_i32(tmp1, tmp1, tmp2); |
| 256 | 256 |
dead_tmp(tmp2); |
| 257 | 257 |
tcg_gen_sari_i32(a, a, 16); |
| ... | ... | |
| 5998 | 5998 |
gen_mulxy(tmp, tmp2, sh & 2, sh & 4); |
| 5999 | 5999 |
dead_tmp(tmp2); |
| 6000 | 6000 |
if (op1 == 2) {
|
| 6001 |
tmp = tcg_temp_new(TCG_TYPE_I64); |
|
| 6002 |
tcg_gen_ext_i32_i64(tmp, cpu_T[0]); |
|
| 6003 |
gen_addq(s, tmp, rn, rd); |
|
| 6004 |
gen_storeq_reg(s, rn, rd, tmp); |
|
| 6001 |
tmp2 = tcg_temp_new(TCG_TYPE_I64); |
|
| 6002 |
tcg_gen_ext_i32_i64(tmp2, tmp); |
|
| 6003 |
dead_tmp(tmp); |
|
| 6004 |
gen_addq(s, tmp2, rn, rd); |
|
| 6005 |
gen_storeq_reg(s, rn, rd, tmp2); |
|
| 6005 | 6006 |
} else {
|
| 6006 | 6007 |
if (op1 == 0) {
|
| 6007 | 6008 |
tmp2 = load_reg(s, rn); |
| ... | ... | |
| 6372 | 6373 |
tmp = load_reg(s, rn); |
| 6373 | 6374 |
tmp2 = load_reg(s, rm); |
| 6374 | 6375 |
shift = (insn >> 7) & 0x1f; |
| 6375 |
if (shift) |
|
| 6376 |
tcg_gen_shli_i32(tmp2, tmp2, shift); |
|
| 6377 | 6376 |
if (insn & (1 << 6)) {
|
| 6378 | 6377 |
/* pkhtb */ |
| 6378 |
if (shift == 0) |
|
| 6379 |
shift = 31; |
|
| 6380 |
tcg_gen_sari_i32(tmp2, tmp2, shift); |
|
| 6379 | 6381 |
tcg_gen_andi_i32(tmp, tmp, 0xffff0000); |
| 6380 | 6382 |
tcg_gen_ext16u_i32(tmp2, tmp2); |
| 6381 | 6383 |
} else {
|
| 6382 | 6384 |
/* pkhbt */ |
| 6385 |
if (shift) |
|
| 6386 |
tcg_gen_shli_i32(tmp2, tmp2, shift); |
|
| 6383 | 6387 |
tcg_gen_ext16u_i32(tmp, tmp); |
| 6384 | 6388 |
tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); |
| 6385 | 6389 |
} |
| 6386 | 6390 |
tcg_gen_or_i32(tmp, tmp, tmp2); |
| 6391 |
dead_tmp(tmp2); |
|
| 6387 | 6392 |
store_reg(s, rd, tmp); |
| 6388 | 6393 |
} else if ((insn & 0x00200020) == 0x00200000) {
|
| 6389 | 6394 |
/* [us]sat */ |
| ... | ... | |
| 6510 | 6515 |
tmp2 = tcg_temp_new(TCG_TYPE_I64); |
| 6511 | 6516 |
tcg_gen_ext_i32_i64(tmp2, tmp); |
| 6512 | 6517 |
dead_tmp(tmp); |
| 6513 |
gen_addq(s, tmp2, rn, rd);
|
|
| 6514 |
gen_storeq_reg(s, rn, rd, tmp2);
|
|
| 6518 |
gen_addq(s, tmp2, rd, rn);
|
|
| 6519 |
gen_storeq_reg(s, rd, rn, tmp2);
|
|
| 6515 | 6520 |
} else {
|
| 6516 | 6521 |
/* smuad, smusd, smlad, smlsd */ |
| 6517 |
if (rn != 15)
|
|
| 6522 |
if (rd != 15)
|
|
| 6518 | 6523 |
{
|
| 6519 |
tmp2 = load_reg(s, rn);
|
|
| 6524 |
tmp2 = load_reg(s, rd);
|
|
| 6520 | 6525 |
gen_helper_add_setq(tmp, tmp, tmp2); |
| 6521 | 6526 |
dead_tmp(tmp2); |
| 6522 | 6527 |
} |
| 6523 |
store_reg(s, rd, tmp);
|
|
| 6528 |
store_reg(s, rn, tmp);
|
|
| 6524 | 6529 |
} |
| 6525 | 6530 |
} |
| 6526 | 6531 |
break; |
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