root / hw / milkymist-sysctl.c @ 22486aa0
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1 | 96832424 | Michael Walle | /*
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2 | 96832424 | Michael Walle | * QEMU model of the Milkymist System Controller.
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3 | 96832424 | Michael Walle | *
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4 | 96832424 | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | 96832424 | Michael Walle | *
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6 | 96832424 | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | 96832424 | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | 96832424 | Michael Walle | * License as published by the Free Software Foundation; either
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9 | 96832424 | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | 96832424 | Michael Walle | *
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11 | 96832424 | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | 96832424 | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 96832424 | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 96832424 | Michael Walle | * Lesser General Public License for more details.
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15 | 96832424 | Michael Walle | *
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16 | 96832424 | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | 96832424 | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 96832424 | Michael Walle | *
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19 | 96832424 | Michael Walle | *
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20 | 96832424 | Michael Walle | * Specification available at:
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21 | 96832424 | Michael Walle | * http://www.milkymist.org/socdoc/sysctl.pdf
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22 | 96832424 | Michael Walle | */
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23 | 96832424 | Michael Walle | |
24 | 96832424 | Michael Walle | #include "hw.h" |
25 | 96832424 | Michael Walle | #include "sysbus.h" |
26 | 96832424 | Michael Walle | #include "sysemu.h" |
27 | 96832424 | Michael Walle | #include "trace.h" |
28 | 96832424 | Michael Walle | #include "qemu-timer.h" |
29 | 96832424 | Michael Walle | #include "qemu-error.h" |
30 | 96832424 | Michael Walle | |
31 | 96832424 | Michael Walle | enum {
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32 | 96832424 | Michael Walle | CTRL_ENABLE = (1<<0), |
33 | 96832424 | Michael Walle | CTRL_AUTORESTART = (1<<1), |
34 | 96832424 | Michael Walle | }; |
35 | 96832424 | Michael Walle | |
36 | 96832424 | Michael Walle | enum {
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37 | 96832424 | Michael Walle | ICAP_READY = (1<<0), |
38 | 96832424 | Michael Walle | }; |
39 | 96832424 | Michael Walle | |
40 | 96832424 | Michael Walle | enum {
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41 | 96832424 | Michael Walle | R_GPIO_IN = 0,
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42 | 96832424 | Michael Walle | R_GPIO_OUT, |
43 | 96832424 | Michael Walle | R_GPIO_INTEN, |
44 | 96832424 | Michael Walle | R_RESERVED0, |
45 | 96832424 | Michael Walle | R_TIMER0_CONTROL, |
46 | 96832424 | Michael Walle | R_TIMER0_COMPARE, |
47 | 96832424 | Michael Walle | R_TIMER0_COUNTER, |
48 | 96832424 | Michael Walle | R_RESERVED1, |
49 | 96832424 | Michael Walle | R_TIMER1_CONTROL, |
50 | 96832424 | Michael Walle | R_TIMER1_COMPARE, |
51 | 96832424 | Michael Walle | R_TIMER1_COUNTER, |
52 | 96832424 | Michael Walle | R_RESERVED2, |
53 | 96832424 | Michael Walle | R_RESERVED3, |
54 | 96832424 | Michael Walle | R_ICAP, |
55 | 96832424 | Michael Walle | R_CAPABILITIES, |
56 | 96832424 | Michael Walle | R_SYSTEM_ID, |
57 | 96832424 | Michael Walle | R_MAX |
58 | 96832424 | Michael Walle | }; |
59 | 96832424 | Michael Walle | |
60 | 96832424 | Michael Walle | struct MilkymistSysctlState {
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61 | 96832424 | Michael Walle | SysBusDevice busdev; |
62 | 96832424 | Michael Walle | |
63 | 96832424 | Michael Walle | QEMUBH *bh0; |
64 | 96832424 | Michael Walle | QEMUBH *bh1; |
65 | 96832424 | Michael Walle | ptimer_state *ptimer0; |
66 | 96832424 | Michael Walle | ptimer_state *ptimer1; |
67 | 96832424 | Michael Walle | |
68 | 96832424 | Michael Walle | uint32_t freq_hz; |
69 | 96832424 | Michael Walle | uint32_t capabilities; |
70 | 96832424 | Michael Walle | uint32_t systemid; |
71 | 96832424 | Michael Walle | uint32_t strappings; |
72 | 96832424 | Michael Walle | |
73 | 96832424 | Michael Walle | uint32_t regs[R_MAX]; |
74 | 96832424 | Michael Walle | |
75 | 96832424 | Michael Walle | qemu_irq gpio_irq; |
76 | 96832424 | Michael Walle | qemu_irq timer0_irq; |
77 | 96832424 | Michael Walle | qemu_irq timer1_irq; |
78 | 96832424 | Michael Walle | }; |
79 | 96832424 | Michael Walle | typedef struct MilkymistSysctlState MilkymistSysctlState; |
80 | 96832424 | Michael Walle | |
81 | 96832424 | Michael Walle | static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value) |
82 | 96832424 | Michael Walle | { |
83 | 96832424 | Michael Walle | trace_milkymist_sysctl_icap_write(value); |
84 | 96832424 | Michael Walle | switch (value & 0xffff) { |
85 | 96832424 | Michael Walle | case 0x000e: |
86 | 96832424 | Michael Walle | qemu_system_shutdown_request(); |
87 | 96832424 | Michael Walle | break;
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88 | 96832424 | Michael Walle | } |
89 | 96832424 | Michael Walle | } |
90 | 96832424 | Michael Walle | |
91 | 96832424 | Michael Walle | static uint32_t sysctl_read(void *opaque, target_phys_addr_t addr) |
92 | 96832424 | Michael Walle | { |
93 | 96832424 | Michael Walle | MilkymistSysctlState *s = opaque; |
94 | 96832424 | Michael Walle | uint32_t r = 0;
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95 | 96832424 | Michael Walle | |
96 | 96832424 | Michael Walle | addr >>= 2;
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97 | 96832424 | Michael Walle | switch (addr) {
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98 | 96832424 | Michael Walle | case R_TIMER0_COUNTER:
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99 | 96832424 | Michael Walle | r = (uint32_t)ptimer_get_count(s->ptimer0); |
100 | 96832424 | Michael Walle | /* milkymist timer counts up */
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101 | 96832424 | Michael Walle | r = s->regs[R_TIMER0_COMPARE] - r; |
102 | 96832424 | Michael Walle | break;
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103 | 96832424 | Michael Walle | case R_TIMER1_COUNTER:
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104 | 96832424 | Michael Walle | r = (uint32_t)ptimer_get_count(s->ptimer1); |
105 | 96832424 | Michael Walle | /* milkymist timer counts up */
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106 | 96832424 | Michael Walle | r = s->regs[R_TIMER1_COMPARE] - r; |
107 | 96832424 | Michael Walle | break;
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108 | 96832424 | Michael Walle | case R_GPIO_IN:
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109 | 96832424 | Michael Walle | case R_GPIO_OUT:
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110 | 96832424 | Michael Walle | case R_GPIO_INTEN:
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111 | 96832424 | Michael Walle | case R_TIMER0_CONTROL:
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112 | 96832424 | Michael Walle | case R_TIMER0_COMPARE:
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113 | 96832424 | Michael Walle | case R_TIMER1_CONTROL:
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114 | 96832424 | Michael Walle | case R_TIMER1_COMPARE:
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115 | 96832424 | Michael Walle | case R_ICAP:
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116 | 96832424 | Michael Walle | case R_CAPABILITIES:
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117 | 96832424 | Michael Walle | case R_SYSTEM_ID:
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118 | 96832424 | Michael Walle | r = s->regs[addr]; |
119 | 96832424 | Michael Walle | break;
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120 | 96832424 | Michael Walle | |
121 | 96832424 | Michael Walle | default:
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122 | 96832424 | Michael Walle | error_report("milkymist_sysctl: read access to unkown register 0x"
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123 | 96832424 | Michael Walle | TARGET_FMT_plx, addr << 2);
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124 | 96832424 | Michael Walle | break;
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125 | 96832424 | Michael Walle | } |
126 | 96832424 | Michael Walle | |
127 | 96832424 | Michael Walle | trace_milkymist_sysctl_memory_read(addr << 2, r);
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128 | 96832424 | Michael Walle | |
129 | 96832424 | Michael Walle | return r;
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130 | 96832424 | Michael Walle | } |
131 | 96832424 | Michael Walle | |
132 | 96832424 | Michael Walle | static void sysctl_write(void *opaque, target_phys_addr_t addr, uint32_t value) |
133 | 96832424 | Michael Walle | { |
134 | 96832424 | Michael Walle | MilkymistSysctlState *s = opaque; |
135 | 96832424 | Michael Walle | |
136 | 96832424 | Michael Walle | trace_milkymist_sysctl_memory_write(addr, value); |
137 | 96832424 | Michael Walle | |
138 | 96832424 | Michael Walle | addr >>= 2;
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139 | 96832424 | Michael Walle | switch (addr) {
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140 | 96832424 | Michael Walle | case R_GPIO_OUT:
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141 | 96832424 | Michael Walle | case R_GPIO_INTEN:
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142 | 96832424 | Michael Walle | case R_TIMER0_COUNTER:
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143 | 96832424 | Michael Walle | case R_TIMER1_COUNTER:
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144 | f3172a0e | Michael Walle | s->regs[addr] = value; |
145 | 96832424 | Michael Walle | break;
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146 | 96832424 | Michael Walle | case R_TIMER0_COMPARE:
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147 | 96832424 | Michael Walle | ptimer_set_limit(s->ptimer0, value, 0);
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148 | 96832424 | Michael Walle | s->regs[addr] = value; |
149 | 96832424 | Michael Walle | break;
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150 | 96832424 | Michael Walle | case R_TIMER1_COMPARE:
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151 | 96832424 | Michael Walle | ptimer_set_limit(s->ptimer1, value, 0);
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152 | 96832424 | Michael Walle | s->regs[addr] = value; |
153 | 96832424 | Michael Walle | break;
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154 | 96832424 | Michael Walle | case R_TIMER0_CONTROL:
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155 | 96832424 | Michael Walle | s->regs[addr] = value; |
156 | 96832424 | Michael Walle | if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
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157 | f3172a0e | Michael Walle | trace_milkymist_sysctl_start_timer0(); |
158 | f3172a0e | Michael Walle | ptimer_set_count(s->ptimer0, |
159 | f3172a0e | Michael Walle | s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]); |
160 | 96832424 | Michael Walle | ptimer_run(s->ptimer0, 0);
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161 | 96832424 | Michael Walle | } else {
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162 | f3172a0e | Michael Walle | trace_milkymist_sysctl_stop_timer0(); |
163 | 96832424 | Michael Walle | ptimer_stop(s->ptimer0); |
164 | 96832424 | Michael Walle | } |
165 | 96832424 | Michael Walle | break;
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166 | 96832424 | Michael Walle | case R_TIMER1_CONTROL:
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167 | 96832424 | Michael Walle | s->regs[addr] = value; |
168 | 96832424 | Michael Walle | if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
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169 | 96832424 | Michael Walle | trace_milkymist_sysctl_start_timer1(); |
170 | f3172a0e | Michael Walle | ptimer_set_count(s->ptimer1, |
171 | f3172a0e | Michael Walle | s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]); |
172 | 96832424 | Michael Walle | ptimer_run(s->ptimer1, 0);
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173 | 96832424 | Michael Walle | } else {
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174 | 96832424 | Michael Walle | trace_milkymist_sysctl_stop_timer1(); |
175 | 96832424 | Michael Walle | ptimer_stop(s->ptimer1); |
176 | 96832424 | Michael Walle | } |
177 | 96832424 | Michael Walle | break;
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178 | 96832424 | Michael Walle | case R_ICAP:
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179 | 96832424 | Michael Walle | sysctl_icap_write(s, value); |
180 | 96832424 | Michael Walle | break;
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181 | 96832424 | Michael Walle | case R_SYSTEM_ID:
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182 | 96832424 | Michael Walle | qemu_system_reset_request(); |
183 | 96832424 | Michael Walle | break;
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184 | 96832424 | Michael Walle | |
185 | 96832424 | Michael Walle | case R_GPIO_IN:
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186 | 96832424 | Michael Walle | case R_CAPABILITIES:
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187 | 96832424 | Michael Walle | error_report("milkymist_sysctl: write to read-only register 0x"
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188 | 96832424 | Michael Walle | TARGET_FMT_plx, addr << 2);
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189 | 96832424 | Michael Walle | break;
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190 | 96832424 | Michael Walle | |
191 | 96832424 | Michael Walle | default:
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192 | 96832424 | Michael Walle | error_report("milkymist_sysctl: write access to unkown register 0x"
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193 | 96832424 | Michael Walle | TARGET_FMT_plx, addr << 2);
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194 | 96832424 | Michael Walle | break;
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195 | 96832424 | Michael Walle | } |
196 | 96832424 | Michael Walle | } |
197 | 96832424 | Michael Walle | |
198 | 96832424 | Michael Walle | static CPUReadMemoryFunc * const sysctl_read_fn[] = { |
199 | 96832424 | Michael Walle | NULL,
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200 | 96832424 | Michael Walle | NULL,
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201 | 96832424 | Michael Walle | &sysctl_read, |
202 | 96832424 | Michael Walle | }; |
203 | 96832424 | Michael Walle | |
204 | 96832424 | Michael Walle | static CPUWriteMemoryFunc * const sysctl_write_fn[] = { |
205 | 96832424 | Michael Walle | NULL,
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206 | 96832424 | Michael Walle | NULL,
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207 | 96832424 | Michael Walle | &sysctl_write, |
208 | 96832424 | Michael Walle | }; |
209 | 96832424 | Michael Walle | |
210 | 96832424 | Michael Walle | static void timer0_hit(void *opaque) |
211 | 96832424 | Michael Walle | { |
212 | 96832424 | Michael Walle | MilkymistSysctlState *s = opaque; |
213 | 96832424 | Michael Walle | |
214 | 96832424 | Michael Walle | if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
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215 | 96832424 | Michael Walle | s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE; |
216 | 96832424 | Michael Walle | trace_milkymist_sysctl_stop_timer0(); |
217 | 96832424 | Michael Walle | ptimer_stop(s->ptimer0); |
218 | 96832424 | Michael Walle | } |
219 | 96832424 | Michael Walle | |
220 | 96832424 | Michael Walle | trace_milkymist_sysctl_pulse_irq_timer0(); |
221 | 96832424 | Michael Walle | qemu_irq_pulse(s->timer0_irq); |
222 | 96832424 | Michael Walle | } |
223 | 96832424 | Michael Walle | |
224 | 96832424 | Michael Walle | static void timer1_hit(void *opaque) |
225 | 96832424 | Michael Walle | { |
226 | 96832424 | Michael Walle | MilkymistSysctlState *s = opaque; |
227 | 96832424 | Michael Walle | |
228 | 96832424 | Michael Walle | if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
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229 | 96832424 | Michael Walle | s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE; |
230 | 96832424 | Michael Walle | trace_milkymist_sysctl_stop_timer1(); |
231 | 96832424 | Michael Walle | ptimer_stop(s->ptimer1); |
232 | 96832424 | Michael Walle | } |
233 | 96832424 | Michael Walle | |
234 | 96832424 | Michael Walle | trace_milkymist_sysctl_pulse_irq_timer1(); |
235 | 96832424 | Michael Walle | qemu_irq_pulse(s->timer1_irq); |
236 | 96832424 | Michael Walle | } |
237 | 96832424 | Michael Walle | |
238 | 96832424 | Michael Walle | static void milkymist_sysctl_reset(DeviceState *d) |
239 | 96832424 | Michael Walle | { |
240 | 96832424 | Michael Walle | MilkymistSysctlState *s = |
241 | 96832424 | Michael Walle | container_of(d, MilkymistSysctlState, busdev.qdev); |
242 | 96832424 | Michael Walle | int i;
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243 | 96832424 | Michael Walle | |
244 | 96832424 | Michael Walle | for (i = 0; i < R_MAX; i++) { |
245 | 96832424 | Michael Walle | s->regs[i] = 0;
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246 | 96832424 | Michael Walle | } |
247 | 96832424 | Michael Walle | |
248 | 96832424 | Michael Walle | ptimer_stop(s->ptimer0); |
249 | 96832424 | Michael Walle | ptimer_stop(s->ptimer1); |
250 | 96832424 | Michael Walle | |
251 | 96832424 | Michael Walle | /* defaults */
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252 | 96832424 | Michael Walle | s->regs[R_ICAP] = ICAP_READY; |
253 | 96832424 | Michael Walle | s->regs[R_SYSTEM_ID] = s->systemid; |
254 | 96832424 | Michael Walle | s->regs[R_CAPABILITIES] = s->capabilities; |
255 | 96832424 | Michael Walle | s->regs[R_GPIO_IN] = s->strappings; |
256 | 96832424 | Michael Walle | } |
257 | 96832424 | Michael Walle | |
258 | 96832424 | Michael Walle | static int milkymist_sysctl_init(SysBusDevice *dev) |
259 | 96832424 | Michael Walle | { |
260 | 96832424 | Michael Walle | MilkymistSysctlState *s = FROM_SYSBUS(typeof(*s), dev); |
261 | 96832424 | Michael Walle | int sysctl_regs;
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262 | 96832424 | Michael Walle | |
263 | 96832424 | Michael Walle | sysbus_init_irq(dev, &s->gpio_irq); |
264 | 96832424 | Michael Walle | sysbus_init_irq(dev, &s->timer0_irq); |
265 | 96832424 | Michael Walle | sysbus_init_irq(dev, &s->timer1_irq); |
266 | 96832424 | Michael Walle | |
267 | 96832424 | Michael Walle | s->bh0 = qemu_bh_new(timer0_hit, s); |
268 | 96832424 | Michael Walle | s->bh1 = qemu_bh_new(timer1_hit, s); |
269 | 96832424 | Michael Walle | s->ptimer0 = ptimer_init(s->bh0); |
270 | 96832424 | Michael Walle | s->ptimer1 = ptimer_init(s->bh1); |
271 | 96832424 | Michael Walle | ptimer_set_freq(s->ptimer0, s->freq_hz); |
272 | 96832424 | Michael Walle | ptimer_set_freq(s->ptimer1, s->freq_hz); |
273 | 96832424 | Michael Walle | |
274 | 96832424 | Michael Walle | sysctl_regs = cpu_register_io_memory(sysctl_read_fn, sysctl_write_fn, s, |
275 | 96832424 | Michael Walle | DEVICE_NATIVE_ENDIAN); |
276 | 96832424 | Michael Walle | sysbus_init_mmio(dev, R_MAX * 4, sysctl_regs);
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277 | 96832424 | Michael Walle | |
278 | 96832424 | Michael Walle | return 0; |
279 | 96832424 | Michael Walle | } |
280 | 96832424 | Michael Walle | |
281 | 96832424 | Michael Walle | static const VMStateDescription vmstate_milkymist_sysctl = { |
282 | 96832424 | Michael Walle | .name = "milkymist-sysctl",
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283 | 96832424 | Michael Walle | .version_id = 1,
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284 | 96832424 | Michael Walle | .minimum_version_id = 1,
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285 | 96832424 | Michael Walle | .minimum_version_id_old = 1,
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286 | 96832424 | Michael Walle | .fields = (VMStateField[]) { |
287 | 96832424 | Michael Walle | VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX), |
288 | 96832424 | Michael Walle | VMSTATE_PTIMER(ptimer0, MilkymistSysctlState), |
289 | 96832424 | Michael Walle | VMSTATE_PTIMER(ptimer1, MilkymistSysctlState), |
290 | 96832424 | Michael Walle | VMSTATE_END_OF_LIST() |
291 | 96832424 | Michael Walle | } |
292 | 96832424 | Michael Walle | }; |
293 | 96832424 | Michael Walle | |
294 | 96832424 | Michael Walle | static SysBusDeviceInfo milkymist_sysctl_info = {
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295 | 96832424 | Michael Walle | .init = milkymist_sysctl_init, |
296 | 96832424 | Michael Walle | .qdev.name = "milkymist-sysctl",
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297 | 96832424 | Michael Walle | .qdev.size = sizeof(MilkymistSysctlState),
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298 | 96832424 | Michael Walle | .qdev.vmsd = &vmstate_milkymist_sysctl, |
299 | 96832424 | Michael Walle | .qdev.reset = milkymist_sysctl_reset, |
300 | 96832424 | Michael Walle | .qdev.props = (Property[]) { |
301 | 96832424 | Michael Walle | DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
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302 | 96832424 | Michael Walle | freq_hz, 80000000),
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303 | 96832424 | Michael Walle | DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
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304 | 96832424 | Michael Walle | capabilities, 0x00000000),
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305 | 96832424 | Michael Walle | DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
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306 | 96832424 | Michael Walle | systemid, 0x10014d31),
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307 | 96832424 | Michael Walle | DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
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308 | 96832424 | Michael Walle | strappings, 0x00000001),
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309 | 96832424 | Michael Walle | DEFINE_PROP_END_OF_LIST(), |
310 | 96832424 | Michael Walle | } |
311 | 96832424 | Michael Walle | }; |
312 | 96832424 | Michael Walle | |
313 | 96832424 | Michael Walle | static void milkymist_sysctl_register(void) |
314 | 96832424 | Michael Walle | { |
315 | 96832424 | Michael Walle | sysbus_register_withprop(&milkymist_sysctl_info); |
316 | 96832424 | Michael Walle | } |
317 | 96832424 | Michael Walle | |
318 | 96832424 | Michael Walle | device_init(milkymist_sysctl_register) |