root / hw / slavio_intctl.c @ 22548760
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1 | e80cfcfc | bellard | /*
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2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO interrupt controller emulation
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3 | 5fafdf24 | ths | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
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9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
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12 | e80cfcfc | bellard | *
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13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
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14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
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15 | e80cfcfc | bellard | *
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16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | e80cfcfc | bellard | * THE SOFTWARE.
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23 | e80cfcfc | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "console.h" |
27 | 87ecb68b | pbrook | |
28 | e80cfcfc | bellard | //#define DEBUG_IRQ_COUNT
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29 | 66321a11 | bellard | //#define DEBUG_IRQ
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30 | 66321a11 | bellard | |
31 | 66321a11 | bellard | #ifdef DEBUG_IRQ
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32 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
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33 | 66321a11 | bellard | do { printf("IRQ: " fmt , ##args); } while (0) |
34 | 66321a11 | bellard | #else
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35 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
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36 | 66321a11 | bellard | #endif
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37 | e80cfcfc | bellard | |
38 | e80cfcfc | bellard | /*
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39 | e80cfcfc | bellard | * Registers of interrupt controller in sun4m.
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40 | e80cfcfc | bellard | *
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41 | e80cfcfc | bellard | * This is the interrupt controller part of chip STP2001 (Slave I/O), also
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42 | e80cfcfc | bellard | * produced as NCR89C105. See
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43 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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44 | e80cfcfc | bellard | *
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45 | e80cfcfc | bellard | * There is a system master controller and one for each cpu.
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46 | 5fafdf24 | ths | *
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47 | e80cfcfc | bellard | */
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48 | e80cfcfc | bellard | |
49 | e80cfcfc | bellard | #define MAX_CPUS 16 |
50 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
51 | e80cfcfc | bellard | |
52 | e80cfcfc | bellard | typedef struct SLAVIO_INTCTLState { |
53 | e80cfcfc | bellard | uint32_t intreg_pending[MAX_CPUS]; |
54 | e80cfcfc | bellard | uint32_t intregm_pending; |
55 | e80cfcfc | bellard | uint32_t intregm_disabled; |
56 | e80cfcfc | bellard | uint32_t target_cpu; |
57 | e80cfcfc | bellard | #ifdef DEBUG_IRQ_COUNT
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58 | e80cfcfc | bellard | uint64_t irq_count[32];
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59 | e80cfcfc | bellard | #endif
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60 | b3a23197 | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS]; |
61 | e0353fe2 | blueswir1 | const uint32_t *intbit_to_level;
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62 | e3a79bca | blueswir1 | uint32_t cputimer_lbit, cputimer_mbit; |
63 | b3a23197 | blueswir1 | uint32_t pil_out[MAX_CPUS]; |
64 | e80cfcfc | bellard | } SLAVIO_INTCTLState; |
65 | e80cfcfc | bellard | |
66 | e80cfcfc | bellard | #define INTCTL_MAXADDR 0xf |
67 | 5aca8c3b | blueswir1 | #define INTCTL_SIZE (INTCTL_MAXADDR + 1) |
68 | c6fdf5fc | blueswir1 | #define INTCTLM_MAXADDR 0x13 |
69 | 5aca8c3b | blueswir1 | #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1) |
70 | c6fdf5fc | blueswir1 | #define INTCTLM_MASK 0x1f |
71 | 80be36b8 | blueswir1 | #define MASTER_IRQ_MASK ~0x0fa2007f |
72 | 9a87ce9b | blueswir1 | #define MASTER_DISABLE 0x80000000 |
73 | 6341fdcb | blueswir1 | #define CPU_SOFTIRQ_MASK 0xfffe0000 |
74 | 6341fdcb | blueswir1 | #define CPU_HARDIRQ_MASK 0x0000fffe |
75 | 9a87ce9b | blueswir1 | #define CPU_IRQ_INT15_IN 0x0004000 |
76 | 9a87ce9b | blueswir1 | #define CPU_IRQ_INT15_MASK 0x80000000 |
77 | 9a87ce9b | blueswir1 | |
78 | 66321a11 | bellard | static void slavio_check_interrupts(void *opaque); |
79 | e80cfcfc | bellard | |
80 | e80cfcfc | bellard | // per-cpu interrupt controller
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81 | e80cfcfc | bellard | static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) |
82 | e80cfcfc | bellard | { |
83 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
84 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
85 | e80cfcfc | bellard | int cpu;
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86 | e80cfcfc | bellard | |
87 | e80cfcfc | bellard | cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; |
88 | e80cfcfc | bellard | saddr = (addr & INTCTL_MAXADDR) >> 2;
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89 | e80cfcfc | bellard | switch (saddr) {
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90 | e80cfcfc | bellard | case 0: |
91 | dd4131b3 | blueswir1 | ret = s->intreg_pending[cpu]; |
92 | dd4131b3 | blueswir1 | break;
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93 | e80cfcfc | bellard | default:
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94 | dd4131b3 | blueswir1 | ret = 0;
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95 | dd4131b3 | blueswir1 | break;
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96 | e80cfcfc | bellard | } |
97 | 1569fc29 | blueswir1 | DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret); |
98 | dd4131b3 | blueswir1 | |
99 | dd4131b3 | blueswir1 | return ret;
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100 | e80cfcfc | bellard | } |
101 | e80cfcfc | bellard | |
102 | e80cfcfc | bellard | static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
103 | e80cfcfc | bellard | { |
104 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
105 | e80cfcfc | bellard | uint32_t saddr; |
106 | e80cfcfc | bellard | int cpu;
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107 | e80cfcfc | bellard | |
108 | e80cfcfc | bellard | cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; |
109 | e80cfcfc | bellard | saddr = (addr & INTCTL_MAXADDR) >> 2;
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110 | 1569fc29 | blueswir1 | DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); |
111 | e80cfcfc | bellard | switch (saddr) {
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112 | e80cfcfc | bellard | case 1: // clear pending softints |
113 | 9a87ce9b | blueswir1 | if (val & CPU_IRQ_INT15_IN)
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114 | 9a87ce9b | blueswir1 | val |= CPU_IRQ_INT15_MASK; |
115 | 6341fdcb | blueswir1 | val &= CPU_SOFTIRQ_MASK; |
116 | f930d07e | blueswir1 | s->intreg_pending[cpu] &= ~val; |
117 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
118 | f930d07e | blueswir1 | DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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119 | f930d07e | blueswir1 | break;
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120 | e80cfcfc | bellard | case 2: // set softint |
121 | 6341fdcb | blueswir1 | val &= CPU_SOFTIRQ_MASK; |
122 | f930d07e | blueswir1 | s->intreg_pending[cpu] |= val; |
123 | ba3c64fb | bellard | slavio_check_interrupts(s); |
124 | f930d07e | blueswir1 | DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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125 | f930d07e | blueswir1 | break;
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126 | e80cfcfc | bellard | default:
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127 | f930d07e | blueswir1 | break;
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128 | e80cfcfc | bellard | } |
129 | e80cfcfc | bellard | } |
130 | e80cfcfc | bellard | |
131 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = { |
132 | 7c560456 | blueswir1 | NULL,
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133 | 7c560456 | blueswir1 | NULL,
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134 | e80cfcfc | bellard | slavio_intctl_mem_readl, |
135 | e80cfcfc | bellard | }; |
136 | e80cfcfc | bellard | |
137 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = { |
138 | 7c560456 | blueswir1 | NULL,
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139 | 7c560456 | blueswir1 | NULL,
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140 | e80cfcfc | bellard | slavio_intctl_mem_writel, |
141 | e80cfcfc | bellard | }; |
142 | e80cfcfc | bellard | |
143 | e80cfcfc | bellard | // master system interrupt controller
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144 | e80cfcfc | bellard | static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) |
145 | e80cfcfc | bellard | { |
146 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
147 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
148 | e80cfcfc | bellard | |
149 | cc2acc47 | blueswir1 | saddr = (addr & INTCTLM_MASK) >> 2;
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150 | e80cfcfc | bellard | switch (saddr) {
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151 | e80cfcfc | bellard | case 0: |
152 | 9a87ce9b | blueswir1 | ret = s->intregm_pending & ~MASTER_DISABLE; |
153 | dd4131b3 | blueswir1 | break;
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154 | e80cfcfc | bellard | case 1: |
155 | 80be36b8 | blueswir1 | ret = s->intregm_disabled & MASTER_IRQ_MASK; |
156 | dd4131b3 | blueswir1 | break;
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157 | e80cfcfc | bellard | case 4: |
158 | dd4131b3 | blueswir1 | ret = s->target_cpu; |
159 | dd4131b3 | blueswir1 | break;
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160 | e80cfcfc | bellard | default:
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161 | dd4131b3 | blueswir1 | ret = 0;
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162 | dd4131b3 | blueswir1 | break;
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163 | e80cfcfc | bellard | } |
164 | 1569fc29 | blueswir1 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
165 | dd4131b3 | blueswir1 | |
166 | dd4131b3 | blueswir1 | return ret;
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167 | e80cfcfc | bellard | } |
168 | e80cfcfc | bellard | |
169 | e80cfcfc | bellard | static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
170 | e80cfcfc | bellard | { |
171 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
172 | e80cfcfc | bellard | uint32_t saddr; |
173 | e80cfcfc | bellard | |
174 | c6fdf5fc | blueswir1 | saddr = (addr & INTCTLM_MASK) >> 2;
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175 | 1569fc29 | blueswir1 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
176 | e80cfcfc | bellard | switch (saddr) {
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177 | e80cfcfc | bellard | case 2: // clear (enable) |
178 | f930d07e | blueswir1 | // Force clear unused bits
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179 | 9a87ce9b | blueswir1 | val &= MASTER_IRQ_MASK; |
180 | f930d07e | blueswir1 | s->intregm_disabled &= ~val; |
181 | f930d07e | blueswir1 | DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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182 | f930d07e | blueswir1 | slavio_check_interrupts(s); |
183 | f930d07e | blueswir1 | break;
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184 | e80cfcfc | bellard | case 3: // set (disable, clear pending) |
185 | f930d07e | blueswir1 | // Force clear unused bits
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186 | 9a87ce9b | blueswir1 | val &= MASTER_IRQ_MASK; |
187 | f930d07e | blueswir1 | s->intregm_disabled |= val; |
188 | f930d07e | blueswir1 | s->intregm_pending &= ~val; |
189 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
190 | f930d07e | blueswir1 | DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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191 | f930d07e | blueswir1 | break;
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192 | e80cfcfc | bellard | case 4: |
193 | f930d07e | blueswir1 | s->target_cpu = val & (MAX_CPUS - 1);
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194 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
195 | f930d07e | blueswir1 | DPRINTF("Set master irq cpu %d\n", s->target_cpu);
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196 | f930d07e | blueswir1 | break;
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197 | e80cfcfc | bellard | default:
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198 | f930d07e | blueswir1 | break;
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199 | e80cfcfc | bellard | } |
200 | e80cfcfc | bellard | } |
201 | e80cfcfc | bellard | |
202 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = { |
203 | 7c560456 | blueswir1 | NULL,
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204 | 7c560456 | blueswir1 | NULL,
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205 | e80cfcfc | bellard | slavio_intctlm_mem_readl, |
206 | e80cfcfc | bellard | }; |
207 | e80cfcfc | bellard | |
208 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = { |
209 | 7c560456 | blueswir1 | NULL,
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210 | 7c560456 | blueswir1 | NULL,
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211 | e80cfcfc | bellard | slavio_intctlm_mem_writel, |
212 | e80cfcfc | bellard | }; |
213 | e80cfcfc | bellard | |
214 | e80cfcfc | bellard | void slavio_pic_info(void *opaque) |
215 | e80cfcfc | bellard | { |
216 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
217 | e80cfcfc | bellard | int i;
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218 | e80cfcfc | bellard | |
219 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
220 | f930d07e | blueswir1 | term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
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221 | e80cfcfc | bellard | } |
222 | e80cfcfc | bellard | term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
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223 | e80cfcfc | bellard | } |
224 | e80cfcfc | bellard | |
225 | e80cfcfc | bellard | void slavio_irq_info(void *opaque) |
226 | e80cfcfc | bellard | { |
227 | e80cfcfc | bellard | #ifndef DEBUG_IRQ_COUNT
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228 | e80cfcfc | bellard | term_printf("irq statistic code not compiled.\n");
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229 | e80cfcfc | bellard | #else
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230 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
231 | e80cfcfc | bellard | int i;
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232 | e80cfcfc | bellard | int64_t count; |
233 | e80cfcfc | bellard | |
234 | e80cfcfc | bellard | term_printf("IRQ statistics:\n");
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235 | e80cfcfc | bellard | for (i = 0; i < 32; i++) { |
236 | e80cfcfc | bellard | count = s->irq_count[i]; |
237 | e80cfcfc | bellard | if (count > 0) |
238 | 26a76461 | bellard | term_printf("%2d: %" PRId64 "\n", i, count); |
239 | e80cfcfc | bellard | } |
240 | e80cfcfc | bellard | #endif
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241 | e80cfcfc | bellard | } |
242 | e80cfcfc | bellard | |
243 | 66321a11 | bellard | static void slavio_check_interrupts(void *opaque) |
244 | 66321a11 | bellard | { |
245 | 66321a11 | bellard | SLAVIO_INTCTLState *s = opaque; |
246 | 327ac2e7 | blueswir1 | uint32_t pending = s->intregm_pending, pil_pending; |
247 | 327ac2e7 | blueswir1 | unsigned int i, j; |
248 | 66321a11 | bellard | |
249 | 66321a11 | bellard | pending &= ~s->intregm_disabled; |
250 | 66321a11 | bellard | |
251 | b3a23197 | blueswir1 | DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
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252 | ba3c64fb | bellard | for (i = 0; i < MAX_CPUS; i++) { |
253 | 327ac2e7 | blueswir1 | pil_pending = 0;
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254 | 9a87ce9b | blueswir1 | if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
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255 | b3a23197 | blueswir1 | (i == s->target_cpu)) { |
256 | b3a23197 | blueswir1 | for (j = 0; j < 32; j++) { |
257 | 327ac2e7 | blueswir1 | if (pending & (1 << j)) |
258 | 327ac2e7 | blueswir1 | pil_pending |= 1 << s->intbit_to_level[j];
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259 | b3a23197 | blueswir1 | } |
260 | b3a23197 | blueswir1 | } |
261 | 6341fdcb | blueswir1 | pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
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262 | 327ac2e7 | blueswir1 | |
263 | 327ac2e7 | blueswir1 | for (j = 0; j < MAX_PILS; j++) { |
264 | 327ac2e7 | blueswir1 | if (pil_pending & (1 << j)) { |
265 | 327ac2e7 | blueswir1 | if (!(s->pil_out[i] & (1 << j))) |
266 | 327ac2e7 | blueswir1 | qemu_irq_raise(s->cpu_irqs[i][j]); |
267 | 327ac2e7 | blueswir1 | } else {
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268 | 327ac2e7 | blueswir1 | if (s->pil_out[i] & (1 << j)) |
269 | 327ac2e7 | blueswir1 | qemu_irq_lower(s->cpu_irqs[i][j]); |
270 | ba3c64fb | bellard | } |
271 | ba3c64fb | bellard | } |
272 | 327ac2e7 | blueswir1 | s->pil_out[i] = pil_pending; |
273 | ba3c64fb | bellard | } |
274 | 66321a11 | bellard | } |
275 | 66321a11 | bellard | |
276 | e80cfcfc | bellard | /*
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277 | e80cfcfc | bellard | * "irq" here is the bit number in the system interrupt register to
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278 | e80cfcfc | bellard | * separate serial and keyboard interrupts sharing a level.
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279 | e80cfcfc | bellard | */
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280 | d7edfd27 | blueswir1 | static void slavio_set_irq(void *opaque, int irq, int level) |
281 | e80cfcfc | bellard | { |
282 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
283 | b3a23197 | blueswir1 | uint32_t mask = 1 << irq;
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284 | b3a23197 | blueswir1 | uint32_t pil = s->intbit_to_level[irq]; |
285 | b3a23197 | blueswir1 | |
286 | b3a23197 | blueswir1 | DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
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287 | b3a23197 | blueswir1 | level); |
288 | b3a23197 | blueswir1 | if (pil > 0) { |
289 | b3a23197 | blueswir1 | if (level) {
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290 | 327ac2e7 | blueswir1 | #ifdef DEBUG_IRQ_COUNT
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291 | 327ac2e7 | blueswir1 | s->irq_count[pil]++; |
292 | 327ac2e7 | blueswir1 | #endif
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293 | b3a23197 | blueswir1 | s->intregm_pending |= mask; |
294 | b3a23197 | blueswir1 | s->intreg_pending[s->target_cpu] |= 1 << pil;
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295 | b3a23197 | blueswir1 | } else {
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296 | b3a23197 | blueswir1 | s->intregm_pending &= ~mask; |
297 | b3a23197 | blueswir1 | s->intreg_pending[s->target_cpu] &= ~(1 << pil);
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298 | b3a23197 | blueswir1 | } |
299 | b3a23197 | blueswir1 | slavio_check_interrupts(s); |
300 | e80cfcfc | bellard | } |
301 | e80cfcfc | bellard | } |
302 | e80cfcfc | bellard | |
303 | d7edfd27 | blueswir1 | static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) |
304 | ba3c64fb | bellard | { |
305 | ba3c64fb | bellard | SLAVIO_INTCTLState *s = opaque; |
306 | ba3c64fb | bellard | |
307 | b3a23197 | blueswir1 | DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
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308 | d7edfd27 | blueswir1 | |
309 | e3a79bca | blueswir1 | if (level) {
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310 | e3a79bca | blueswir1 | s->intregm_pending |= s->cputimer_mbit; |
311 | e3a79bca | blueswir1 | s->intreg_pending[cpu] |= s->cputimer_lbit; |
312 | e3a79bca | blueswir1 | } else {
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313 | e3a79bca | blueswir1 | s->intregm_pending &= ~s->cputimer_mbit; |
314 | e3a79bca | blueswir1 | s->intreg_pending[cpu] &= ~s->cputimer_lbit; |
315 | e3a79bca | blueswir1 | } |
316 | d7edfd27 | blueswir1 | |
317 | ba3c64fb | bellard | slavio_check_interrupts(s); |
318 | ba3c64fb | bellard | } |
319 | ba3c64fb | bellard | |
320 | e80cfcfc | bellard | static void slavio_intctl_save(QEMUFile *f, void *opaque) |
321 | e80cfcfc | bellard | { |
322 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
323 | e80cfcfc | bellard | int i;
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324 | 3b46e624 | ths | |
325 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
326 | f930d07e | blueswir1 | qemu_put_be32s(f, &s->intreg_pending[i]); |
327 | e80cfcfc | bellard | } |
328 | e80cfcfc | bellard | qemu_put_be32s(f, &s->intregm_pending); |
329 | e80cfcfc | bellard | qemu_put_be32s(f, &s->intregm_disabled); |
330 | e80cfcfc | bellard | qemu_put_be32s(f, &s->target_cpu); |
331 | e80cfcfc | bellard | } |
332 | e80cfcfc | bellard | |
333 | e80cfcfc | bellard | static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id) |
334 | e80cfcfc | bellard | { |
335 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
336 | e80cfcfc | bellard | int i;
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337 | e80cfcfc | bellard | |
338 | e80cfcfc | bellard | if (version_id != 1) |
339 | e80cfcfc | bellard | return -EINVAL;
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340 | e80cfcfc | bellard | |
341 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
342 | f930d07e | blueswir1 | qemu_get_be32s(f, &s->intreg_pending[i]); |
343 | e80cfcfc | bellard | } |
344 | e80cfcfc | bellard | qemu_get_be32s(f, &s->intregm_pending); |
345 | e80cfcfc | bellard | qemu_get_be32s(f, &s->intregm_disabled); |
346 | e80cfcfc | bellard | qemu_get_be32s(f, &s->target_cpu); |
347 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
348 | e80cfcfc | bellard | return 0; |
349 | e80cfcfc | bellard | } |
350 | e80cfcfc | bellard | |
351 | e80cfcfc | bellard | static void slavio_intctl_reset(void *opaque) |
352 | e80cfcfc | bellard | { |
353 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
354 | e80cfcfc | bellard | int i;
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355 | e80cfcfc | bellard | |
356 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
357 | f930d07e | blueswir1 | s->intreg_pending[i] = 0;
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358 | e80cfcfc | bellard | } |
359 | 9a87ce9b | blueswir1 | s->intregm_disabled = ~MASTER_IRQ_MASK; |
360 | e80cfcfc | bellard | s->intregm_pending = 0;
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361 | e80cfcfc | bellard | s->target_cpu = 0;
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362 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
363 | e80cfcfc | bellard | } |
364 | e80cfcfc | bellard | |
365 | 5dcb6b91 | blueswir1 | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
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366 | d537cf6c | pbrook | const uint32_t *intbit_to_level,
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367 | d7edfd27 | blueswir1 | qemu_irq **irq, qemu_irq **cpu_irq, |
368 | b3a23197 | blueswir1 | qemu_irq **parent_irq, unsigned int cputimer) |
369 | e80cfcfc | bellard | { |
370 | e80cfcfc | bellard | int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
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371 | e80cfcfc | bellard | SLAVIO_INTCTLState *s; |
372 | e80cfcfc | bellard | |
373 | e80cfcfc | bellard | s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
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374 | e80cfcfc | bellard | if (!s)
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375 | e80cfcfc | bellard | return NULL; |
376 | e80cfcfc | bellard | |
377 | e0353fe2 | blueswir1 | s->intbit_to_level = intbit_to_level; |
378 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
379 | f930d07e | blueswir1 | slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
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380 | f930d07e | blueswir1 | cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, |
381 | 5aca8c3b | blueswir1 | slavio_intctl_io_memory); |
382 | b3a23197 | blueswir1 | s->cpu_irqs[i] = parent_irq[i]; |
383 | e80cfcfc | bellard | } |
384 | e80cfcfc | bellard | |
385 | e80cfcfc | bellard | slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
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386 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory); |
387 | e80cfcfc | bellard | |
388 | e80cfcfc | bellard | register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s); |
389 | e80cfcfc | bellard | qemu_register_reset(slavio_intctl_reset, s); |
390 | d537cf6c | pbrook | *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
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391 | d7edfd27 | blueswir1 | |
392 | d7edfd27 | blueswir1 | *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS); |
393 | e3a79bca | blueswir1 | s->cputimer_mbit = 1 << cputimer;
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394 | e3a79bca | blueswir1 | s->cputimer_lbit = 1 << intbit_to_level[cputimer];
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395 | e80cfcfc | bellard | slavio_intctl_reset(s); |
396 | e80cfcfc | bellard | return s;
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397 | e80cfcfc | bellard | } |