root / hw / pflash_cfi02.c @ 22ed1d34
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1 | 29133e9a | bellard | /*
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2 | 29133e9a | bellard | * CFI parallel flash with AMD command set emulation
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3 | 5fafdf24 | ths | *
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4 | 29133e9a | bellard | * Copyright (c) 2005 Jocelyn Mayer
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5 | 29133e9a | bellard | *
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6 | 29133e9a | bellard | * This library is free software; you can redistribute it and/or
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7 | 29133e9a | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 29133e9a | bellard | * License as published by the Free Software Foundation; either
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9 | 29133e9a | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 29133e9a | bellard | *
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11 | 29133e9a | bellard | * This library is distributed in the hope that it will be useful,
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12 | 29133e9a | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 29133e9a | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 29133e9a | bellard | * Lesser General Public License for more details.
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15 | 29133e9a | bellard | *
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16 | 29133e9a | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 29133e9a | bellard | */
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19 | 29133e9a | bellard | |
20 | 29133e9a | bellard | /*
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21 | 29133e9a | bellard | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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22 | 29133e9a | bellard | * Supported commands/modes are:
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23 | 29133e9a | bellard | * - flash read
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24 | 29133e9a | bellard | * - flash write
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25 | 29133e9a | bellard | * - flash ID read
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26 | 29133e9a | bellard | * - sector erase
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27 | 29133e9a | bellard | * - chip erase
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28 | 29133e9a | bellard | * - unlock bypass command
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29 | 29133e9a | bellard | * - CFI queries
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30 | 29133e9a | bellard | *
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31 | 29133e9a | bellard | * It does not support flash interleaving.
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32 | 29133e9a | bellard | * It does not implement boot blocs with reduced size
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33 | 29133e9a | bellard | * It does not implement software data protection as found in many real chips
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34 | 29133e9a | bellard | * It does not implement erase suspend/resume commands
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35 | 29133e9a | bellard | * It does not implement multiple sectors erase
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36 | 29133e9a | bellard | */
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37 | 29133e9a | bellard | |
38 | 87ecb68b | pbrook | #include "hw.h" |
39 | 87ecb68b | pbrook | #include "flash.h" |
40 | 87ecb68b | pbrook | #include "qemu-timer.h" |
41 | 87ecb68b | pbrook | #include "block.h" |
42 | 29133e9a | bellard | |
43 | 29133e9a | bellard | //#define PFLASH_DEBUG
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44 | 29133e9a | bellard | #ifdef PFLASH_DEBUG
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45 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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46 | 29133e9a | bellard | do { \
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47 | 001faf32 | Blue Swirl | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
48 | 29133e9a | bellard | } while (0) |
49 | 29133e9a | bellard | #else
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50 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
51 | 29133e9a | bellard | #endif
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52 | 29133e9a | bellard | |
53 | c227f099 | Anthony Liguori | struct pflash_t {
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54 | 29133e9a | bellard | BlockDriverState *bs; |
55 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
56 | 71db710f | blueswir1 | uint32_t sector_len; |
57 | 4fbd24ba | balrog | uint32_t chip_len; |
58 | 4fbd24ba | balrog | int mappings;
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59 | 29133e9a | bellard | int width;
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60 | 29133e9a | bellard | int wcycle; /* if 0, the flash is read normally */ |
61 | 29133e9a | bellard | int bypass;
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62 | 29133e9a | bellard | int ro;
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63 | 29133e9a | bellard | uint8_t cmd; |
64 | 29133e9a | bellard | uint8_t status; |
65 | 29133e9a | bellard | uint16_t ident[4];
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66 | 6725070d | balrog | uint16_t unlock_addr[2];
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67 | 29133e9a | bellard | uint8_t cfi_len; |
68 | 29133e9a | bellard | uint8_t cfi_table[0x52];
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69 | 29133e9a | bellard | QEMUTimer *timer; |
70 | c227f099 | Anthony Liguori | ram_addr_t off; |
71 | 29133e9a | bellard | int fl_mem;
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72 | 9c9bb6c8 | balrog | int rom_mode;
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73 | 29133e9a | bellard | void *storage;
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74 | 29133e9a | bellard | }; |
75 | 29133e9a | bellard | |
76 | c227f099 | Anthony Liguori | static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
77 | 4fbd24ba | balrog | { |
78 | 4fbd24ba | balrog | unsigned long phys_offset = pfl->fl_mem; |
79 | 4fbd24ba | balrog | int i;
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80 | 4fbd24ba | balrog | |
81 | 4fbd24ba | balrog | if (rom_mode)
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82 | 4fbd24ba | balrog | phys_offset |= pfl->off | IO_MEM_ROMD; |
83 | 9c9bb6c8 | balrog | pfl->rom_mode = rom_mode; |
84 | 4fbd24ba | balrog | |
85 | 4fbd24ba | balrog | for (i = 0; i < pfl->mappings; i++) |
86 | 4fbd24ba | balrog | cpu_register_physical_memory(pfl->base + i * pfl->chip_len, |
87 | 4fbd24ba | balrog | pfl->chip_len, phys_offset); |
88 | 4fbd24ba | balrog | } |
89 | 4fbd24ba | balrog | |
90 | 29133e9a | bellard | static void pflash_timer (void *opaque) |
91 | 29133e9a | bellard | { |
92 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
93 | 29133e9a | bellard | |
94 | 29133e9a | bellard | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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95 | 29133e9a | bellard | /* Reset flash */
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96 | 29133e9a | bellard | pfl->status ^= 0x80;
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97 | 29133e9a | bellard | if (pfl->bypass) {
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98 | 29133e9a | bellard | pfl->wcycle = 2;
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99 | 29133e9a | bellard | } else {
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100 | 4fbd24ba | balrog | pflash_register_memory(pfl, 1);
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101 | 29133e9a | bellard | pfl->wcycle = 0;
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102 | 29133e9a | bellard | } |
103 | 29133e9a | bellard | pfl->cmd = 0;
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104 | 29133e9a | bellard | } |
105 | 29133e9a | bellard | |
106 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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107 | 5f9fc5ad | Blue Swirl | int width, int be) |
108 | 29133e9a | bellard | { |
109 | f8be67ee | Blue Swirl | target_phys_addr_t boff; |
110 | 29133e9a | bellard | uint32_t ret; |
111 | 29133e9a | bellard | uint8_t *p; |
112 | 29133e9a | bellard | |
113 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); |
114 | 29133e9a | bellard | ret = -1;
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115 | 9c9bb6c8 | balrog | if (pfl->rom_mode) {
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116 | 9c9bb6c8 | balrog | /* Lazy reset of to ROMD mode */
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117 | 9c9bb6c8 | balrog | if (pfl->wcycle == 0) |
118 | 9c9bb6c8 | balrog | pflash_register_memory(pfl, 1);
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119 | 0f459d16 | pbrook | } |
120 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
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121 | 29133e9a | bellard | boff = offset & 0xFF;
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122 | 29133e9a | bellard | if (pfl->width == 2) |
123 | 29133e9a | bellard | boff = boff >> 1;
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124 | 29133e9a | bellard | else if (pfl->width == 4) |
125 | 29133e9a | bellard | boff = boff >> 2;
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126 | 29133e9a | bellard | switch (pfl->cmd) {
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127 | 29133e9a | bellard | default:
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128 | 29133e9a | bellard | /* This should never happen : reset state & treat it as a read*/
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129 | 29133e9a | bellard | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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130 | 29133e9a | bellard | pfl->wcycle = 0;
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131 | 29133e9a | bellard | pfl->cmd = 0;
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132 | 29133e9a | bellard | case 0x80: |
133 | 29133e9a | bellard | /* We accept reads during second unlock sequence... */
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134 | 29133e9a | bellard | case 0x00: |
135 | 29133e9a | bellard | flash_read:
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136 | 29133e9a | bellard | /* Flash area read */
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137 | 29133e9a | bellard | p = pfl->storage; |
138 | 29133e9a | bellard | switch (width) {
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139 | 29133e9a | bellard | case 1: |
140 | 29133e9a | bellard | ret = p[offset]; |
141 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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142 | 29133e9a | bellard | break;
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143 | 29133e9a | bellard | case 2: |
144 | 5f9fc5ad | Blue Swirl | if (be) {
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145 | 5f9fc5ad | Blue Swirl | ret = p[offset] << 8;
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146 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1];
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147 | 5f9fc5ad | Blue Swirl | } else {
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148 | 5f9fc5ad | Blue Swirl | ret = p[offset]; |
149 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 8; |
150 | 5f9fc5ad | Blue Swirl | } |
151 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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152 | 29133e9a | bellard | break;
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153 | 29133e9a | bellard | case 4: |
154 | 5f9fc5ad | Blue Swirl | if (be) {
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155 | 5f9fc5ad | Blue Swirl | ret = p[offset] << 24;
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156 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 16; |
157 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 2] << 8; |
158 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 3];
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159 | 5f9fc5ad | Blue Swirl | } else {
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160 | 5f9fc5ad | Blue Swirl | ret = p[offset]; |
161 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 1] << 8; |
162 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 2] << 16; |
163 | 5f9fc5ad | Blue Swirl | ret |= p[offset + 3] << 24; |
164 | 5f9fc5ad | Blue Swirl | } |
165 | 29133e9a | bellard | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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166 | 29133e9a | bellard | break;
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167 | 29133e9a | bellard | } |
168 | 29133e9a | bellard | break;
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169 | 29133e9a | bellard | case 0x90: |
170 | 29133e9a | bellard | /* flash ID read */
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171 | 29133e9a | bellard | switch (boff) {
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172 | 29133e9a | bellard | case 0x00: |
173 | 29133e9a | bellard | case 0x01: |
174 | 29133e9a | bellard | ret = pfl->ident[boff & 0x01];
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175 | 29133e9a | bellard | break;
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176 | 29133e9a | bellard | case 0x02: |
177 | 29133e9a | bellard | ret = 0x00; /* Pretend all sectors are unprotected */ |
178 | 29133e9a | bellard | break;
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179 | 29133e9a | bellard | case 0x0E: |
180 | 29133e9a | bellard | case 0x0F: |
181 | 29133e9a | bellard | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
182 | 29133e9a | bellard | goto flash_read;
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183 | 29133e9a | bellard | ret = pfl->ident[2 + (boff & 0x01)]; |
184 | 29133e9a | bellard | break;
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185 | 29133e9a | bellard | default:
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186 | 29133e9a | bellard | goto flash_read;
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187 | 29133e9a | bellard | } |
188 | f8be67ee | Blue Swirl | DPRINTF("%s: ID " TARGET_FMT_pld " %x\n", __func__, boff, ret); |
189 | 29133e9a | bellard | break;
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190 | 29133e9a | bellard | case 0xA0: |
191 | 29133e9a | bellard | case 0x10: |
192 | 29133e9a | bellard | case 0x30: |
193 | 29133e9a | bellard | /* Status register read */
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194 | 29133e9a | bellard | ret = pfl->status; |
195 | 29133e9a | bellard | DPRINTF("%s: status %x\n", __func__, ret);
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196 | 29133e9a | bellard | /* Toggle bit 6 */
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197 | 29133e9a | bellard | pfl->status ^= 0x40;
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198 | 29133e9a | bellard | break;
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199 | 29133e9a | bellard | case 0x98: |
200 | 29133e9a | bellard | /* CFI query mode */
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201 | 29133e9a | bellard | if (boff > pfl->cfi_len)
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202 | 29133e9a | bellard | ret = 0;
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203 | 29133e9a | bellard | else
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204 | 29133e9a | bellard | ret = pfl->cfi_table[boff]; |
205 | 29133e9a | bellard | break;
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206 | 29133e9a | bellard | } |
207 | 29133e9a | bellard | |
208 | 29133e9a | bellard | return ret;
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209 | 29133e9a | bellard | } |
210 | 29133e9a | bellard | |
211 | 29133e9a | bellard | /* update flash content on disk */
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212 | c227f099 | Anthony Liguori | static void pflash_update(pflash_t *pfl, int offset, |
213 | 29133e9a | bellard | int size)
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214 | 29133e9a | bellard | { |
215 | 29133e9a | bellard | int offset_end;
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216 | 29133e9a | bellard | if (pfl->bs) {
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217 | 29133e9a | bellard | offset_end = offset + size; |
218 | 29133e9a | bellard | /* round to sectors */
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219 | 29133e9a | bellard | offset = offset >> 9;
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220 | 29133e9a | bellard | offset_end = (offset_end + 511) >> 9; |
221 | 5fafdf24 | ths | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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222 | 29133e9a | bellard | offset_end - offset); |
223 | 29133e9a | bellard | } |
224 | 29133e9a | bellard | } |
225 | 29133e9a | bellard | |
226 | f8be67ee | Blue Swirl | static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, |
227 | 5f9fc5ad | Blue Swirl | uint32_t value, int width, int be) |
228 | 29133e9a | bellard | { |
229 | f8be67ee | Blue Swirl | target_phys_addr_t boff; |
230 | 29133e9a | bellard | uint8_t *p; |
231 | 29133e9a | bellard | uint8_t cmd; |
232 | 29133e9a | bellard | |
233 | 95d1f3ed | j_mayer | cmd = value; |
234 | 95d1f3ed | j_mayer | if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
235 | 95d1f3ed | j_mayer | #if 0
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236 | 95d1f3ed | j_mayer | DPRINTF("%s: flash reset asked (%02x %02x)\n",
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237 | 95d1f3ed | j_mayer | __func__, pfl->cmd, cmd);
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238 | 95d1f3ed | j_mayer | #endif
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239 | 95d1f3ed | j_mayer | goto reset_flash;
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240 | 95d1f3ed | j_mayer | } |
241 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, |
242 | 95d1f3ed | j_mayer | offset, value, width, pfl->wcycle); |
243 | 4fbd24ba | balrog | offset &= pfl->chip_len - 1;
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244 | 3b46e624 | ths | |
245 | f8be67ee | Blue Swirl | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, |
246 | e96efcfc | j_mayer | offset, value, width); |
247 | 29133e9a | bellard | boff = offset & (pfl->sector_len - 1);
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248 | 29133e9a | bellard | if (pfl->width == 2) |
249 | 29133e9a | bellard | boff = boff >> 1;
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250 | 29133e9a | bellard | else if (pfl->width == 4) |
251 | 29133e9a | bellard | boff = boff >> 2;
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252 | 29133e9a | bellard | switch (pfl->wcycle) {
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253 | 29133e9a | bellard | case 0: |
254 | 9c9bb6c8 | balrog | /* Set the device in I/O access mode if required */
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255 | 9c9bb6c8 | balrog | if (pfl->rom_mode)
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256 | 9c9bb6c8 | balrog | pflash_register_memory(pfl, 0);
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257 | 29133e9a | bellard | /* We're in read mode */
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258 | 29133e9a | bellard | check_unlock0:
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259 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) { |
260 | 29133e9a | bellard | enter_CFI_mode:
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261 | 29133e9a | bellard | /* Enter CFI query mode */
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262 | 29133e9a | bellard | pfl->wcycle = 7;
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263 | 29133e9a | bellard | pfl->cmd = 0x98;
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264 | 29133e9a | bellard | return;
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265 | 29133e9a | bellard | } |
266 | 6725070d | balrog | if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
267 | f8be67ee | Blue Swirl | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
268 | 6725070d | balrog | __func__, boff, cmd, pfl->unlock_addr[0]);
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269 | 29133e9a | bellard | goto reset_flash;
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270 | 29133e9a | bellard | } |
271 | 29133e9a | bellard | DPRINTF("%s: unlock sequence started\n", __func__);
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272 | 29133e9a | bellard | break;
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273 | 29133e9a | bellard | case 1: |
274 | 29133e9a | bellard | /* We started an unlock sequence */
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275 | 29133e9a | bellard | check_unlock1:
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276 | 6725070d | balrog | if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
277 | f8be67ee | Blue Swirl | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
278 | e96efcfc | j_mayer | boff, cmd); |
279 | 29133e9a | bellard | goto reset_flash;
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280 | 29133e9a | bellard | } |
281 | 29133e9a | bellard | DPRINTF("%s: unlock sequence done\n", __func__);
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282 | 29133e9a | bellard | break;
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283 | 29133e9a | bellard | case 2: |
284 | 29133e9a | bellard | /* We finished an unlock sequence */
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285 | 6725070d | balrog | if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
286 | f8be67ee | Blue Swirl | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
287 | e96efcfc | j_mayer | boff, cmd); |
288 | 29133e9a | bellard | goto reset_flash;
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289 | 29133e9a | bellard | } |
290 | 29133e9a | bellard | switch (cmd) {
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291 | 29133e9a | bellard | case 0x20: |
292 | 29133e9a | bellard | pfl->bypass = 1;
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293 | 29133e9a | bellard | goto do_bypass;
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294 | 29133e9a | bellard | case 0x80: |
295 | 29133e9a | bellard | case 0x90: |
296 | 29133e9a | bellard | case 0xA0: |
297 | 29133e9a | bellard | pfl->cmd = cmd; |
298 | 29133e9a | bellard | DPRINTF("%s: starting command %02x\n", __func__, cmd);
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299 | 29133e9a | bellard | break;
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300 | 29133e9a | bellard | default:
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301 | 29133e9a | bellard | DPRINTF("%s: unknown command %02x\n", __func__, cmd);
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302 | 29133e9a | bellard | goto reset_flash;
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303 | 29133e9a | bellard | } |
304 | 29133e9a | bellard | break;
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305 | 29133e9a | bellard | case 3: |
306 | 29133e9a | bellard | switch (pfl->cmd) {
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307 | 29133e9a | bellard | case 0x80: |
308 | 29133e9a | bellard | /* We need another unlock sequence */
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309 | 29133e9a | bellard | goto check_unlock0;
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310 | 29133e9a | bellard | case 0xA0: |
311 | f8be67ee | Blue Swirl | DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", |
312 | 29133e9a | bellard | __func__, offset, value, width); |
313 | 29133e9a | bellard | p = pfl->storage; |
314 | 29133e9a | bellard | switch (width) {
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315 | 29133e9a | bellard | case 1: |
316 | 29133e9a | bellard | p[offset] &= value; |
317 | 29133e9a | bellard | pflash_update(pfl, offset, 1);
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318 | 29133e9a | bellard | break;
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319 | 29133e9a | bellard | case 2: |
320 | 5f9fc5ad | Blue Swirl | if (be) {
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321 | 5f9fc5ad | Blue Swirl | p[offset] &= value >> 8;
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322 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value;
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323 | 5f9fc5ad | Blue Swirl | } else {
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324 | 5f9fc5ad | Blue Swirl | p[offset] &= value; |
325 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value >> 8; |
326 | 5f9fc5ad | Blue Swirl | } |
327 | 29133e9a | bellard | pflash_update(pfl, offset, 2);
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328 | 29133e9a | bellard | break;
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329 | 29133e9a | bellard | case 4: |
330 | 5f9fc5ad | Blue Swirl | if (be) {
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331 | 5f9fc5ad | Blue Swirl | p[offset] &= value >> 24;
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332 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value >> 16; |
333 | 5f9fc5ad | Blue Swirl | p[offset + 2] &= value >> 8; |
334 | 5f9fc5ad | Blue Swirl | p[offset + 3] &= value;
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335 | 5f9fc5ad | Blue Swirl | } else {
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336 | 5f9fc5ad | Blue Swirl | p[offset] &= value; |
337 | 5f9fc5ad | Blue Swirl | p[offset + 1] &= value >> 8; |
338 | 5f9fc5ad | Blue Swirl | p[offset + 2] &= value >> 16; |
339 | 5f9fc5ad | Blue Swirl | p[offset + 3] &= value >> 24; |
340 | 5f9fc5ad | Blue Swirl | } |
341 | 29133e9a | bellard | pflash_update(pfl, offset, 4);
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342 | 29133e9a | bellard | break;
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343 | 29133e9a | bellard | } |
344 | 29133e9a | bellard | pfl->status = 0x00 | ~(value & 0x80); |
345 | 29133e9a | bellard | /* Let's pretend write is immediate */
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346 | 29133e9a | bellard | if (pfl->bypass)
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347 | 29133e9a | bellard | goto do_bypass;
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348 | 29133e9a | bellard | goto reset_flash;
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349 | 29133e9a | bellard | case 0x90: |
350 | 29133e9a | bellard | if (pfl->bypass && cmd == 0x00) { |
351 | 29133e9a | bellard | /* Unlock bypass reset */
|
352 | 29133e9a | bellard | goto reset_flash;
|
353 | 29133e9a | bellard | } |
354 | 29133e9a | bellard | /* We can enter CFI query mode from autoselect mode */
|
355 | 29133e9a | bellard | if (boff == 0x55 && cmd == 0x98) |
356 | 29133e9a | bellard | goto enter_CFI_mode;
|
357 | 29133e9a | bellard | /* No break here */
|
358 | 29133e9a | bellard | default:
|
359 | 29133e9a | bellard | DPRINTF("%s: invalid write for command %02x\n",
|
360 | 29133e9a | bellard | __func__, pfl->cmd); |
361 | 29133e9a | bellard | goto reset_flash;
|
362 | 29133e9a | bellard | } |
363 | 29133e9a | bellard | case 4: |
364 | 29133e9a | bellard | switch (pfl->cmd) {
|
365 | 29133e9a | bellard | case 0xA0: |
366 | 29133e9a | bellard | /* Ignore writes while flash data write is occuring */
|
367 | 29133e9a | bellard | /* As we suppose write is immediate, this should never happen */
|
368 | 29133e9a | bellard | return;
|
369 | 29133e9a | bellard | case 0x80: |
370 | 29133e9a | bellard | goto check_unlock1;
|
371 | 29133e9a | bellard | default:
|
372 | 29133e9a | bellard | /* Should never happen */
|
373 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
374 | 29133e9a | bellard | __func__, pfl->cmd); |
375 | 29133e9a | bellard | goto reset_flash;
|
376 | 29133e9a | bellard | } |
377 | 29133e9a | bellard | break;
|
378 | 29133e9a | bellard | case 5: |
379 | 29133e9a | bellard | switch (cmd) {
|
380 | 29133e9a | bellard | case 0x10: |
381 | 6725070d | balrog | if (boff != pfl->unlock_addr[0]) { |
382 | f8be67ee | Blue Swirl | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
383 | 29133e9a | bellard | __func__, offset); |
384 | 29133e9a | bellard | goto reset_flash;
|
385 | 29133e9a | bellard | } |
386 | 29133e9a | bellard | /* Chip erase */
|
387 | 29133e9a | bellard | DPRINTF("%s: start chip erase\n", __func__);
|
388 | 4fbd24ba | balrog | memset(pfl->storage, 0xFF, pfl->chip_len);
|
389 | 29133e9a | bellard | pfl->status = 0x00;
|
390 | 4fbd24ba | balrog | pflash_update(pfl, 0, pfl->chip_len);
|
391 | 29133e9a | bellard | /* Let's wait 5 seconds before chip erase is done */
|
392 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
393 | 6ee093c9 | Juan Quintela | qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 5));
|
394 | 29133e9a | bellard | break;
|
395 | 29133e9a | bellard | case 0x30: |
396 | 29133e9a | bellard | /* Sector erase */
|
397 | 29133e9a | bellard | p = pfl->storage; |
398 | 29133e9a | bellard | offset &= ~(pfl->sector_len - 1);
|
399 | f8be67ee | Blue Swirl | DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
400 | e96efcfc | j_mayer | offset); |
401 | 29133e9a | bellard | memset(p + offset, 0xFF, pfl->sector_len);
|
402 | 29133e9a | bellard | pflash_update(pfl, offset, pfl->sector_len); |
403 | 29133e9a | bellard | pfl->status = 0x00;
|
404 | 29133e9a | bellard | /* Let's wait 1/2 second before sector erase is done */
|
405 | 5fafdf24 | ths | qemu_mod_timer(pfl->timer, |
406 | 6ee093c9 | Juan Quintela | qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 2));
|
407 | 29133e9a | bellard | break;
|
408 | 29133e9a | bellard | default:
|
409 | 29133e9a | bellard | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
410 | 29133e9a | bellard | goto reset_flash;
|
411 | 29133e9a | bellard | } |
412 | 29133e9a | bellard | pfl->cmd = cmd; |
413 | 29133e9a | bellard | break;
|
414 | 29133e9a | bellard | case 6: |
415 | 29133e9a | bellard | switch (pfl->cmd) {
|
416 | 29133e9a | bellard | case 0x10: |
417 | 29133e9a | bellard | /* Ignore writes during chip erase */
|
418 | 29133e9a | bellard | return;
|
419 | 29133e9a | bellard | case 0x30: |
420 | 29133e9a | bellard | /* Ignore writes during sector erase */
|
421 | 29133e9a | bellard | return;
|
422 | 29133e9a | bellard | default:
|
423 | 29133e9a | bellard | /* Should never happen */
|
424 | 29133e9a | bellard | DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
425 | 29133e9a | bellard | __func__, pfl->cmd); |
426 | 29133e9a | bellard | goto reset_flash;
|
427 | 29133e9a | bellard | } |
428 | 29133e9a | bellard | break;
|
429 | 29133e9a | bellard | case 7: /* Special value for CFI queries */ |
430 | 29133e9a | bellard | DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
431 | 29133e9a | bellard | goto reset_flash;
|
432 | 29133e9a | bellard | default:
|
433 | 29133e9a | bellard | /* Should never happen */
|
434 | 29133e9a | bellard | DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
435 | 29133e9a | bellard | goto reset_flash;
|
436 | 29133e9a | bellard | } |
437 | 29133e9a | bellard | pfl->wcycle++; |
438 | 29133e9a | bellard | |
439 | 29133e9a | bellard | return;
|
440 | 29133e9a | bellard | |
441 | 29133e9a | bellard | /* Reset flash */
|
442 | 29133e9a | bellard | reset_flash:
|
443 | 29133e9a | bellard | pfl->bypass = 0;
|
444 | 29133e9a | bellard | pfl->wcycle = 0;
|
445 | 29133e9a | bellard | pfl->cmd = 0;
|
446 | 29133e9a | bellard | return;
|
447 | 29133e9a | bellard | |
448 | 29133e9a | bellard | do_bypass:
|
449 | 29133e9a | bellard | pfl->wcycle = 2;
|
450 | 29133e9a | bellard | pfl->cmd = 0;
|
451 | 29133e9a | bellard | return;
|
452 | 29133e9a | bellard | } |
453 | 29133e9a | bellard | |
454 | 29133e9a | bellard | |
455 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) |
456 | 5f9fc5ad | Blue Swirl | { |
457 | 5f9fc5ad | Blue Swirl | return pflash_read(opaque, addr, 1, 1); |
458 | 5f9fc5ad | Blue Swirl | } |
459 | 5f9fc5ad | Blue Swirl | |
460 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) |
461 | 5f9fc5ad | Blue Swirl | { |
462 | 5f9fc5ad | Blue Swirl | return pflash_read(opaque, addr, 1, 0); |
463 | 5f9fc5ad | Blue Swirl | } |
464 | 5f9fc5ad | Blue Swirl | |
465 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) |
466 | 5f9fc5ad | Blue Swirl | { |
467 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
468 | 5f9fc5ad | Blue Swirl | |
469 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 2, 1); |
470 | 5f9fc5ad | Blue Swirl | } |
471 | 5f9fc5ad | Blue Swirl | |
472 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) |
473 | 5f9fc5ad | Blue Swirl | { |
474 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
475 | 5f9fc5ad | Blue Swirl | |
476 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 2, 0); |
477 | 5f9fc5ad | Blue Swirl | } |
478 | 5f9fc5ad | Blue Swirl | |
479 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) |
480 | 29133e9a | bellard | { |
481 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
482 | 5f9fc5ad | Blue Swirl | |
483 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 4, 1); |
484 | 29133e9a | bellard | } |
485 | 29133e9a | bellard | |
486 | 5f9fc5ad | Blue Swirl | static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) |
487 | 29133e9a | bellard | { |
488 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
489 | 29133e9a | bellard | |
490 | 5f9fc5ad | Blue Swirl | return pflash_read(pfl, addr, 4, 0); |
491 | 5f9fc5ad | Blue Swirl | } |
492 | 5f9fc5ad | Blue Swirl | |
493 | 5f9fc5ad | Blue Swirl | static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, |
494 | 5f9fc5ad | Blue Swirl | uint32_t value) |
495 | 5f9fc5ad | Blue Swirl | { |
496 | 5f9fc5ad | Blue Swirl | pflash_write(opaque, addr, value, 1, 1); |
497 | 29133e9a | bellard | } |
498 | 29133e9a | bellard | |
499 | 5f9fc5ad | Blue Swirl | static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, |
500 | 5f9fc5ad | Blue Swirl | uint32_t value) |
501 | 5f9fc5ad | Blue Swirl | { |
502 | 5f9fc5ad | Blue Swirl | pflash_write(opaque, addr, value, 1, 0); |
503 | 5f9fc5ad | Blue Swirl | } |
504 | 5f9fc5ad | Blue Swirl | |
505 | 5f9fc5ad | Blue Swirl | static void pflash_writew_be(void *opaque, target_phys_addr_t addr, |
506 | 5f9fc5ad | Blue Swirl | uint32_t value) |
507 | 29133e9a | bellard | { |
508 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
509 | 29133e9a | bellard | |
510 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 2, 1); |
511 | 29133e9a | bellard | } |
512 | 29133e9a | bellard | |
513 | 5f9fc5ad | Blue Swirl | static void pflash_writew_le(void *opaque, target_phys_addr_t addr, |
514 | 5f9fc5ad | Blue Swirl | uint32_t value) |
515 | 29133e9a | bellard | { |
516 | 5f9fc5ad | Blue Swirl | pflash_t *pfl = opaque; |
517 | 5f9fc5ad | Blue Swirl | |
518 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 2, 0); |
519 | 29133e9a | bellard | } |
520 | 29133e9a | bellard | |
521 | 5f9fc5ad | Blue Swirl | static void pflash_writel_be(void *opaque, target_phys_addr_t addr, |
522 | 5f9fc5ad | Blue Swirl | uint32_t value) |
523 | 29133e9a | bellard | { |
524 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
525 | 29133e9a | bellard | |
526 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 4, 1); |
527 | 29133e9a | bellard | } |
528 | 29133e9a | bellard | |
529 | 5f9fc5ad | Blue Swirl | static void pflash_writel_le(void *opaque, target_phys_addr_t addr, |
530 | 5f9fc5ad | Blue Swirl | uint32_t value) |
531 | 29133e9a | bellard | { |
532 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
533 | 29133e9a | bellard | |
534 | 5f9fc5ad | Blue Swirl | pflash_write(pfl, addr, value, 4, 0); |
535 | 29133e9a | bellard | } |
536 | 29133e9a | bellard | |
537 | 5f9fc5ad | Blue Swirl | static CPUWriteMemoryFunc * const pflash_write_ops_be[] = { |
538 | 5f9fc5ad | Blue Swirl | &pflash_writeb_be, |
539 | 5f9fc5ad | Blue Swirl | &pflash_writew_be, |
540 | 5f9fc5ad | Blue Swirl | &pflash_writel_be, |
541 | 29133e9a | bellard | }; |
542 | 29133e9a | bellard | |
543 | 5f9fc5ad | Blue Swirl | static CPUReadMemoryFunc * const pflash_read_ops_be[] = { |
544 | 5f9fc5ad | Blue Swirl | &pflash_readb_be, |
545 | 5f9fc5ad | Blue Swirl | &pflash_readw_be, |
546 | 5f9fc5ad | Blue Swirl | &pflash_readl_be, |
547 | 5f9fc5ad | Blue Swirl | }; |
548 | 5f9fc5ad | Blue Swirl | |
549 | 5f9fc5ad | Blue Swirl | static CPUWriteMemoryFunc * const pflash_write_ops_le[] = { |
550 | 5f9fc5ad | Blue Swirl | &pflash_writeb_le, |
551 | 5f9fc5ad | Blue Swirl | &pflash_writew_le, |
552 | 5f9fc5ad | Blue Swirl | &pflash_writel_le, |
553 | 5f9fc5ad | Blue Swirl | }; |
554 | 5f9fc5ad | Blue Swirl | |
555 | 5f9fc5ad | Blue Swirl | static CPUReadMemoryFunc * const pflash_read_ops_le[] = { |
556 | 5f9fc5ad | Blue Swirl | &pflash_readb_le, |
557 | 5f9fc5ad | Blue Swirl | &pflash_readw_le, |
558 | 5f9fc5ad | Blue Swirl | &pflash_readl_le, |
559 | 29133e9a | bellard | }; |
560 | 29133e9a | bellard | |
561 | 29133e9a | bellard | /* Count trailing zeroes of a 32 bits quantity */
|
562 | 29133e9a | bellard | static int ctz32 (uint32_t n) |
563 | 29133e9a | bellard | { |
564 | 29133e9a | bellard | int ret;
|
565 | 29133e9a | bellard | |
566 | 29133e9a | bellard | ret = 0;
|
567 | 29133e9a | bellard | if (!(n & 0xFFFF)) { |
568 | 29133e9a | bellard | ret += 16;
|
569 | 29133e9a | bellard | n = n >> 16;
|
570 | 29133e9a | bellard | } |
571 | 29133e9a | bellard | if (!(n & 0xFF)) { |
572 | 29133e9a | bellard | ret += 8;
|
573 | 29133e9a | bellard | n = n >> 8;
|
574 | 29133e9a | bellard | } |
575 | 29133e9a | bellard | if (!(n & 0xF)) { |
576 | 29133e9a | bellard | ret += 4;
|
577 | 29133e9a | bellard | n = n >> 4;
|
578 | 29133e9a | bellard | } |
579 | 29133e9a | bellard | if (!(n & 0x3)) { |
580 | 29133e9a | bellard | ret += 2;
|
581 | 29133e9a | bellard | n = n >> 2;
|
582 | 29133e9a | bellard | } |
583 | 29133e9a | bellard | if (!(n & 0x1)) { |
584 | 29133e9a | bellard | ret++; |
585 | 22ed1d34 | Blue Swirl | #if 0 /* This is not necessary as n is never 0 */
|
586 | 29133e9a | bellard | n = n >> 1;
|
587 | 22ed1d34 | Blue Swirl | #endif
|
588 | 29133e9a | bellard | } |
589 | 29133e9a | bellard | #if 0 /* This is not necessary as n is never 0 */
|
590 | 29133e9a | bellard | if (!n)
|
591 | 29133e9a | bellard | ret++;
|
592 | 29133e9a | bellard | #endif
|
593 | 29133e9a | bellard | |
594 | 29133e9a | bellard | return ret;
|
595 | 29133e9a | bellard | } |
596 | 29133e9a | bellard | |
597 | c227f099 | Anthony Liguori | pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
598 | cf6d9118 | balrog | BlockDriverState *bs, uint32_t sector_len, |
599 | 4fbd24ba | balrog | int nb_blocs, int nb_mappings, int width, |
600 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
601 | 6725070d | balrog | uint16_t id2, uint16_t id3, |
602 | 5f9fc5ad | Blue Swirl | uint16_t unlock_addr0, uint16_t unlock_addr1, |
603 | 5f9fc5ad | Blue Swirl | int be)
|
604 | 29133e9a | bellard | { |
605 | c227f099 | Anthony Liguori | pflash_t *pfl; |
606 | 4fbd24ba | balrog | int32_t chip_len; |
607 | d0e7605e | Vijay Kumar | int ret;
|
608 | 29133e9a | bellard | |
609 | 4fbd24ba | balrog | chip_len = sector_len * nb_blocs; |
610 | 29133e9a | bellard | /* XXX: to be fixed */
|
611 | 95d1f3ed | j_mayer | #if 0
|
612 | 29133e9a | bellard | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
613 | 29133e9a | bellard | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
614 | 29133e9a | bellard | return NULL;
|
615 | 95d1f3ed | j_mayer | #endif
|
616 | c227f099 | Anthony Liguori | pfl = qemu_mallocz(sizeof(pflash_t));
|
617 | 5c130f65 | pbrook | /* FIXME: Allocate ram ourselves. */
|
618 | 5c130f65 | pbrook | pfl->storage = qemu_get_ram_ptr(off); |
619 | 5f9fc5ad | Blue Swirl | if (be) {
|
620 | 5f9fc5ad | Blue Swirl | pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, |
621 | 5f9fc5ad | Blue Swirl | pflash_write_ops_be, |
622 | 5f9fc5ad | Blue Swirl | pfl); |
623 | 5f9fc5ad | Blue Swirl | } else {
|
624 | 5f9fc5ad | Blue Swirl | pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, |
625 | 5f9fc5ad | Blue Swirl | pflash_write_ops_le, |
626 | 5f9fc5ad | Blue Swirl | pfl); |
627 | 5f9fc5ad | Blue Swirl | } |
628 | 29133e9a | bellard | pfl->off = off; |
629 | 4fbd24ba | balrog | pfl->base = base; |
630 | 4fbd24ba | balrog | pfl->chip_len = chip_len; |
631 | 4fbd24ba | balrog | pfl->mappings = nb_mappings; |
632 | 4fbd24ba | balrog | pflash_register_memory(pfl, 1);
|
633 | 29133e9a | bellard | pfl->bs = bs; |
634 | 29133e9a | bellard | if (pfl->bs) {
|
635 | 29133e9a | bellard | /* read the initial flash content */
|
636 | d0e7605e | Vijay Kumar | ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
637 | d0e7605e | Vijay Kumar | if (ret < 0) { |
638 | d0e7605e | Vijay Kumar | cpu_unregister_io_memory(pfl->fl_mem); |
639 | d0e7605e | Vijay Kumar | qemu_free(pfl); |
640 | d0e7605e | Vijay Kumar | return NULL; |
641 | d0e7605e | Vijay Kumar | } |
642 | 29133e9a | bellard | } |
643 | 29133e9a | bellard | #if 0 /* XXX: there should be a bit to set up read-only,
|
644 | 29133e9a | bellard | * the same way the hardware does (with WP pin).
|
645 | 29133e9a | bellard | */
|
646 | 29133e9a | bellard | pfl->ro = 1;
|
647 | 29133e9a | bellard | #else
|
648 | 29133e9a | bellard | pfl->ro = 0;
|
649 | 29133e9a | bellard | #endif
|
650 | 29133e9a | bellard | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
651 | 29133e9a | bellard | pfl->sector_len = sector_len; |
652 | 29133e9a | bellard | pfl->width = width; |
653 | 29133e9a | bellard | pfl->wcycle = 0;
|
654 | 29133e9a | bellard | pfl->cmd = 0;
|
655 | 29133e9a | bellard | pfl->status = 0;
|
656 | 29133e9a | bellard | pfl->ident[0] = id0;
|
657 | 29133e9a | bellard | pfl->ident[1] = id1;
|
658 | 29133e9a | bellard | pfl->ident[2] = id2;
|
659 | 29133e9a | bellard | pfl->ident[3] = id3;
|
660 | 6725070d | balrog | pfl->unlock_addr[0] = unlock_addr0;
|
661 | 6725070d | balrog | pfl->unlock_addr[1] = unlock_addr1;
|
662 | 29133e9a | bellard | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
663 | 29133e9a | bellard | pfl->cfi_len = 0x52;
|
664 | 29133e9a | bellard | /* Standard "QRY" string */
|
665 | 29133e9a | bellard | pfl->cfi_table[0x10] = 'Q'; |
666 | 29133e9a | bellard | pfl->cfi_table[0x11] = 'R'; |
667 | 29133e9a | bellard | pfl->cfi_table[0x12] = 'Y'; |
668 | 29133e9a | bellard | /* Command set (AMD/Fujitsu) */
|
669 | 29133e9a | bellard | pfl->cfi_table[0x13] = 0x02; |
670 | 29133e9a | bellard | pfl->cfi_table[0x14] = 0x00; |
671 | 78556820 | edgar_igl | /* Primary extended table address */
|
672 | 78556820 | edgar_igl | pfl->cfi_table[0x15] = 0x31; |
673 | 29133e9a | bellard | pfl->cfi_table[0x16] = 0x00; |
674 | 29133e9a | bellard | /* Alternate command set (none) */
|
675 | 29133e9a | bellard | pfl->cfi_table[0x17] = 0x00; |
676 | 29133e9a | bellard | pfl->cfi_table[0x18] = 0x00; |
677 | 29133e9a | bellard | /* Alternate extended table (none) */
|
678 | 29133e9a | bellard | pfl->cfi_table[0x19] = 0x00; |
679 | 29133e9a | bellard | pfl->cfi_table[0x1A] = 0x00; |
680 | 29133e9a | bellard | /* Vcc min */
|
681 | 29133e9a | bellard | pfl->cfi_table[0x1B] = 0x27; |
682 | 29133e9a | bellard | /* Vcc max */
|
683 | 29133e9a | bellard | pfl->cfi_table[0x1C] = 0x36; |
684 | 29133e9a | bellard | /* Vpp min (no Vpp pin) */
|
685 | 29133e9a | bellard | pfl->cfi_table[0x1D] = 0x00; |
686 | 29133e9a | bellard | /* Vpp max (no Vpp pin) */
|
687 | 29133e9a | bellard | pfl->cfi_table[0x1E] = 0x00; |
688 | 29133e9a | bellard | /* Reserved */
|
689 | 29133e9a | bellard | pfl->cfi_table[0x1F] = 0x07; |
690 | 78556820 | edgar_igl | /* Timeout for min size buffer write (NA) */
|
691 | 78556820 | edgar_igl | pfl->cfi_table[0x20] = 0x00; |
692 | 29133e9a | bellard | /* Typical timeout for block erase (512 ms) */
|
693 | 29133e9a | bellard | pfl->cfi_table[0x21] = 0x09; |
694 | 29133e9a | bellard | /* Typical timeout for full chip erase (4096 ms) */
|
695 | 29133e9a | bellard | pfl->cfi_table[0x22] = 0x0C; |
696 | 29133e9a | bellard | /* Reserved */
|
697 | 29133e9a | bellard | pfl->cfi_table[0x23] = 0x01; |
698 | 78556820 | edgar_igl | /* Max timeout for buffer write (NA) */
|
699 | 78556820 | edgar_igl | pfl->cfi_table[0x24] = 0x00; |
700 | 29133e9a | bellard | /* Max timeout for block erase */
|
701 | 29133e9a | bellard | pfl->cfi_table[0x25] = 0x0A; |
702 | 29133e9a | bellard | /* Max timeout for chip erase */
|
703 | 29133e9a | bellard | pfl->cfi_table[0x26] = 0x0D; |
704 | 29133e9a | bellard | /* Device size */
|
705 | 78556820 | edgar_igl | pfl->cfi_table[0x27] = ctz32(chip_len);
|
706 | 29133e9a | bellard | /* Flash device interface (8 & 16 bits) */
|
707 | 29133e9a | bellard | pfl->cfi_table[0x28] = 0x02; |
708 | 29133e9a | bellard | pfl->cfi_table[0x29] = 0x00; |
709 | 29133e9a | bellard | /* Max number of bytes in multi-bytes write */
|
710 | 95d1f3ed | j_mayer | /* XXX: disable buffered write as it's not supported */
|
711 | 95d1f3ed | j_mayer | // pfl->cfi_table[0x2A] = 0x05;
|
712 | 95d1f3ed | j_mayer | pfl->cfi_table[0x2A] = 0x00; |
713 | 29133e9a | bellard | pfl->cfi_table[0x2B] = 0x00; |
714 | 29133e9a | bellard | /* Number of erase block regions (uniform) */
|
715 | 29133e9a | bellard | pfl->cfi_table[0x2C] = 0x01; |
716 | 29133e9a | bellard | /* Erase block region 1 */
|
717 | 29133e9a | bellard | pfl->cfi_table[0x2D] = nb_blocs - 1; |
718 | 29133e9a | bellard | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
719 | 29133e9a | bellard | pfl->cfi_table[0x2F] = sector_len >> 8; |
720 | 29133e9a | bellard | pfl->cfi_table[0x30] = sector_len >> 16; |
721 | 29133e9a | bellard | |
722 | 78556820 | edgar_igl | /* Extended */
|
723 | 78556820 | edgar_igl | pfl->cfi_table[0x31] = 'P'; |
724 | 78556820 | edgar_igl | pfl->cfi_table[0x32] = 'R'; |
725 | 78556820 | edgar_igl | pfl->cfi_table[0x33] = 'I'; |
726 | 78556820 | edgar_igl | |
727 | 78556820 | edgar_igl | pfl->cfi_table[0x34] = '1'; |
728 | 78556820 | edgar_igl | pfl->cfi_table[0x35] = '0'; |
729 | 78556820 | edgar_igl | |
730 | 78556820 | edgar_igl | pfl->cfi_table[0x36] = 0x00; |
731 | 78556820 | edgar_igl | pfl->cfi_table[0x37] = 0x00; |
732 | 78556820 | edgar_igl | pfl->cfi_table[0x38] = 0x00; |
733 | 78556820 | edgar_igl | pfl->cfi_table[0x39] = 0x00; |
734 | 78556820 | edgar_igl | |
735 | 78556820 | edgar_igl | pfl->cfi_table[0x3a] = 0x00; |
736 | 78556820 | edgar_igl | |
737 | 78556820 | edgar_igl | pfl->cfi_table[0x3b] = 0x00; |
738 | 78556820 | edgar_igl | pfl->cfi_table[0x3c] = 0x00; |
739 | 78556820 | edgar_igl | |
740 | 29133e9a | bellard | return pfl;
|
741 | 29133e9a | bellard | } |