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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | b346ff46 | bellard | /* is_jmp field values */
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25 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
26 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
27 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
28 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
29 | b346ff46 | bellard | |
30 | b346ff46 | bellard | struct TranslationBlock;
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31 | b346ff46 | bellard | |
32 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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33 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
34 | 0115be31 | pbrook | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
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35 | 0115be31 | pbrook | #define MAX_OPC_PARAM 10 |
36 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
37 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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38 | b346ff46 | bellard | |
39 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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40 | b346ff46 | bellard | |
41 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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42 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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43 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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44 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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45 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
46 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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47 | b346ff46 | bellard | |
48 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
49 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
50 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
51 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
52 | 3b46e624 | ths | |
53 | b346ff46 | bellard | #if defined(TARGET_I386)
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54 | b346ff46 | bellard | |
55 | 33417e70 | bellard | void optimize_flags_init(void); |
56 | d4e8164f | bellard | |
57 | b346ff46 | bellard | #endif
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58 | b346ff46 | bellard | |
59 | b346ff46 | bellard | extern FILE *logfile;
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60 | b346ff46 | bellard | extern int loglevel; |
61 | b346ff46 | bellard | |
62 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
63 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
64 | d07bde88 | blueswir1 | unsigned long code_gen_max_block_size(void); |
65 | 57fec1fe | bellard | void cpu_gen_init(void); |
66 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
67 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
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68 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
69 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
70 | 58fe2f10 | bellard | void *puc);
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71 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
72 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
73 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
74 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
75 | 58fe2f10 | bellard | void *puc);
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76 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
77 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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78 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
79 | 5fafdf24 | ths | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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80 | 2e12669a | bellard | int is_cpu_write_access);
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81 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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82 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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83 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
84 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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85 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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86 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
87 | 5fafdf24 | ths | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
88 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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89 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
90 | 84b7b8e7 | bellard | { |
91 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
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92 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
93 | 6ebbf390 | j_mayer | return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
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94 | 84b7b8e7 | bellard | } |
95 | d4e8164f | bellard | |
96 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
97 | d4e8164f | bellard | |
98 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
99 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
100 | 4390df51 | bellard | |
101 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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102 | 4390df51 | bellard | |
103 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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104 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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105 | 4390df51 | bellard | summary of the ranges:
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106 | 4390df51 | bellard | |
107 | 4390df51 | bellard | i386 : signed 32 bits
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108 | 4390df51 | bellard | arm : signed 26 bits
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109 | 4390df51 | bellard | ppc : signed 24 bits
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110 | 4390df51 | bellard | sparc : signed 32 bits
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111 | 4390df51 | bellard | alpha : signed 23 bits
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112 | 4390df51 | bellard | */
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113 | 4390df51 | bellard | |
114 | 4390df51 | bellard | #if defined(__alpha__)
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115 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
116 | b8076a74 | bellard | #elif defined(__ia64)
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117 | b8076a74 | bellard | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
118 | 4390df51 | bellard | #elif defined(__powerpc__)
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119 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
120 | 4390df51 | bellard | #else
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121 | 57fec1fe | bellard | /* XXX: make it dynamic on x86 */
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122 | c98baaac | bellard | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
123 | 4390df51 | bellard | #endif
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124 | 4390df51 | bellard | |
125 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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126 | d4e8164f | bellard | |
127 | 4390df51 | bellard | /* estimated block size for TB allocation */
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128 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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129 | 4390df51 | bellard | according to the host CPU */
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130 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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131 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
132 | 4390df51 | bellard | #else
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133 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
134 | 4390df51 | bellard | #endif
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135 | 4390df51 | bellard | |
136 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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137 | 4390df51 | bellard | |
138 | 57fec1fe | bellard | #if defined(__powerpc__) || defined(__x86_64__)
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139 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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140 | 4390df51 | bellard | #endif
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141 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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142 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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143 | d4e8164f | bellard | #endif
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144 | d4e8164f | bellard | |
145 | d4e8164f | bellard | typedef struct TranslationBlock { |
146 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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147 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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148 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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149 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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150 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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151 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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152 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
153 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
154 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
155 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
156 | 58fe2f10 | bellard | |
157 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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158 | 4390df51 | bellard | /* next matching tb for physical address. */
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159 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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160 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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161 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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162 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
163 | 5fafdf24 | ths | target_ulong page_addr[2];
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164 | 4390df51 | bellard | |
165 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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166 | d4e8164f | bellard | the code of this one. */
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167 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
168 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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169 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
170 | d4e8164f | bellard | #else
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171 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
172 | d4e8164f | bellard | #endif
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173 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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174 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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175 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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176 | d4e8164f | bellard | jmp_first */
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177 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
178 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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179 | d4e8164f | bellard | } TranslationBlock; |
180 | d4e8164f | bellard | |
181 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
182 | b362e5e0 | pbrook | { |
183 | b362e5e0 | pbrook | target_ulong tmp; |
184 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
185 | b362e5e0 | pbrook | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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186 | b362e5e0 | pbrook | } |
187 | b362e5e0 | pbrook | |
188 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
189 | d4e8164f | bellard | { |
190 | b362e5e0 | pbrook | target_ulong tmp; |
191 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
192 | b362e5e0 | pbrook | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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193 | b362e5e0 | pbrook | (tmp & TB_JMP_ADDR_MASK)); |
194 | d4e8164f | bellard | } |
195 | d4e8164f | bellard | |
196 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
197 | 4390df51 | bellard | { |
198 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
199 | 4390df51 | bellard | } |
200 | 4390df51 | bellard | |
201 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
202 | 0124311e | bellard | void tb_flush(CPUState *env);
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203 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
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204 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
205 | d4e8164f | bellard | |
206 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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207 | d4e8164f | bellard | |
208 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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209 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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210 | d4e8164f | bellard | |
211 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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212 | 4390df51 | bellard | |
213 | 4390df51 | bellard | #if defined(__powerpc__)
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214 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
215 | d4e8164f | bellard | { |
216 | d4e8164f | bellard | uint32_t val, *ptr; |
217 | d4e8164f | bellard | |
218 | d4e8164f | bellard | /* patch the branch destination */
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219 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
220 | d4e8164f | bellard | val = *ptr; |
221 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
222 | d4e8164f | bellard | *ptr = val; |
223 | d4e8164f | bellard | /* flush icache */
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224 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
225 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
226 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
227 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
228 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
229 | d4e8164f | bellard | } |
230 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
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231 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
232 | 4390df51 | bellard | { |
233 | 4390df51 | bellard | /* patch the branch destination */
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234 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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235 | 4390df51 | bellard | /* no need to flush icache explicitely */
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236 | 4390df51 | bellard | } |
237 | 4390df51 | bellard | #endif
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238 | d4e8164f | bellard | |
239 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
240 | 4cbb86e1 | bellard | int n, unsigned long addr) |
241 | 4cbb86e1 | bellard | { |
242 | 4cbb86e1 | bellard | unsigned long offset; |
243 | 4cbb86e1 | bellard | |
244 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
245 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
246 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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247 | 4cbb86e1 | bellard | if (offset != 0xffff) |
248 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
249 | 4cbb86e1 | bellard | } |
250 | 4cbb86e1 | bellard | |
251 | d4e8164f | bellard | #else
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252 | d4e8164f | bellard | |
253 | d4e8164f | bellard | /* set the jump target */
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254 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
255 | d4e8164f | bellard | int n, unsigned long addr) |
256 | d4e8164f | bellard | { |
257 | 95f7652d | bellard | tb->tb_next[n] = addr; |
258 | d4e8164f | bellard | } |
259 | d4e8164f | bellard | |
260 | d4e8164f | bellard | #endif
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261 | d4e8164f | bellard | |
262 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
263 | d4e8164f | bellard | TranslationBlock *tb_next) |
264 | d4e8164f | bellard | { |
265 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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266 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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267 | cf25629d | bellard | /* patch the native jump address */
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268 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
269 | 3b46e624 | ths | |
270 | cf25629d | bellard | /* add in TB jmp circular list */
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271 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
272 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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273 | cf25629d | bellard | } |
274 | d4e8164f | bellard | } |
275 | d4e8164f | bellard | |
276 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
277 | a513fe19 | bellard | |
278 | d4e8164f | bellard | #ifndef offsetof
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279 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
280 | d4e8164f | bellard | #endif
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281 | d4e8164f | bellard | |
282 | d549f7d9 | bellard | #if defined(_WIN32)
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283 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
284 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
285 | d549f7d9 | bellard | #elif defined(__APPLE__)
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286 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
287 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
288 | d549f7d9 | bellard | #else
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289 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
290 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
291 | d549f7d9 | bellard | #endif
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292 | d549f7d9 | bellard | |
293 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
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294 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
295 | 75913b72 | bellard | |
296 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
297 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
298 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
299 | 33417e70 | bellard | |
300 | 204a1b8d | ths | #if defined(__powerpc__)
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301 | d4e8164f | bellard | static inline int testandset (int *p) |
302 | d4e8164f | bellard | { |
303 | d4e8164f | bellard | int ret;
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304 | d4e8164f | bellard | __asm__ __volatile__ ( |
305 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
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306 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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307 | 02e1ec9b | bellard | " bne 1f\n"
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308 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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309 | 02e1ec9b | bellard | " bne- 0b\n"
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310 | d4e8164f | bellard | "1: "
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311 | d4e8164f | bellard | : "=&r" (ret)
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312 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
313 | d4e8164f | bellard | : "cr0", "memory"); |
314 | d4e8164f | bellard | return ret;
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315 | d4e8164f | bellard | } |
316 | 204a1b8d | ths | #elif defined(__i386__)
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317 | d4e8164f | bellard | static inline int testandset (int *p) |
318 | d4e8164f | bellard | { |
319 | 4955a2cd | bellard | long int readval = 0; |
320 | 3b46e624 | ths | |
321 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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322 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
323 | 4955a2cd | bellard | : "r" (1) |
324 | 4955a2cd | bellard | : "cc");
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325 | 4955a2cd | bellard | return readval;
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326 | d4e8164f | bellard | } |
327 | 204a1b8d | ths | #elif defined(__x86_64__)
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328 | bc51c5c9 | bellard | static inline int testandset (int *p) |
329 | bc51c5c9 | bellard | { |
330 | 4955a2cd | bellard | long int readval = 0; |
331 | 3b46e624 | ths | |
332 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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333 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
334 | 4955a2cd | bellard | : "r" (1) |
335 | 4955a2cd | bellard | : "cc");
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336 | 4955a2cd | bellard | return readval;
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337 | bc51c5c9 | bellard | } |
338 | 204a1b8d | ths | #elif defined(__s390__)
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339 | d4e8164f | bellard | static inline int testandset (int *p) |
340 | d4e8164f | bellard | { |
341 | d4e8164f | bellard | int ret;
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342 | d4e8164f | bellard | |
343 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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344 | d4e8164f | bellard | " jl 0b"
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345 | d4e8164f | bellard | : "=&d" (ret)
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346 | 5fafdf24 | ths | : "r" (1), "a" (p), "0" (*p) |
347 | d4e8164f | bellard | : "cc", "memory" ); |
348 | d4e8164f | bellard | return ret;
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349 | d4e8164f | bellard | } |
350 | 204a1b8d | ths | #elif defined(__alpha__)
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351 | 2f87c607 | bellard | static inline int testandset (int *p) |
352 | d4e8164f | bellard | { |
353 | d4e8164f | bellard | int ret;
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354 | d4e8164f | bellard | unsigned long one; |
355 | d4e8164f | bellard | |
356 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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357 | d4e8164f | bellard | " ldl_l %0,%1\n"
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358 | d4e8164f | bellard | " stl_c %2,%1\n"
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359 | d4e8164f | bellard | " beq %2,1f\n"
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360 | d4e8164f | bellard | ".subsection 2\n"
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361 | d4e8164f | bellard | "1: br 0b\n"
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362 | d4e8164f | bellard | ".previous"
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363 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
364 | d4e8164f | bellard | : "m" (*p));
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365 | d4e8164f | bellard | return ret;
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366 | d4e8164f | bellard | } |
367 | 204a1b8d | ths | #elif defined(__sparc__)
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368 | d4e8164f | bellard | static inline int testandset (int *p) |
369 | d4e8164f | bellard | { |
370 | d4e8164f | bellard | int ret;
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371 | d4e8164f | bellard | |
372 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
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373 | d4e8164f | bellard | : "=r" (ret)
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374 | d4e8164f | bellard | : "r" (p)
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375 | d4e8164f | bellard | : "memory");
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376 | d4e8164f | bellard | |
377 | d4e8164f | bellard | return (ret ? 1 : 0); |
378 | d4e8164f | bellard | } |
379 | 204a1b8d | ths | #elif defined(__arm__)
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380 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
381 | a95c6790 | bellard | { |
382 | a95c6790 | bellard | register unsigned int ret; |
383 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
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384 | a95c6790 | bellard | : "=r"(ret)
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385 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
386 | 3b46e624 | ths | |
387 | a95c6790 | bellard | return ret;
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388 | a95c6790 | bellard | } |
389 | 204a1b8d | ths | #elif defined(__mc68000)
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390 | 38e584a0 | bellard | static inline int testandset (int *p) |
391 | 38e584a0 | bellard | { |
392 | 38e584a0 | bellard | char ret;
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393 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
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394 | 38e584a0 | bellard | : "=r" (ret)
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395 | 38e584a0 | bellard | : "m" (p)
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396 | 38e584a0 | bellard | : "cc","memory"); |
397 | 4955a2cd | bellard | return ret;
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398 | 38e584a0 | bellard | } |
399 | 204a1b8d | ths | #elif defined(__ia64)
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400 | 38e584a0 | bellard | |
401 | b8076a74 | bellard | #include <ia64intrin.h> |
402 | b8076a74 | bellard | |
403 | b8076a74 | bellard | static inline int testandset (int *p) |
404 | b8076a74 | bellard | { |
405 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
406 | b8076a74 | bellard | } |
407 | 204a1b8d | ths | #elif defined(__mips__)
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408 | c4b89d18 | ths | static inline int testandset (int *p) |
409 | c4b89d18 | ths | { |
410 | c4b89d18 | ths | int ret;
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411 | c4b89d18 | ths | |
412 | c4b89d18 | ths | __asm__ __volatile__ ( |
413 | c4b89d18 | ths | " .set push \n"
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414 | c4b89d18 | ths | " .set noat \n"
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415 | c4b89d18 | ths | " .set mips2 \n"
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416 | c4b89d18 | ths | "1: li $1, 1 \n"
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417 | c4b89d18 | ths | " ll %0, %1 \n"
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418 | c4b89d18 | ths | " sc $1, %1 \n"
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419 | 976a0d0d | ths | " beqz $1, 1b \n"
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420 | c4b89d18 | ths | " .set pop "
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421 | c4b89d18 | ths | : "=r" (ret), "+R" (*p) |
422 | c4b89d18 | ths | : |
423 | c4b89d18 | ths | : "memory");
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424 | c4b89d18 | ths | |
425 | c4b89d18 | ths | return ret;
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426 | c4b89d18 | ths | } |
427 | 204a1b8d | ths | #else
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428 | 204a1b8d | ths | #error unimplemented CPU support
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429 | c4b89d18 | ths | #endif
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430 | c4b89d18 | ths | |
431 | d4e8164f | bellard | typedef int spinlock_t; |
432 | d4e8164f | bellard | |
433 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
434 | d4e8164f | bellard | |
435 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
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436 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
437 | d4e8164f | bellard | { |
438 | d4e8164f | bellard | while (testandset(lock));
|
439 | d4e8164f | bellard | } |
440 | d4e8164f | bellard | |
441 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
442 | d4e8164f | bellard | { |
443 | d4e8164f | bellard | *lock = 0;
|
444 | d4e8164f | bellard | } |
445 | d4e8164f | bellard | |
446 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
447 | d4e8164f | bellard | { |
448 | d4e8164f | bellard | return !testandset(lock);
|
449 | d4e8164f | bellard | } |
450 | 3c1cf9fa | bellard | #else
|
451 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
452 | 3c1cf9fa | bellard | { |
453 | 3c1cf9fa | bellard | } |
454 | 3c1cf9fa | bellard | |
455 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
456 | 3c1cf9fa | bellard | { |
457 | 3c1cf9fa | bellard | } |
458 | 3c1cf9fa | bellard | |
459 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
460 | 3c1cf9fa | bellard | { |
461 | 3c1cf9fa | bellard | return 1; |
462 | 3c1cf9fa | bellard | } |
463 | 3c1cf9fa | bellard | #endif
|
464 | d4e8164f | bellard | |
465 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
466 | d4e8164f | bellard | |
467 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
468 | 6e59c1db | bellard | |
469 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
470 | 6e59c1db | bellard | |
471 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
472 | 6e59c1db | bellard | void *retaddr);
|
473 | 6e59c1db | bellard | |
474 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
475 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
476 | 6e59c1db | bellard | #define env cpu_single_env
|
477 | 6e59c1db | bellard | |
478 | 6e59c1db | bellard | #define DATA_SIZE 1 |
479 | 6e59c1db | bellard | #include "softmmu_header.h" |
480 | 6e59c1db | bellard | |
481 | 6e59c1db | bellard | #define DATA_SIZE 2 |
482 | 6e59c1db | bellard | #include "softmmu_header.h" |
483 | 6e59c1db | bellard | |
484 | 6e59c1db | bellard | #define DATA_SIZE 4 |
485 | 6e59c1db | bellard | #include "softmmu_header.h" |
486 | 6e59c1db | bellard | |
487 | c27004ec | bellard | #define DATA_SIZE 8 |
488 | c27004ec | bellard | #include "softmmu_header.h" |
489 | c27004ec | bellard | |
490 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
491 | 6e59c1db | bellard | #undef MEMSUFFIX
|
492 | 6e59c1db | bellard | #undef env
|
493 | 6e59c1db | bellard | |
494 | 6e59c1db | bellard | #endif
|
495 | 4390df51 | bellard | |
496 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
497 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
498 | 4390df51 | bellard | { |
499 | 4390df51 | bellard | return addr;
|
500 | 4390df51 | bellard | } |
501 | 4390df51 | bellard | #else
|
502 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
503 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
504 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
505 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
506 | 4390df51 | bellard | { |
507 | 6ebbf390 | j_mayer | int mmu_idx, index, pd;
|
508 | 4390df51 | bellard | |
509 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
510 | 6ebbf390 | j_mayer | mmu_idx = cpu_mmu_index(env); |
511 | 6ebbf390 | j_mayer | if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
|
512 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
513 | c27004ec | bellard | ldub_code(addr); |
514 | c27004ec | bellard | } |
515 | 6ebbf390 | j_mayer | pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; |
516 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
517 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
518 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
519 | 6c36d3fa | blueswir1 | #else
|
520 | 36d23958 | ths | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
521 | 6c36d3fa | blueswir1 | #endif
|
522 | 4390df51 | bellard | } |
523 | 6ebbf390 | j_mayer | return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base; |
524 | 4390df51 | bellard | } |
525 | 4390df51 | bellard | #endif
|
526 | 9df217a3 | bellard | |
527 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
528 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
529 | f32fc648 | bellard | |
530 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
531 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
532 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
533 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
534 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
535 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
536 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
537 | f32fc648 | bellard | void kqemu_record_dump(void); |
538 | 9df217a3 | bellard | |
539 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
540 | 9df217a3 | bellard | { |
541 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
542 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
|
543 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
544 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
545 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
546 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
|
547 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
548 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
549 | 9df217a3 | bellard | } |
550 | 9df217a3 | bellard | |
551 | 9df217a3 | bellard | #endif |