root / hw / versatilepb.c @ 24c7b0e3
History | View | Annotate | Download (8.3 kB)
1 | cdbdb648 | pbrook | /*
|
---|---|---|---|
2 | 16406950 | pbrook | * ARM Versatile Platform/Application Baseboard System emulation.
|
3 | cdbdb648 | pbrook | *
|
4 | cdbdb648 | pbrook | * Copyright (c) 2005-2006 CodeSourcery.
|
5 | cdbdb648 | pbrook | * Written by Paul Brook
|
6 | cdbdb648 | pbrook | *
|
7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
|
8 | cdbdb648 | pbrook | */
|
9 | cdbdb648 | pbrook | |
10 | cdbdb648 | pbrook | #include "vl.h" |
11 | cdbdb648 | pbrook | #include "arm_pic.h" |
12 | cdbdb648 | pbrook | |
13 | cdbdb648 | pbrook | /* Primary interrupt controller. */
|
14 | cdbdb648 | pbrook | |
15 | cdbdb648 | pbrook | typedef struct vpb_sic_state |
16 | cdbdb648 | pbrook | { |
17 | cdbdb648 | pbrook | arm_pic_handler handler; |
18 | cdbdb648 | pbrook | uint32_t base; |
19 | cdbdb648 | pbrook | uint32_t level; |
20 | cdbdb648 | pbrook | uint32_t mask; |
21 | cdbdb648 | pbrook | uint32_t pic_enable; |
22 | cdbdb648 | pbrook | void *parent;
|
23 | cdbdb648 | pbrook | int irq;
|
24 | cdbdb648 | pbrook | } vpb_sic_state; |
25 | cdbdb648 | pbrook | |
26 | cdbdb648 | pbrook | static void vpb_sic_update(vpb_sic_state *s) |
27 | cdbdb648 | pbrook | { |
28 | cdbdb648 | pbrook | uint32_t flags; |
29 | cdbdb648 | pbrook | |
30 | cdbdb648 | pbrook | flags = s->level & s->mask; |
31 | cdbdb648 | pbrook | pic_set_irq_new(s->parent, s->irq, flags != 0);
|
32 | cdbdb648 | pbrook | } |
33 | cdbdb648 | pbrook | |
34 | cdbdb648 | pbrook | static void vpb_sic_update_pic(vpb_sic_state *s) |
35 | cdbdb648 | pbrook | { |
36 | cdbdb648 | pbrook | int i;
|
37 | cdbdb648 | pbrook | uint32_t mask; |
38 | cdbdb648 | pbrook | |
39 | cdbdb648 | pbrook | for (i = 21; i <= 30; i++) { |
40 | cdbdb648 | pbrook | mask = 1u << i;
|
41 | cdbdb648 | pbrook | if (!(s->pic_enable & mask))
|
42 | cdbdb648 | pbrook | continue;
|
43 | cdbdb648 | pbrook | pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
|
44 | cdbdb648 | pbrook | } |
45 | cdbdb648 | pbrook | } |
46 | cdbdb648 | pbrook | |
47 | cdbdb648 | pbrook | static void vpb_sic_set_irq(void *opaque, int irq, int level) |
48 | cdbdb648 | pbrook | { |
49 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
50 | cdbdb648 | pbrook | if (level)
|
51 | cdbdb648 | pbrook | s->level |= 1u << irq;
|
52 | cdbdb648 | pbrook | else
|
53 | cdbdb648 | pbrook | s->level &= ~(1u << irq);
|
54 | cdbdb648 | pbrook | if (s->pic_enable & (1u << irq)) |
55 | cdbdb648 | pbrook | pic_set_irq_new(s->parent, irq, level); |
56 | cdbdb648 | pbrook | vpb_sic_update(s); |
57 | cdbdb648 | pbrook | } |
58 | cdbdb648 | pbrook | |
59 | cdbdb648 | pbrook | static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) |
60 | cdbdb648 | pbrook | { |
61 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
62 | cdbdb648 | pbrook | |
63 | cdbdb648 | pbrook | offset -= s->base; |
64 | cdbdb648 | pbrook | switch (offset >> 2) { |
65 | cdbdb648 | pbrook | case 0: /* STATUS */ |
66 | cdbdb648 | pbrook | return s->level & s->mask;
|
67 | cdbdb648 | pbrook | case 1: /* RAWSTAT */ |
68 | cdbdb648 | pbrook | return s->level;
|
69 | cdbdb648 | pbrook | case 2: /* ENABLE */ |
70 | cdbdb648 | pbrook | return s->mask;
|
71 | cdbdb648 | pbrook | case 4: /* SOFTINT */ |
72 | cdbdb648 | pbrook | return s->level & 1; |
73 | cdbdb648 | pbrook | case 8: /* PICENABLE */ |
74 | cdbdb648 | pbrook | return s->pic_enable;
|
75 | cdbdb648 | pbrook | default:
|
76 | e69954b9 | pbrook | printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
77 | cdbdb648 | pbrook | return 0; |
78 | cdbdb648 | pbrook | } |
79 | cdbdb648 | pbrook | } |
80 | cdbdb648 | pbrook | |
81 | cdbdb648 | pbrook | static void vpb_sic_write(void *opaque, target_phys_addr_t offset, |
82 | cdbdb648 | pbrook | uint32_t value) |
83 | cdbdb648 | pbrook | { |
84 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
85 | cdbdb648 | pbrook | offset -= s->base; |
86 | cdbdb648 | pbrook | |
87 | cdbdb648 | pbrook | switch (offset >> 2) { |
88 | cdbdb648 | pbrook | case 2: /* ENSET */ |
89 | cdbdb648 | pbrook | s->mask |= value; |
90 | cdbdb648 | pbrook | break;
|
91 | cdbdb648 | pbrook | case 3: /* ENCLR */ |
92 | cdbdb648 | pbrook | s->mask &= ~value; |
93 | cdbdb648 | pbrook | break;
|
94 | cdbdb648 | pbrook | case 4: /* SOFTINTSET */ |
95 | cdbdb648 | pbrook | if (value)
|
96 | cdbdb648 | pbrook | s->mask |= 1;
|
97 | cdbdb648 | pbrook | break;
|
98 | cdbdb648 | pbrook | case 5: /* SOFTINTCLR */ |
99 | cdbdb648 | pbrook | if (value)
|
100 | cdbdb648 | pbrook | s->mask &= ~1u;
|
101 | cdbdb648 | pbrook | break;
|
102 | cdbdb648 | pbrook | case 8: /* PICENSET */ |
103 | cdbdb648 | pbrook | s->pic_enable |= (value & 0x7fe00000);
|
104 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
105 | cdbdb648 | pbrook | break;
|
106 | cdbdb648 | pbrook | case 9: /* PICENCLR */ |
107 | cdbdb648 | pbrook | s->pic_enable &= ~value; |
108 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
109 | cdbdb648 | pbrook | break;
|
110 | cdbdb648 | pbrook | default:
|
111 | e69954b9 | pbrook | printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
112 | cdbdb648 | pbrook | return;
|
113 | cdbdb648 | pbrook | } |
114 | cdbdb648 | pbrook | vpb_sic_update(s); |
115 | cdbdb648 | pbrook | } |
116 | cdbdb648 | pbrook | |
117 | cdbdb648 | pbrook | static CPUReadMemoryFunc *vpb_sic_readfn[] = {
|
118 | cdbdb648 | pbrook | vpb_sic_read, |
119 | cdbdb648 | pbrook | vpb_sic_read, |
120 | cdbdb648 | pbrook | vpb_sic_read |
121 | cdbdb648 | pbrook | }; |
122 | cdbdb648 | pbrook | |
123 | cdbdb648 | pbrook | static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
|
124 | cdbdb648 | pbrook | vpb_sic_write, |
125 | cdbdb648 | pbrook | vpb_sic_write, |
126 | cdbdb648 | pbrook | vpb_sic_write |
127 | cdbdb648 | pbrook | }; |
128 | cdbdb648 | pbrook | |
129 | cdbdb648 | pbrook | static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq) |
130 | cdbdb648 | pbrook | { |
131 | cdbdb648 | pbrook | vpb_sic_state *s; |
132 | cdbdb648 | pbrook | int iomemtype;
|
133 | cdbdb648 | pbrook | |
134 | cdbdb648 | pbrook | s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
|
135 | cdbdb648 | pbrook | if (!s)
|
136 | cdbdb648 | pbrook | return NULL; |
137 | cdbdb648 | pbrook | s->handler = vpb_sic_set_irq; |
138 | cdbdb648 | pbrook | s->base = base; |
139 | cdbdb648 | pbrook | s->parent = parent; |
140 | cdbdb648 | pbrook | s->irq = irq; |
141 | cdbdb648 | pbrook | iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
|
142 | cdbdb648 | pbrook | vpb_sic_writefn, s); |
143 | cdbdb648 | pbrook | cpu_register_physical_memory(base, 0x00000fff, iomemtype);
|
144 | cdbdb648 | pbrook | /* ??? Save/restore. */
|
145 | cdbdb648 | pbrook | return s;
|
146 | cdbdb648 | pbrook | } |
147 | cdbdb648 | pbrook | |
148 | cdbdb648 | pbrook | /* Board init. */
|
149 | cdbdb648 | pbrook | |
150 | 16406950 | pbrook | /* The AB and PB boards both use the same core, just with different
|
151 | 16406950 | pbrook | peripherans and expansion busses. For now we emulate a subset of the
|
152 | 16406950 | pbrook | PB peripherals and just change the board ID. */
|
153 | cdbdb648 | pbrook | |
154 | 16406950 | pbrook | static void versatile_init(int ram_size, int vga_ram_size, int boot_device, |
155 | cdbdb648 | pbrook | DisplayState *ds, const char **fd_filename, int snapshot, |
156 | cdbdb648 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
157 | 3371d272 | pbrook | const char *initrd_filename, const char *cpu_model, |
158 | 3371d272 | pbrook | int board_id)
|
159 | cdbdb648 | pbrook | { |
160 | cdbdb648 | pbrook | CPUState *env; |
161 | cdbdb648 | pbrook | void *pic;
|
162 | cdbdb648 | pbrook | void *sic;
|
163 | 7d8406be | pbrook | void *scsi_hba;
|
164 | 502a5395 | pbrook | PCIBus *pci_bus; |
165 | 502a5395 | pbrook | NICInfo *nd; |
166 | 502a5395 | pbrook | int n;
|
167 | 502a5395 | pbrook | int done_smc = 0; |
168 | cdbdb648 | pbrook | |
169 | cdbdb648 | pbrook | env = cpu_init(); |
170 | 3371d272 | pbrook | if (!cpu_model)
|
171 | 3371d272 | pbrook | cpu_model = "arm926";
|
172 | 3371d272 | pbrook | cpu_arm_set_model(env, cpu_model); |
173 | cdbdb648 | pbrook | /* ??? RAM shoud repeat to fill physical memory space. */
|
174 | cdbdb648 | pbrook | /* SDRAM at address zero. */
|
175 | cdbdb648 | pbrook | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
176 | cdbdb648 | pbrook | |
177 | e69954b9 | pbrook | arm_sysctl_init(0x10000000, 0x41007004); |
178 | cdbdb648 | pbrook | pic = arm_pic_init_cpu(env); |
179 | cdbdb648 | pbrook | pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
|
180 | cdbdb648 | pbrook | sic = vpb_sic_init(0x10003000, pic, 31); |
181 | cdbdb648 | pbrook | pl050_init(0x10006000, sic, 3, 0); |
182 | cdbdb648 | pbrook | pl050_init(0x10007000, sic, 4, 1); |
183 | cdbdb648 | pbrook | |
184 | e69954b9 | pbrook | pci_bus = pci_vpb_init(sic, 27, 0); |
185 | 502a5395 | pbrook | /* The Versatile PCI bridge does not provide access to PCI IO space,
|
186 | 502a5395 | pbrook | so many of the qemu PCI devices are not useable. */
|
187 | 502a5395 | pbrook | for(n = 0; n < nb_nics; n++) { |
188 | 502a5395 | pbrook | nd = &nd_table[n]; |
189 | 502a5395 | pbrook | if (!nd->model)
|
190 | 502a5395 | pbrook | nd->model = done_smc ? "rtl8139" : "smc91c111"; |
191 | 502a5395 | pbrook | if (strcmp(nd->model, "smc91c111") == 0) { |
192 | 502a5395 | pbrook | smc91c111_init(nd, 0x10010000, sic, 25); |
193 | cdbdb648 | pbrook | } else {
|
194 | abcebc7e | ths | pci_nic_init(pci_bus, nd, -1);
|
195 | cdbdb648 | pbrook | } |
196 | cdbdb648 | pbrook | } |
197 | 0d92ed30 | pbrook | if (usb_enabled) {
|
198 | e24ad6f1 | pbrook | usb_ohci_init_pci(pci_bus, 3, -1); |
199 | 0d92ed30 | pbrook | } |
200 | 7d8406be | pbrook | scsi_hba = lsi_scsi_init(pci_bus, -1);
|
201 | 7d8406be | pbrook | for (n = 0; n < MAX_DISKS; n++) { |
202 | 7d8406be | pbrook | if (bs_table[n]) {
|
203 | 7d8406be | pbrook | lsi_scsi_attach(scsi_hba, bs_table[n], n); |
204 | 7d8406be | pbrook | } |
205 | 7d8406be | pbrook | } |
206 | cdbdb648 | pbrook | |
207 | cdbdb648 | pbrook | pl011_init(0x101f1000, pic, 12, serial_hds[0]); |
208 | cdbdb648 | pbrook | pl011_init(0x101f2000, pic, 13, serial_hds[1]); |
209 | cdbdb648 | pbrook | pl011_init(0x101f3000, pic, 14, serial_hds[2]); |
210 | cdbdb648 | pbrook | pl011_init(0x10009000, sic, 6, serial_hds[3]); |
211 | cdbdb648 | pbrook | |
212 | e69954b9 | pbrook | pl080_init(0x10130000, pic, 17, 8); |
213 | cdbdb648 | pbrook | sp804_init(0x101e2000, pic, 4); |
214 | cdbdb648 | pbrook | sp804_init(0x101e3000, pic, 5); |
215 | cdbdb648 | pbrook | |
216 | cdbdb648 | pbrook | /* The versatile/PB actually has a modified Color LCD controller
|
217 | cdbdb648 | pbrook | that includes hardware cursor support from the PL111. */
|
218 | cdbdb648 | pbrook | pl110_init(ds, 0x10120000, pic, 16, 1); |
219 | cdbdb648 | pbrook | |
220 | 16406950 | pbrook | /* Memory map for Versatile/PB: */
|
221 | cdbdb648 | pbrook | /* 0x10000000 System registers. */
|
222 | cdbdb648 | pbrook | /* 0x10001000 PCI controller config registers. */
|
223 | cdbdb648 | pbrook | /* 0x10002000 Serial bus interface. */
|
224 | cdbdb648 | pbrook | /* 0x10003000 Secondary interrupt controller. */
|
225 | cdbdb648 | pbrook | /* 0x10004000 AACI (audio). */
|
226 | cdbdb648 | pbrook | /* 0x10005000 MMCI0. */
|
227 | cdbdb648 | pbrook | /* 0x10006000 KMI0 (keyboard). */
|
228 | cdbdb648 | pbrook | /* 0x10007000 KMI1 (mouse). */
|
229 | cdbdb648 | pbrook | /* 0x10008000 Character LCD Interface. */
|
230 | cdbdb648 | pbrook | /* 0x10009000 UART3. */
|
231 | cdbdb648 | pbrook | /* 0x1000a000 Smart card 1. */
|
232 | cdbdb648 | pbrook | /* 0x1000b000 MMCI1. */
|
233 | cdbdb648 | pbrook | /* 0x10010000 Ethernet. */
|
234 | cdbdb648 | pbrook | /* 0x10020000 USB. */
|
235 | cdbdb648 | pbrook | /* 0x10100000 SSMC. */
|
236 | cdbdb648 | pbrook | /* 0x10110000 MPMC. */
|
237 | cdbdb648 | pbrook | /* 0x10120000 CLCD Controller. */
|
238 | cdbdb648 | pbrook | /* 0x10130000 DMA Controller. */
|
239 | cdbdb648 | pbrook | /* 0x10140000 Vectored interrupt controller. */
|
240 | cdbdb648 | pbrook | /* 0x101d0000 AHB Monitor Interface. */
|
241 | cdbdb648 | pbrook | /* 0x101e0000 System Controller. */
|
242 | cdbdb648 | pbrook | /* 0x101e1000 Watchdog Interface. */
|
243 | cdbdb648 | pbrook | /* 0x101e2000 Timer 0/1. */
|
244 | cdbdb648 | pbrook | /* 0x101e3000 Timer 2/3. */
|
245 | cdbdb648 | pbrook | /* 0x101e4000 GPIO port 0. */
|
246 | cdbdb648 | pbrook | /* 0x101e5000 GPIO port 1. */
|
247 | cdbdb648 | pbrook | /* 0x101e6000 GPIO port 2. */
|
248 | cdbdb648 | pbrook | /* 0x101e7000 GPIO port 3. */
|
249 | cdbdb648 | pbrook | /* 0x101e8000 RTC. */
|
250 | cdbdb648 | pbrook | /* 0x101f0000 Smart card 0. */
|
251 | cdbdb648 | pbrook | /* 0x101f1000 UART0. */
|
252 | cdbdb648 | pbrook | /* 0x101f2000 UART1. */
|
253 | cdbdb648 | pbrook | /* 0x101f3000 UART2. */
|
254 | cdbdb648 | pbrook | /* 0x101f4000 SSPI. */
|
255 | cdbdb648 | pbrook | |
256 | daf90626 | pbrook | arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline, |
257 | 16406950 | pbrook | initrd_filename, board_id); |
258 | 16406950 | pbrook | } |
259 | 16406950 | pbrook | |
260 | 16406950 | pbrook | static void vpb_init(int ram_size, int vga_ram_size, int boot_device, |
261 | 16406950 | pbrook | DisplayState *ds, const char **fd_filename, int snapshot, |
262 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
263 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
264 | 16406950 | pbrook | { |
265 | 16406950 | pbrook | versatile_init(ram_size, vga_ram_size, boot_device, |
266 | 16406950 | pbrook | ds, fd_filename, snapshot, |
267 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
268 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x183);
|
269 | 16406950 | pbrook | } |
270 | 16406950 | pbrook | |
271 | 16406950 | pbrook | static void vab_init(int ram_size, int vga_ram_size, int boot_device, |
272 | 16406950 | pbrook | DisplayState *ds, const char **fd_filename, int snapshot, |
273 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
274 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
275 | 16406950 | pbrook | { |
276 | 16406950 | pbrook | versatile_init(ram_size, vga_ram_size, boot_device, |
277 | 16406950 | pbrook | ds, fd_filename, snapshot, |
278 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
279 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x25e);
|
280 | cdbdb648 | pbrook | } |
281 | cdbdb648 | pbrook | |
282 | cdbdb648 | pbrook | QEMUMachine versatilepb_machine = { |
283 | cdbdb648 | pbrook | "versatilepb",
|
284 | cdbdb648 | pbrook | "ARM Versatile/PB (ARM926EJ-S)",
|
285 | cdbdb648 | pbrook | vpb_init, |
286 | cdbdb648 | pbrook | }; |
287 | 16406950 | pbrook | |
288 | 16406950 | pbrook | QEMUMachine versatileab_machine = { |
289 | 16406950 | pbrook | "versatileab",
|
290 | 16406950 | pbrook | "ARM Versatile/AB (ARM926EJ-S)",
|
291 | 16406950 | pbrook | vab_init, |
292 | 16406950 | pbrook | }; |