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/*
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* SH7750 device
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include <assert.h> |
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#include "vl.h" |
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#include "sh7750_regs.h" |
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#include "sh7750_regnames.h" |
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typedef struct { |
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uint8_t data[16];
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uint8_t length; /* Number of characters in the FIFO */
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uint8_t write_idx; /* Index of first character to write */
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uint8_t read_idx; /* Index of first character to read */
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} fifo; |
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#define NB_DEVICES 4 |
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typedef struct SH7750State { |
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/* CPU */
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CPUSH4State *cpu; |
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/* Peripheral frequency in Hz */
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uint32_t periph_freq; |
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/* SDRAM controller */
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uint16_t rfcr; |
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/* First serial port */
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CharDriverState *serial1; |
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uint8_t scscr1; |
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uint8_t scsmr1; |
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uint8_t scbrr1; |
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uint8_t scssr1; |
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uint8_t scssr1_read; |
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uint8_t sctsr1; |
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uint8_t sctsr1_loaded; |
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uint8_t sctdr1; |
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uint8_t scrdr1; |
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/* Second serial port */
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CharDriverState *serial2; |
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uint16_t sclsr2; |
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uint16_t scscr2; |
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uint16_t scfcr2; |
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uint16_t scfsr2; |
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uint16_t scsmr2; |
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uint8_t scbrr2; |
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fifo serial2_receive_fifo; |
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fifo serial2_transmit_fifo; |
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/* Timers */
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uint8_t tstr; |
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/* Timer 0 */
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QEMUTimer *timer0; |
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uint16_t tcr0; |
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uint32_t tcor0; |
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uint32_t tcnt0; |
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/* IO ports */
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uint16_t gpioic; |
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uint32_t pctra; |
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uint32_t pctrb; |
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uint16_t portdira; /* Cached */
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uint16_t portpullupa; /* Cached */
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uint16_t portdirb; /* Cached */
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uint16_t portpullupb; /* Cached */
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uint16_t pdtra; |
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uint16_t pdtrb; |
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uint16_t periph_pdtra; /* Imposed by the peripherals */
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uint16_t periph_portdira; /* Direction seen from the peripherals */
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uint16_t periph_pdtrb; /* Imposed by the peripherals */
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uint16_t periph_portdirb; /* Direction seen from the peripherals */
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sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
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/* Cache */
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uint32_t ccr; |
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} SH7750State; |
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|
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/**********************************************************************
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Timers
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**********************************************************************/
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|
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/* XXXXX At this time, timer0 works in underflow only mode, that is
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the value of tcnt0 is read at alarm computation time and cannot
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be read back by the guest OS */
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|
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static void start_timer0(SH7750State * s) |
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{ |
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uint64_t now, next, prescaler; |
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if ((s->tcr0 & 6) == 6) { |
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fprintf(stderr, "rtc clock for timer 0 not supported\n");
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assert(0);
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} |
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if ((s->tcr0 & 7) == 5) { |
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fprintf(stderr, "timer 0 configuration not supported\n");
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assert(0);
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} |
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if ((s->tcr0 & 4) == 4) |
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prescaler = 1024;
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else
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prescaler = 4 << (s->tcr0 & 3); |
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now = qemu_get_clock(vm_clock); |
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/* XXXXX */
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next = |
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now + muldiv64(prescaler * s->tcnt0, ticks_per_sec, |
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s->periph_freq); |
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if (next == now)
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next = now + 1;
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fprintf(stderr, "now=%016" PRIx64 ", next=%016" PRIx64 "\n", now, next); |
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fprintf(stderr, "timer will underflow in %f seconds\n",
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(float) (next - now) / (float) ticks_per_sec); |
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qemu_mod_timer(s->timer0, next); |
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} |
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static void timer_start_changed(SH7750State * s) |
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{ |
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if (s->tstr & SH7750_TSTR_STR0) {
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start_timer0(s); |
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} else {
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fprintf(stderr, "timer 0 is stopped\n");
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qemu_del_timer(s->timer0); |
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} |
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} |
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static void timer0_cb(void *opaque) |
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{ |
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SH7750State *s = opaque; |
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s->tcnt0 = (uint32_t) 0; /* XXXXX */ |
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if (--s->tcnt0 == (uint32_t) - 1) { |
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fprintf(stderr, "timer 0 underflow\n");
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s->tcnt0 = s->tcor0; |
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s->tcr0 |= SH7750_TCR_UNF; |
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if (s->tcr0 & SH7750_TCR_UNIE) {
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fprintf(stderr, |
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"interrupt generation for timer 0 not supported\n");
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assert(0);
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} |
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} |
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start_timer0(s); |
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} |
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static void init_timers(SH7750State * s) |
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{ |
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s->tcor0 = 0xffffffff;
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s->tcnt0 = 0xffffffff;
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s->timer0 = qemu_new_timer(vm_clock, &timer0_cb, s); |
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} |
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/**********************************************************************
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First serial port
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**********************************************************************/
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static int serial1_can_receive(void *opaque) |
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{ |
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SH7750State *s = opaque; |
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return s->scscr1 & SH7750_SCSCR_RE;
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} |
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static void serial1_receive_char(SH7750State * s, uint8_t c) |
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{ |
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if (s->scssr1 & SH7750_SCSSR1_RDRF) {
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s->scssr1 |= SH7750_SCSSR1_ORER; |
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return;
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} |
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s->scrdr1 = c; |
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s->scssr1 |= SH7750_SCSSR1_RDRF; |
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} |
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static void serial1_receive(void *opaque, const uint8_t * buf, int size) |
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{ |
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SH7750State *s = opaque; |
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int i;
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for (i = 0; i < size; i++) { |
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serial1_receive_char(s, buf[i]); |
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} |
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} |
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static void serial1_event(void *opaque, int event) |
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{ |
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assert(0);
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} |
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static void serial1_maybe_send(SH7750State * s) |
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{ |
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uint8_t c; |
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if (s->scssr1 & SH7750_SCSSR1_TDRE)
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return;
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c = s->sctdr1; |
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s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND; |
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if (s->scscr1 & SH7750_SCSCR_TIE) {
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fprintf(stderr, "interrupts for serial port 1 not implemented\n");
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assert(0);
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} |
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/* XXXXX Check for errors in write */
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qemu_chr_write(s->serial1, &c, 1);
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} |
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static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value) |
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{ |
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uint8_t new_flags; |
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/* If transmit disable, TDRE and TEND stays up */
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if ((s->scscr1 & SH7750_SCSCR_TE) == 0) { |
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mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND; |
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} |
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/* Only clear bits which have been read before and do not set any bit
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in the flags */
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new_flags = s->scssr1 & ~s->scssr1_read; /* Preserve unread flags */
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new_flags &= mem_value | ~s->scssr1_read; /* Clear read flags */
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s->scssr1 = (new_flags & 0xf8) | (mem_value & 1); |
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s->scssr1_read &= mem_value; |
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/* If TDRE has been cleared, TEND will also be cleared */
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if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) { |
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s->scssr1 &= ~SH7750_SCSSR1_TEND; |
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} |
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/* Check for transmission to start */
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serial1_maybe_send(s); |
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} |
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static void serial1_update_parameters(SH7750State * s) |
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{ |
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QEMUSerialSetParams ssp; |
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if (s->scsmr1 & SH7750_SCSMR_CHR_7)
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ssp.data_bits = 7;
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else
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ssp.data_bits = 8;
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if (s->scsmr1 & SH7750_SCSMR_PE) {
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if (s->scsmr1 & SH7750_SCSMR_PM_ODD)
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ssp.parity = 'O';
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else
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ssp.parity = 'E';
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} else
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ssp.parity = 'N';
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if (s->scsmr1 & SH7750_SCSMR_STOP_2)
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ssp.stop_bits = 2;
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else
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ssp.stop_bits = 1;
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fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1);
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ssp.speed = s->periph_freq / |
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(32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1; |
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fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
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ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed); |
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qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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} |
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static void scscr1_changed(SH7750State * s) |
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{ |
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if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
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if (!s->serial1) {
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fprintf(stderr, "serial port 1 not bound to anything\n");
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assert(0);
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} |
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serial1_update_parameters(s); |
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} |
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if ((s->scscr1 & SH7750_SCSCR_RE) == 0) { |
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s->scssr1 |= SH7750_SCSSR1_TDRE; |
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} |
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} |
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static void init_serial1(SH7750State * s, int serial_nb) |
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{ |
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CharDriverState *chr; |
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s->scssr1 = 0x84;
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chr = serial_hds[serial_nb]; |
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if (!chr) {
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fprintf(stderr, |
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"no serial port associated to SH7750 first serial port\n");
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return;
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} |
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s->serial1 = chr; |
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qemu_chr_add_handlers(chr, serial1_can_receive, |
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serial1_receive, serial1_event, s); |
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} |
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|
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/**********************************************************************
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Second serial port
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**********************************************************************/
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static int serial2_can_receive(void *opaque) |
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{ |
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SH7750State *s = opaque; |
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static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 }; |
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return s->serial2_receive_fifo.length <
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max_fifo_size[(s->scfcr2 >> 9) & 7]; |
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} |
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static void serial2_adjust_receive_flags(SH7750State * s) |
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{ |
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static uint8_t max_fifo_size[] = { 1, 4, 8, 14 }; |
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/* XXXXX Add interrupt generation */
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if (s->serial2_receive_fifo.length >=
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max_fifo_size[(s->scfcr2 >> 7) & 3]) { |
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s->scfsr2 |= SH7750_SCFSR2_RDF; |
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s->scfsr2 &= ~SH7750_SCFSR2_DR; |
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} else {
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s->scfsr2 &= ~SH7750_SCFSR2_RDF; |
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if (s->serial2_receive_fifo.length > 0) |
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s->scfsr2 |= SH7750_SCFSR2_DR; |
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else
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s->scfsr2 &= ~SH7750_SCFSR2_DR; |
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} |
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} |
336 |
|
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static void serial2_append_char(SH7750State * s, uint8_t c) |
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{ |
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if (s->serial2_receive_fifo.length == 16) { |
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/* Overflow */
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s->sclsr2 |= SH7750_SCLSR2_ORER; |
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return;
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} |
344 |
|
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s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c; |
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s->serial2_receive_fifo.length++; |
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serial2_adjust_receive_flags(s); |
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} |
349 |
|
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static void serial2_receive(void *opaque, const uint8_t * buf, int size) |
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{ |
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SH7750State *s = opaque; |
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int i;
|
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|
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for (i = 0; i < size; i++) |
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serial2_append_char(s, buf[i]); |
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} |
358 |
|
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static void serial2_event(void *opaque, int event) |
360 |
{ |
361 |
/* XXXXX */
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assert(0);
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} |
364 |
|
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static void serial2_update_parameters(SH7750State * s) |
366 |
{ |
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QEMUSerialSetParams ssp; |
368 |
|
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if (s->scsmr2 & SH7750_SCSMR_CHR_7)
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ssp.data_bits = 7;
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else
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ssp.data_bits = 8;
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if (s->scsmr2 & SH7750_SCSMR_PE) {
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if (s->scsmr2 & SH7750_SCSMR_PM_ODD)
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ssp.parity = 'O';
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else
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ssp.parity = 'E';
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} else
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ssp.parity = 'N';
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if (s->scsmr2 & SH7750_SCSMR_STOP_2)
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ssp.stop_bits = 2;
|
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else
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ssp.stop_bits = 1;
|
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fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2);
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ssp.speed = s->periph_freq / |
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(32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1; |
387 |
fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
|
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ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed); |
389 |
qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
390 |
} |
391 |
|
392 |
static void scscr2_changed(SH7750State * s) |
393 |
{ |
394 |
if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
|
395 |
if (!s->serial2) {
|
396 |
fprintf(stderr, "serial port 2 not bound to anything\n");
|
397 |
assert(0);
|
398 |
} |
399 |
serial2_update_parameters(s); |
400 |
} |
401 |
} |
402 |
|
403 |
static void init_serial2(SH7750State * s, int serial_nb) |
404 |
{ |
405 |
CharDriverState *chr; |
406 |
|
407 |
s->scfsr2 = 0x0060;
|
408 |
|
409 |
chr = serial_hds[serial_nb]; |
410 |
if (!chr) {
|
411 |
fprintf(stderr, |
412 |
"no serial port associated to SH7750 second serial port\n");
|
413 |
return;
|
414 |
} |
415 |
|
416 |
s->serial2 = chr; |
417 |
qemu_chr_add_handlers(chr, serial2_can_receive, |
418 |
serial2_receive, serial1_event, s); |
419 |
} |
420 |
|
421 |
static void init_serial_ports(SH7750State * s) |
422 |
{ |
423 |
init_serial1(s, 0);
|
424 |
init_serial2(s, 1);
|
425 |
} |
426 |
|
427 |
/**********************************************************************
|
428 |
I/O ports
|
429 |
**********************************************************************/
|
430 |
|
431 |
int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
|
432 |
{ |
433 |
int i;
|
434 |
|
435 |
for (i = 0; i < NB_DEVICES; i++) { |
436 |
if (s->devices[i] == NULL) { |
437 |
s->devices[i] = device; |
438 |
return 0; |
439 |
} |
440 |
} |
441 |
return -1; |
442 |
} |
443 |
|
444 |
static uint16_t portdir(uint32_t v)
|
445 |
{ |
446 |
#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) |
447 |
return
|
448 |
EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | |
449 |
EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | |
450 |
EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | |
451 |
EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | |
452 |
EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | |
453 |
EVENPORTMASK(0);
|
454 |
} |
455 |
|
456 |
static uint16_t portpullup(uint32_t v)
|
457 |
{ |
458 |
#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) |
459 |
return
|
460 |
ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | |
461 |
ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | |
462 |
ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | |
463 |
ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | |
464 |
ODDPORTMASK(1) | ODDPORTMASK(0); |
465 |
} |
466 |
|
467 |
static uint16_t porta_lines(SH7750State * s)
|
468 |
{ |
469 |
return (s->portdira & s->pdtra) | /* CPU */ |
470 |
(s->periph_portdira & s->periph_pdtra) | /* Peripherals */
|
471 |
(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
|
472 |
} |
473 |
|
474 |
static uint16_t portb_lines(SH7750State * s)
|
475 |
{ |
476 |
return (s->portdirb & s->pdtrb) | /* CPU */ |
477 |
(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
|
478 |
(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
|
479 |
} |
480 |
|
481 |
static void gen_port_interrupts(SH7750State * s) |
482 |
{ |
483 |
/* XXXXX interrupts not generated */
|
484 |
} |
485 |
|
486 |
static void porta_changed(SH7750State * s, uint16_t prev) |
487 |
{ |
488 |
uint16_t currenta, changes; |
489 |
int i, r = 0; |
490 |
|
491 |
#if 0
|
492 |
fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
|
493 |
prev, porta_lines(s));
|
494 |
fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
|
495 |
#endif
|
496 |
currenta = porta_lines(s); |
497 |
if (currenta == prev)
|
498 |
return;
|
499 |
changes = currenta ^ prev; |
500 |
|
501 |
for (i = 0; i < NB_DEVICES; i++) { |
502 |
if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
|
503 |
r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), |
504 |
&s->periph_pdtra, |
505 |
&s->periph_portdira, |
506 |
&s->periph_pdtrb, |
507 |
&s->periph_portdirb); |
508 |
} |
509 |
} |
510 |
|
511 |
if (r)
|
512 |
gen_port_interrupts(s); |
513 |
} |
514 |
|
515 |
static void portb_changed(SH7750State * s, uint16_t prev) |
516 |
{ |
517 |
uint16_t currentb, changes; |
518 |
int i, r = 0; |
519 |
|
520 |
currentb = portb_lines(s); |
521 |
if (currentb == prev)
|
522 |
return;
|
523 |
changes = currentb ^ prev; |
524 |
|
525 |
for (i = 0; i < NB_DEVICES; i++) { |
526 |
if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
|
527 |
r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, |
528 |
&s->periph_pdtra, |
529 |
&s->periph_portdira, |
530 |
&s->periph_pdtrb, |
531 |
&s->periph_portdirb); |
532 |
} |
533 |
} |
534 |
|
535 |
if (r)
|
536 |
gen_port_interrupts(s); |
537 |
} |
538 |
|
539 |
/**********************************************************************
|
540 |
Memory
|
541 |
**********************************************************************/
|
542 |
|
543 |
static void error_access(const char *kind, target_phys_addr_t addr) |
544 |
{ |
545 |
fprintf(stderr, "%s to %s (0x%08x) not supported\n",
|
546 |
kind, regname(addr), addr); |
547 |
} |
548 |
|
549 |
static void ignore_access(const char *kind, target_phys_addr_t addr) |
550 |
{ |
551 |
fprintf(stderr, "%s to %s (0x%08x) ignored\n",
|
552 |
kind, regname(addr), addr); |
553 |
} |
554 |
|
555 |
static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) |
556 |
{ |
557 |
SH7750State *s = opaque; |
558 |
uint8_t r; |
559 |
|
560 |
switch (addr) {
|
561 |
case SH7750_SCSSR1_A7:
|
562 |
r = s->scssr1; |
563 |
s->scssr1_read |= r; |
564 |
return s->scssr1;
|
565 |
case SH7750_SCRDR1_A7:
|
566 |
s->scssr1 &= ~SH7750_SCSSR1_RDRF; |
567 |
return s->scrdr1;
|
568 |
default:
|
569 |
error_access("byte read", addr);
|
570 |
assert(0);
|
571 |
} |
572 |
} |
573 |
|
574 |
static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) |
575 |
{ |
576 |
SH7750State *s = opaque; |
577 |
uint16_t r; |
578 |
|
579 |
switch (addr) {
|
580 |
case SH7750_RFCR_A7:
|
581 |
fprintf(stderr, |
582 |
"Read access to refresh count register, incrementing\n");
|
583 |
return s->rfcr++;
|
584 |
case SH7750_TCR0_A7:
|
585 |
return s->tcr0;
|
586 |
case SH7750_SCLSR2_A7:
|
587 |
/* Read and clear overflow bit */
|
588 |
r = s->sclsr2; |
589 |
s->sclsr2 = 0;
|
590 |
return r;
|
591 |
case SH7750_SCSFR2_A7:
|
592 |
return s->scfsr2;
|
593 |
case SH7750_PDTRA_A7:
|
594 |
return porta_lines(s);
|
595 |
case SH7750_PDTRB_A7:
|
596 |
return portb_lines(s);
|
597 |
default:
|
598 |
error_access("word read", addr);
|
599 |
assert(0);
|
600 |
} |
601 |
} |
602 |
|
603 |
static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) |
604 |
{ |
605 |
SH7750State *s = opaque; |
606 |
|
607 |
switch (addr) {
|
608 |
case SH7750_MMUCR_A7:
|
609 |
return s->cpu->mmucr;
|
610 |
case SH7750_PTEH_A7:
|
611 |
return s->cpu->pteh;
|
612 |
case SH7750_PTEL_A7:
|
613 |
return s->cpu->ptel;
|
614 |
case SH7750_TTB_A7:
|
615 |
return s->cpu->ttb;
|
616 |
case SH7750_TEA_A7:
|
617 |
return s->cpu->tea;
|
618 |
case SH7750_TRA_A7:
|
619 |
return s->cpu->tra;
|
620 |
case SH7750_EXPEVT_A7:
|
621 |
return s->cpu->expevt;
|
622 |
case SH7750_INTEVT_A7:
|
623 |
return s->cpu->intevt;
|
624 |
case SH7750_CCR_A7:
|
625 |
return s->ccr;
|
626 |
case 0x1f000030: /* Processor version PVR */ |
627 |
return 0x00050000; /* SH7750R */ |
628 |
case 0x1f000040: /* Processor version CVR */ |
629 |
return 0x00110000; /* Minimum caches */ |
630 |
case 0x1f000044: /* Processor version PRR */ |
631 |
return 0x00000100; /* SH7750R */ |
632 |
default:
|
633 |
error_access("long read", addr);
|
634 |
assert(0);
|
635 |
} |
636 |
} |
637 |
|
638 |
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
639 |
uint32_t mem_value) |
640 |
{ |
641 |
SH7750State *s = opaque; |
642 |
|
643 |
switch (addr) {
|
644 |
/* PRECHARGE ? XXXXX */
|
645 |
case SH7750_PRECHARGE0_A7:
|
646 |
case SH7750_PRECHARGE1_A7:
|
647 |
ignore_access("byte write", addr);
|
648 |
return;
|
649 |
case SH7750_SCBRR2_A7:
|
650 |
s->scbrr2 = mem_value; |
651 |
return;
|
652 |
case SH7750_TSTR_A7:
|
653 |
s->tstr = mem_value; |
654 |
timer_start_changed(s); |
655 |
return;
|
656 |
case SH7750_SCSCR1_A7:
|
657 |
s->scscr1 = mem_value; |
658 |
scscr1_changed(s); |
659 |
return;
|
660 |
case SH7750_SCSMR1_A7:
|
661 |
s->scsmr1 = mem_value; |
662 |
return;
|
663 |
case SH7750_SCBRR1_A7:
|
664 |
s->scbrr1 = mem_value; |
665 |
return;
|
666 |
case SH7750_SCTDR1_A7:
|
667 |
s->scssr1 &= ~SH7750_SCSSR1_TEND; |
668 |
s->sctdr1 = mem_value; |
669 |
return;
|
670 |
case SH7750_SCSSR1_A7:
|
671 |
serial1_change_scssr1(s, mem_value); |
672 |
return;
|
673 |
default:
|
674 |
error_access("byte write", addr);
|
675 |
assert(0);
|
676 |
} |
677 |
} |
678 |
|
679 |
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
680 |
uint32_t mem_value) |
681 |
{ |
682 |
SH7750State *s = opaque; |
683 |
uint16_t temp; |
684 |
|
685 |
switch (addr) {
|
686 |
/* SDRAM controller */
|
687 |
case SH7750_SCBRR1_A7:
|
688 |
case SH7750_SCBRR2_A7:
|
689 |
case SH7750_BCR2_A7:
|
690 |
case SH7750_BCR3_A7:
|
691 |
case SH7750_RTCOR_A7:
|
692 |
case SH7750_RTCNT_A7:
|
693 |
case SH7750_RTCSR_A7:
|
694 |
ignore_access("word write", addr);
|
695 |
return;
|
696 |
/* IO ports */
|
697 |
case SH7750_PDTRA_A7:
|
698 |
temp = porta_lines(s); |
699 |
s->pdtra = mem_value; |
700 |
porta_changed(s, temp); |
701 |
return;
|
702 |
case SH7750_PDTRB_A7:
|
703 |
temp = portb_lines(s); |
704 |
s->pdtrb = mem_value; |
705 |
portb_changed(s, temp); |
706 |
return;
|
707 |
case SH7750_RFCR_A7:
|
708 |
fprintf(stderr, "Write access to refresh count register\n");
|
709 |
s->rfcr = mem_value; |
710 |
return;
|
711 |
case SH7750_SCLSR2_A7:
|
712 |
s->sclsr2 = mem_value; |
713 |
return;
|
714 |
case SH7750_SCSCR2_A7:
|
715 |
s->scscr2 = mem_value; |
716 |
scscr2_changed(s); |
717 |
return;
|
718 |
case SH7750_SCFCR2_A7:
|
719 |
s->scfcr2 = mem_value; |
720 |
return;
|
721 |
case SH7750_SCSMR2_A7:
|
722 |
s->scsmr2 = mem_value; |
723 |
return;
|
724 |
case SH7750_TCR0_A7:
|
725 |
s->tcr0 = mem_value; |
726 |
return;
|
727 |
case SH7750_GPIOIC_A7:
|
728 |
s->gpioic = mem_value; |
729 |
if (mem_value != 0) { |
730 |
fprintf(stderr, "I/O interrupts not implemented\n");
|
731 |
assert(0);
|
732 |
} |
733 |
return;
|
734 |
default:
|
735 |
error_access("word write", addr);
|
736 |
assert(0);
|
737 |
} |
738 |
} |
739 |
|
740 |
static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, |
741 |
uint32_t mem_value) |
742 |
{ |
743 |
SH7750State *s = opaque; |
744 |
uint16_t temp; |
745 |
|
746 |
switch (addr) {
|
747 |
/* SDRAM controller */
|
748 |
case SH7750_BCR1_A7:
|
749 |
case SH7750_BCR4_A7:
|
750 |
case SH7750_WCR1_A7:
|
751 |
case SH7750_WCR2_A7:
|
752 |
case SH7750_WCR3_A7:
|
753 |
case SH7750_MCR_A7:
|
754 |
ignore_access("long write", addr);
|
755 |
return;
|
756 |
/* IO ports */
|
757 |
case SH7750_PCTRA_A7:
|
758 |
temp = porta_lines(s); |
759 |
s->pctra = mem_value; |
760 |
s->portdira = portdir(mem_value); |
761 |
s->portpullupa = portpullup(mem_value); |
762 |
porta_changed(s, temp); |
763 |
return;
|
764 |
case SH7750_PCTRB_A7:
|
765 |
temp = portb_lines(s); |
766 |
s->pctrb = mem_value; |
767 |
s->portdirb = portdir(mem_value); |
768 |
s->portpullupb = portpullup(mem_value); |
769 |
portb_changed(s, temp); |
770 |
return;
|
771 |
case SH7750_TCNT0_A7:
|
772 |
s->tcnt0 = mem_value & 0xf;
|
773 |
return;
|
774 |
case SH7750_MMUCR_A7:
|
775 |
s->cpu->mmucr = mem_value; |
776 |
return;
|
777 |
case SH7750_PTEH_A7:
|
778 |
s->cpu->pteh = mem_value; |
779 |
return;
|
780 |
case SH7750_PTEL_A7:
|
781 |
s->cpu->ptel = mem_value; |
782 |
return;
|
783 |
case SH7750_TTB_A7:
|
784 |
s->cpu->ttb = mem_value; |
785 |
return;
|
786 |
case SH7750_TEA_A7:
|
787 |
s->cpu->tea = mem_value; |
788 |
return;
|
789 |
case SH7750_TRA_A7:
|
790 |
s->cpu->tra = mem_value & 0x000007ff;
|
791 |
return;
|
792 |
case SH7750_EXPEVT_A7:
|
793 |
s->cpu->expevt = mem_value & 0x000007ff;
|
794 |
return;
|
795 |
case SH7750_INTEVT_A7:
|
796 |
s->cpu->intevt = mem_value & 0x000007ff;
|
797 |
return;
|
798 |
case SH7750_CCR_A7:
|
799 |
s->ccr = mem_value; |
800 |
return;
|
801 |
default:
|
802 |
error_access("long write", addr);
|
803 |
assert(0);
|
804 |
} |
805 |
} |
806 |
|
807 |
static CPUReadMemoryFunc *sh7750_mem_read[] = {
|
808 |
sh7750_mem_readb, |
809 |
sh7750_mem_readw, |
810 |
sh7750_mem_readl |
811 |
}; |
812 |
|
813 |
static CPUWriteMemoryFunc *sh7750_mem_write[] = {
|
814 |
sh7750_mem_writeb, |
815 |
sh7750_mem_writew, |
816 |
sh7750_mem_writel |
817 |
}; |
818 |
|
819 |
SH7750State *sh7750_init(CPUSH4State * cpu) |
820 |
{ |
821 |
SH7750State *s; |
822 |
int sh7750_io_memory;
|
823 |
|
824 |
s = qemu_mallocz(sizeof(SH7750State));
|
825 |
s->cpu = cpu; |
826 |
s->periph_freq = 60000000; /* 60MHz */ |
827 |
sh7750_io_memory = cpu_register_io_memory(0,
|
828 |
sh7750_mem_read, |
829 |
sh7750_mem_write, s); |
830 |
cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory); |
831 |
init_timers(s); |
832 |
init_serial_ports(s); |
833 |
return s;
|
834 |
} |