Archipelago » qemu

/*

 * QEMU IDE disk and CD/DVD-ROM Emulator

 *

 * Copyright (c) 2003 Fabrice Bellard

 * Copyright (c) 2006 Openedhand Ltd.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include <hw/hw.h>

#include <hw/pc.h>

#include <hw/pci.h>

#include <hw/scsi.h>

#include "qemu-error.h"

#include "qemu-timer.h"

#include "sysemu.h"

#include "dma.h"

#include "blockdev.h"

#include <hw/ide/internal.h>

#define IDE_PAGE_SIZE 4096

static const int smart_attributes[][5] = {

    /* id,  flags, val, wrst, thrsh */

    { 0x01, 0x03, 0x64, 0x64, 0x06}, /* raw read */

    { 0x03, 0x03, 0x64, 0x64, 0x46}, /* spin up */

    { 0x04, 0x02, 0x64, 0x64, 0x14}, /* start stop count */

    { 0x05, 0x03, 0x64, 0x64, 0x36}, /* remapped sectors */

    { 0x00, 0x00, 0x00, 0x00, 0x00}

};

/* XXX: DVDs that could fit on a CD will be reported as a CD */

static inline int media_present(IDEState *s)

{

    return (s->nb_sectors > 0);

}

static inline int media_is_dvd(IDEState *s)

{

    return (media_present(s) && s->nb_sectors > CD_MAX_SECTORS);

}

static inline int media_is_cd(IDEState *s)

{

    return (media_present(s) && s->nb_sectors <= CD_MAX_SECTORS);

}

static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);

static void ide_dma_restart(IDEState *s, int is_read);

static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);

static int ide_handle_rw_error(IDEState *s, int error, int op);

static void ide_flush_cache(IDEState *s);

static void padstr(char *str, const char *src, int len)

{

    int i, v;

    for(i = 0; i < len; i++) {

        if (*src)

            v = *src++;

        else

            v = ' ';

        str[i^1] = v;

    }

}

static void padstr8(uint8_t *buf, int buf_size, const char *src)

{

    int i;

    for(i = 0; i < buf_size; i++) {

        if (*src)

            buf[i] = *src++;

        else

            buf[i] = ' ';

    }

}

static void put_le16(uint16_t *p, unsigned int v)

{

    *p = cpu_to_le16(v);

}

static void ide_identify(IDEState *s)

{

    uint16_t *p;

    unsigned int oldsize;

    IDEDevice *dev;

    if (s->identify_set) {

        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));

        return;

    }

    memset(s->io_buffer, 0, 512);

    p = (uint16_t *)s->io_buffer;

    put_le16(p + 0, 0x0040);

    put_le16(p + 1, s->cylinders);

    put_le16(p + 3, s->heads);

    put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */

    put_le16(p + 5, 512); /* XXX: retired, remove ? */

    put_le16(p + 6, s->sectors);

    padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */

    put_le16(p + 20, 3); /* XXX: retired, remove ? */

    put_le16(p + 21, 512); /* cache size in sectors */

    put_le16(p + 22, 4); /* ecc bytes */

    padstr((char *)(p + 23), s->version, 8); /* firmware version */

    padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */

#if MAX_MULT_SECTORS > 1

    put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);

#endif

    put_le16(p + 48, 1); /* dword I/O */

    put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */

    put_le16(p + 51, 0x200); /* PIO transfer cycle */

    put_le16(p + 52, 0x200); /* DMA transfer cycle */

    put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */

    put_le16(p + 54, s->cylinders);

    put_le16(p + 55, s->heads);

    put_le16(p + 56, s->sectors);

    oldsize = s->cylinders * s->heads * s->sectors;

    put_le16(p + 57, oldsize);

    put_le16(p + 58, oldsize >> 16);

    if (s->mult_sectors)

        put_le16(p + 59, 0x100 | s->mult_sectors);

    put_le16(p + 60, s->nb_sectors);

    put_le16(p + 61, s->nb_sectors >> 16);

    put_le16(p + 62, 0x07); /* single word dma0-2 supported */

    put_le16(p + 63, 0x07); /* mdma0-2 supported */

    put_le16(p + 64, 0x03); /* pio3-4 supported */

    put_le16(p + 65, 120);

    put_le16(p + 66, 120);

    put_le16(p + 67, 120);

    put_le16(p + 68, 120);

    put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */

    put_le16(p + 81, 0x16); /* conforms to ata5 */

    /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */

    put_le16(p + 82, (1 << 14) | (1 << 5) | 1);

    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */

    put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));

    /* 14=set to 1, 1=SMART self test, 0=SMART error logging */

    put_le16(p + 84, (1 << 14) | 0);

    /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */

    if (bdrv_enable_write_cache(s->bs))

         put_le16(p + 85, (1 << 14) | (1 << 5) | 1);

    else

         put_le16(p + 85, (1 << 14) | 1);

    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */

    put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));

    /* 14=set to 1, 1=smart self test, 0=smart error logging */

    put_le16(p + 87, (1 << 14) | 0);

    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */

    put_le16(p + 93, 1 | (1 << 14) | 0x2000);

    put_le16(p + 100, s->nb_sectors);

    put_le16(p + 101, s->nb_sectors >> 16);

    put_le16(p + 102, s->nb_sectors >> 32);

    put_le16(p + 103, s->nb_sectors >> 48);

    dev = s->unit ? s->bus->slave : s->bus->master;

    if (dev && dev->conf.physical_block_size)

        put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));

    memcpy(s->identify_data, p, sizeof(s->identify_data));

    s->identify_set = 1;

}

static void ide_atapi_identify(IDEState *s)

{

    uint16_t *p;

    if (s->identify_set) {

        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));

        return;

    }

    memset(s->io_buffer, 0, 512);

    p = (uint16_t *)s->io_buffer;

    /* Removable CDROM, 50us response, 12 byte packets */

    put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));

    padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */

    put_le16(p + 20, 3); /* buffer type */

    put_le16(p + 21, 512); /* cache size in sectors */

    put_le16(p + 22, 4); /* ecc bytes */

    padstr((char *)(p + 23), s->version, 8); /* firmware version */

    padstr((char *)(p + 27), "QEMU DVD-ROM", 40); /* model */

    put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */

#ifdef USE_DMA_CDROM

    put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */

    put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */

    put_le16(p + 62, 7);  /* single word dma0-2 supported */

    put_le16(p + 63, 7);  /* mdma0-2 supported */

#else

    put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */

    put_le16(p + 53, 3); /* words 64-70, 54-58 valid */

    put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */

#endif

    put_le16(p + 64, 3); /* pio3-4 supported */

    put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */

    put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */

    put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */

    put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */

    put_le16(p + 71, 30); /* in ns */

    put_le16(p + 72, 30); /* in ns */

    put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */

#ifdef USE_DMA_CDROM

    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */

#endif

    memcpy(s->identify_data, p, sizeof(s->identify_data));

    s->identify_set = 1;

}

static void ide_cfata_identify(IDEState *s)

{

    uint16_t *p;

    uint32_t cur_sec;

    p = (uint16_t *) s->identify_data;

    if (s->identify_set)

        goto fill_buffer;

    memset(p, 0, sizeof(s->identify_data));

    cur_sec = s->cylinders * s->heads * s->sectors;

    put_le16(p + 0, 0x848a);                        /* CF Storage Card signature */

    put_le16(p + 1, s->cylinders);                /* Default cylinders */

    put_le16(p + 3, s->heads);                        /* Default heads */

    put_le16(p + 6, s->sectors);                /* Default sectors per track */

    put_le16(p + 7, s->nb_sectors >> 16);        /* Sectors per card */

    put_le16(p + 8, s->nb_sectors);                /* Sectors per card */

    padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */

    put_le16(p + 22, 0x0004);                        /* ECC bytes */

    padstr((char *) (p + 23), s->version, 8);        /* Firmware Revision */

    padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */

#if MAX_MULT_SECTORS > 1

    put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);

#else

    put_le16(p + 47, 0x0000);

#endif

    put_le16(p + 49, 0x0f00);                        /* Capabilities */

    put_le16(p + 51, 0x0002);                        /* PIO cycle timing mode */

    put_le16(p + 52, 0x0001);                        /* DMA cycle timing mode */

    put_le16(p + 53, 0x0003);                        /* Translation params valid */

    put_le16(p + 54, s->cylinders);                /* Current cylinders */

    put_le16(p + 55, s->heads);                        /* Current heads */

    put_le16(p + 56, s->sectors);                /* Current sectors */

    put_le16(p + 57, cur_sec);                        /* Current capacity */

    put_le16(p + 58, cur_sec >> 16);                /* Current capacity */

    if (s->mult_sectors)                        /* Multiple sector setting */

        put_le16(p + 59, 0x100 | s->mult_sectors);

    put_le16(p + 60, s->nb_sectors);                /* Total LBA sectors */

    put_le16(p + 61, s->nb_sectors >> 16);        /* Total LBA sectors */

    put_le16(p + 63, 0x0203);                        /* Multiword DMA capability */

    put_le16(p + 64, 0x0001);                        /* Flow Control PIO support */

    put_le16(p + 65, 0x0096);                        /* Min. Multiword DMA cycle */

    put_le16(p + 66, 0x0096);                        /* Rec. Multiword DMA cycle */

    put_le16(p + 68, 0x00b4);                        /* Min. PIO cycle time */

    put_le16(p + 82, 0x400c);                        /* Command Set supported */

    put_le16(p + 83, 0x7068);                        /* Command Set supported */

    put_le16(p + 84, 0x4000);                        /* Features supported */

    put_le16(p + 85, 0x000c);                        /* Command Set enabled */

    put_le16(p + 86, 0x7044);                        /* Command Set enabled */

    put_le16(p + 87, 0x4000);                        /* Features enabled */

    put_le16(p + 91, 0x4060);                        /* Current APM level */

    put_le16(p + 129, 0x0002);                        /* Current features option */

    put_le16(p + 130, 0x0005);                        /* Reassigned sectors */

    put_le16(p + 131, 0x0001);                        /* Initial power mode */

    put_le16(p + 132, 0x0000);                        /* User signature */

    put_le16(p + 160, 0x8100);                        /* Power requirement */

    put_le16(p + 161, 0x8001);                        /* CF command set */

    s->identify_set = 1;

fill_buffer:

    memcpy(s->io_buffer, p, sizeof(s->identify_data));

}

static void ide_set_signature(IDEState *s)

{

    s->select &= 0xf0; /* clear head */

    /* put signature */

    s->nsector = 1;

    s->sector = 1;

    if (s->drive_kind == IDE_CD) {

        s->lcyl = 0x14;

        s->hcyl = 0xeb;

    } else if (s->bs) {

        s->lcyl = 0;

        s->hcyl = 0;

    } else {

        s->lcyl = 0xff;

        s->hcyl = 0xff;

    }

}

static inline void ide_abort_command(IDEState *s)

{

    s->status = READY_STAT | ERR_STAT;

    s->error = ABRT_ERR;

}

static inline void ide_dma_submit_check(IDEState *s,

          BlockDriverCompletionFunc *dma_cb, BMDMAState *bm)

{

    if (bm->aiocb)

        return;

    dma_cb(bm, -1);

}

/* prepare data transfer and tell what to do after */

static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,

                               EndTransferFunc *end_transfer_func)

{

    s->end_transfer_func = end_transfer_func;

    s->data_ptr = buf;

    s->data_end = buf + size;

    if (!(s->status & ERR_STAT))

        s->status |= DRQ_STAT;

}

static void ide_transfer_stop(IDEState *s)

{

    s->end_transfer_func = ide_transfer_stop;

    s->data_ptr = s->io_buffer;

    s->data_end = s->io_buffer;

    s->status &= ~DRQ_STAT;

}

int64_t ide_get_sector(IDEState *s)

{

    int64_t sector_num;

    if (s->select & 0x40) {

        /* lba */

        if (!s->lba48) {

            sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |

                (s->lcyl << 8) | s->sector;

        } else {

            sector_num = ((int64_t)s->hob_hcyl << 40) |

                ((int64_t) s->hob_lcyl << 32) |

                ((int64_t) s->hob_sector << 24) |

                ((int64_t) s->hcyl << 16) |

                ((int64_t) s->lcyl << 8) | s->sector;

        }

    } else {

        sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +

            (s->select & 0x0f) * s->sectors + (s->sector - 1);

    }

    return sector_num;

}

void ide_set_sector(IDEState *s, int64_t sector_num)

{

    unsigned int cyl, r;

    if (s->select & 0x40) {

        if (!s->lba48) {

            s->select = (s->select & 0xf0) | (sector_num >> 24);

            s->hcyl = (sector_num >> 16);

            s->lcyl = (sector_num >> 8);

            s->sector = (sector_num);

        } else {

            s->sector = sector_num;

            s->lcyl = sector_num >> 8;

            s->hcyl = sector_num >> 16;

            s->hob_sector = sector_num >> 24;

            s->hob_lcyl = sector_num >> 32;

            s->hob_hcyl = sector_num >> 40;

        }

    } else {

        cyl = sector_num / (s->heads * s->sectors);

        r = sector_num % (s->heads * s->sectors);

        s->hcyl = cyl >> 8;

        s->lcyl = cyl;

        s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);

        s->sector = (r % s->sectors) + 1;

    }

}

static void ide_rw_error(IDEState *s) {

    ide_abort_command(s);

    ide_set_irq(s->bus);

}

static void ide_sector_read(IDEState *s)

{

    int64_t sector_num;

    int ret, n;

    s->status = READY_STAT | SEEK_STAT;

    s->error = 0; /* not needed by IDE spec, but needed by Windows */

    sector_num = ide_get_sector(s);

    n = s->nsector;

    if (n == 0) {

        /* no more sector to read from disk */

        ide_transfer_stop(s);

    } else {

#if defined(DEBUG_IDE)

        printf("read sector=%" PRId64 "\n", sector_num);

#endif

        if (n > s->req_nb_sectors)

            n = s->req_nb_sectors;

        ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);

        if (ret != 0) {

            if (ide_handle_rw_error(s, -ret,

                BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ))

            {

                return;

            }

        }

        ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);

        ide_set_irq(s->bus);

        ide_set_sector(s, sector_num + n);

        s->nsector -= n;

    }

}

/* return 0 if buffer completed */

static int dma_buf_prepare(BMDMAState *bm, int is_write)

{

    IDEState *s = bmdma_active_if(bm);

    struct {

        uint32_t addr;

        uint32_t size;

    } prd;

    int l, len;

    qemu_sglist_init(&s->sg, s->nsector / (IDE_PAGE_SIZE / 512) + 1);

    s->io_buffer_size = 0;

    for(;;) {

        if (bm->cur_prd_len == 0) {

            /* end of table (with a fail safe of one page) */

            if (bm->cur_prd_last ||

                (bm->cur_addr - bm->addr) >= IDE_PAGE_SIZE)

                return s->io_buffer_size != 0;

            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);

            bm->cur_addr += 8;

            prd.addr = le32_to_cpu(prd.addr);

            prd.size = le32_to_cpu(prd.size);

            len = prd.size & 0xfffe;

            if (len == 0)

                len = 0x10000;

            bm->cur_prd_len = len;

            bm->cur_prd_addr = prd.addr;

            bm->cur_prd_last = (prd.size & 0x80000000);

        }

        l = bm->cur_prd_len;

        if (l > 0) {

            qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);

            bm->cur_prd_addr += l;

            bm->cur_prd_len -= l;

            s->io_buffer_size += l;

        }

    }

    return 1;

}

static void dma_buf_commit(IDEState *s, int is_write)

{

    qemu_sglist_destroy(&s->sg);

}

static void ide_dma_set_inactive(BMDMAState *bm)

{

    bm->status &= ~BM_STATUS_DMAING;

    bm->dma_cb = NULL;

    bm->unit = -1;

    bm->aiocb = NULL;

}

void ide_dma_error(IDEState *s)

{

    ide_transfer_stop(s);

    s->error = ABRT_ERR;

    s->status = READY_STAT | ERR_STAT;

    ide_dma_set_inactive(s->bus->bmdma);

    s->bus->bmdma->status |= BM_STATUS_INT;

    ide_set_irq(s->bus);

}

static int ide_handle_rw_error(IDEState *s, int error, int op)

{

    int is_read = (op & BM_STATUS_RETRY_READ);

    BlockErrorAction action = bdrv_get_on_error(s->bs, is_read);

    if (action == BLOCK_ERR_IGNORE) {

        bdrv_mon_event(s->bs, BDRV_ACTION_IGNORE, is_read);

        return 0;

    }

    if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)

            || action == BLOCK_ERR_STOP_ANY) {

        s->bus->bmdma->unit = s->unit;

        s->bus->bmdma->status |= op;

        bdrv_mon_event(s->bs, BDRV_ACTION_STOP, is_read);

        vm_stop(0);

    } else {

        if (op & BM_STATUS_DMA_RETRY) {

            dma_buf_commit(s, 0);

            ide_dma_error(s);

        } else {

            ide_rw_error(s);

        }

        bdrv_mon_event(s->bs, BDRV_ACTION_REPORT, is_read);

    }

    return 1;

}

/* return 0 if buffer completed */

static int dma_buf_rw(BMDMAState *bm, int is_write)

{

    IDEState *s = bmdma_active_if(bm);

    struct {

        uint32_t addr;

        uint32_t size;

    } prd;

    int l, len;

    for(;;) {

        l = s->io_buffer_size - s->io_buffer_index;

        if (l <= 0)

            break;

        if (bm->cur_prd_len == 0) {

            /* end of table (with a fail safe of one page) */

            if (bm->cur_prd_last ||

                (bm->cur_addr - bm->addr) >= IDE_PAGE_SIZE)

                return 0;

            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);

            bm->cur_addr += 8;

            prd.addr = le32_to_cpu(prd.addr);

            prd.size = le32_to_cpu(prd.size);

            len = prd.size & 0xfffe;

            if (len == 0)

                len = 0x10000;

            bm->cur_prd_len = len;

            bm->cur_prd_addr = prd.addr;

            bm->cur_prd_last = (prd.size & 0x80000000);

        }

        if (l > bm->cur_prd_len)

            l = bm->cur_prd_len;

        if (l > 0) {

            if (is_write) {

                cpu_physical_memory_write(bm->cur_prd_addr,

                                          s->io_buffer + s->io_buffer_index, l);

            } else {

                cpu_physical_memory_read(bm->cur_prd_addr,

                                          s->io_buffer + s->io_buffer_index, l);

            }

            bm->cur_prd_addr += l;

            bm->cur_prd_len -= l;

            s->io_buffer_index += l;

        }

    }

    return 1;

}

static void ide_read_dma_cb(void *opaque, int ret)

{

    BMDMAState *bm = opaque;

    IDEState *s = bmdma_active_if(bm);

    int n;

    int64_t sector_num;

    if (ret < 0) {

        if (ide_handle_rw_error(s, -ret,

            BM_STATUS_DMA_RETRY | BM_STATUS_RETRY_READ))

        {

            return;

        }

    }

    n = s->io_buffer_size >> 9;

    sector_num = ide_get_sector(s);

    if (n > 0) {

        dma_buf_commit(s, 1);

        sector_num += n;

        ide_set_sector(s, sector_num);

        s->nsector -= n;

    }

    /* end of transfer ? */

    if (s->nsector == 0) {

        s->status = READY_STAT | SEEK_STAT;

        ide_set_irq(s->bus);

    eot:

        bm->status |= BM_STATUS_INT;

        ide_dma_set_inactive(bm);

        return;

    }

    /* launch next transfer */

    n = s->nsector;

    s->io_buffer_index = 0;

    s->io_buffer_size = n * 512;

    if (dma_buf_prepare(bm, 1) == 0)

        goto eot;

#ifdef DEBUG_AIO

    printf("aio_read: sector_num=%" PRId64 " n=%d\n", sector_num, n);

#endif

    bm->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, ide_read_dma_cb, bm);

    ide_dma_submit_check(s, ide_read_dma_cb, bm);

}

static void ide_sector_read_dma(IDEState *s)

{

    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;

    s->io_buffer_index = 0;

    s->io_buffer_size = 0;

    s->is_read = 1;

    ide_dma_start(s, ide_read_dma_cb);

}

static void ide_sector_write_timer_cb(void *opaque)

{

    IDEState *s = opaque;

    ide_set_irq(s->bus);

}

static void ide_sector_write(IDEState *s)

{

    int64_t sector_num;

    int ret, n, n1;

    s->status = READY_STAT | SEEK_STAT;

    sector_num = ide_get_sector(s);

#if defined(DEBUG_IDE)

    printf("write sector=%" PRId64 "\n", sector_num);

#endif

    n = s->nsector;

    if (n > s->req_nb_sectors)

        n = s->req_nb_sectors;

    ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);

    if (ret != 0) {

        if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY))

            return;

    }

    s->nsector -= n;

    if (s->nsector == 0) {

        /* no more sectors to write */

        ide_transfer_stop(s);

    } else {

        n1 = s->nsector;

        if (n1 > s->req_nb_sectors)

            n1 = s->req_nb_sectors;

        ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);

    }

    ide_set_sector(s, sector_num + n);

    if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {

        /* It seems there is a bug in the Windows 2000 installer HDD

           IDE driver which fills the disk with empty logs when the

           IDE write IRQ comes too early. This hack tries to correct

           that at the expense of slower write performances. Use this

           option _only_ to install Windows 2000. You must disable it

           for normal use. */

        qemu_mod_timer(s->sector_write_timer,

                       qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 1000));

    } else {

        ide_set_irq(s->bus);

    }

}

static void ide_dma_restart_bh(void *opaque)

{

    BMDMAState *bm = opaque;

    int is_read;

    qemu_bh_delete(bm->bh);

    bm->bh = NULL;

    is_read = !!(bm->status & BM_STATUS_RETRY_READ);

    if (bm->status & BM_STATUS_DMA_RETRY) {

        bm->status &= ~(BM_STATUS_DMA_RETRY | BM_STATUS_RETRY_READ);

        ide_dma_restart(bmdma_active_if(bm), is_read);

    } else if (bm->status & BM_STATUS_PIO_RETRY) {

        bm->status &= ~(BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ);

        if (is_read) {

            ide_sector_read(bmdma_active_if(bm));

        } else {

            ide_sector_write(bmdma_active_if(bm));

        }

    } else if (bm->status & BM_STATUS_RETRY_FLUSH) {

        ide_flush_cache(bmdma_active_if(bm));

    }

}

void ide_dma_restart_cb(void *opaque, int running, int reason)

{

    BMDMAState *bm = opaque;

    if (!running)

        return;

    if (!bm->bh) {

        bm->bh = qemu_bh_new(ide_dma_restart_bh, bm);

        qemu_bh_schedule(bm->bh);

    }

}

static void ide_write_dma_cb(void *opaque, int ret)

{

    BMDMAState *bm = opaque;

    IDEState *s = bmdma_active_if(bm);

    int n;

    int64_t sector_num;

    if (ret < 0) {

        if (ide_handle_rw_error(s, -ret,  BM_STATUS_DMA_RETRY))

            return;

    }

    n = s->io_buffer_size >> 9;

    sector_num = ide_get_sector(s);

    if (n > 0) {

        dma_buf_commit(s, 0);

        sector_num += n;

        ide_set_sector(s, sector_num);

        s->nsector -= n;

    }

    /* end of transfer ? */

    if (s->nsector == 0) {

        s->status = READY_STAT | SEEK_STAT;

        ide_set_irq(s->bus);

    eot:

        bm->status |= BM_STATUS_INT;

        ide_dma_set_inactive(bm);

        return;

    }

    n = s->nsector;

    s->io_buffer_size = n * 512;

    /* launch next transfer */

    if (dma_buf_prepare(bm, 0) == 0)

        goto eot;

#ifdef DEBUG_AIO

    printf("aio_write: sector_num=%" PRId64 " n=%d\n", sector_num, n);

#endif

    bm->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, ide_write_dma_cb, bm);

    ide_dma_submit_check(s, ide_write_dma_cb, bm);

}

static void ide_sector_write_dma(IDEState *s)

{

    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;

    s->io_buffer_index = 0;

    s->io_buffer_size = 0;

    s->is_read = 0;

    ide_dma_start(s, ide_write_dma_cb);

}

void ide_atapi_cmd_ok(IDEState *s)

{

    s->error = 0;

    s->status = READY_STAT | SEEK_STAT;

    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;

    ide_set_irq(s->bus);

}

void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)

{

#ifdef DEBUG_IDE_ATAPI

    printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);

#endif

    s->error = sense_key << 4;

    s->status = READY_STAT | ERR_STAT;

    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;

    s->sense_key = sense_key;

    s->asc = asc;

    ide_set_irq(s->bus);

}

static void ide_atapi_cmd_check_status(IDEState *s)

{

#ifdef DEBUG_IDE_ATAPI

    printf("atapi_cmd_check_status\n");

#endif

    s->error = MC_ERR | (SENSE_UNIT_ATTENTION << 4);

    s->status = ERR_STAT;

    s->nsector = 0;

    ide_set_irq(s->bus);

}

static void ide_flush_cb(void *opaque, int ret)

{

    IDEState *s = opaque;

    if (ret < 0) {

        /* XXX: What sector number to set here? */

        if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {

            return;

        }

    }

    s->status = READY_STAT | SEEK_STAT;

    ide_set_irq(s->bus);

}

static void ide_flush_cache(IDEState *s)

{

    BlockDriverAIOCB *acb;

    if (s->bs == NULL) {

        ide_flush_cb(s, 0);

        return;

    }

    acb = bdrv_aio_flush(s->bs, ide_flush_cb, s);

    if (acb == NULL) {

        ide_flush_cb(s, -EIO);

    }

}

static inline void cpu_to_ube16(uint8_t *buf, int val)

{

    buf[0] = val >> 8;

    buf[1] = val & 0xff;

}

static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)

{

    buf[0] = val >> 24;

    buf[1] = val >> 16;

    buf[2] = val >> 8;

    buf[3] = val & 0xff;

}

static inline int ube16_to_cpu(const uint8_t *buf)

{

    return (buf[0] << 8) | buf[1];

}

static inline int ube32_to_cpu(const uint8_t *buf)

{

    return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];

}

static void lba_to_msf(uint8_t *buf, int lba)

{

    lba += 150;

    buf[0] = (lba / 75) / 60;

    buf[1] = (lba / 75) % 60;

    buf[2] = lba % 75;

}

static void cd_data_to_raw(uint8_t *buf, int lba)

{

    /* sync bytes */

    buf[0] = 0x00;

    memset(buf + 1, 0xff, 10);