Revision 2507c12a hw/omap1.c
| b/hw/omap1.c | ||
|---|---|---|
| 264 | 264 |
omap_timer_clk_setup(s); |
| 265 | 265 |
|
| 266 | 266 |
iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn, |
| 267 |
omap_mpu_timer_writefn, s); |
|
| 267 |
omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 268 | 268 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
| 269 | 269 |
|
| 270 | 270 |
return s; |
| ... | ... | |
| 387 | 387 |
omap_timer_clk_setup(&s->timer); |
| 388 | 388 |
|
| 389 | 389 |
iomemtype = cpu_register_io_memory(omap_wd_timer_readfn, |
| 390 |
omap_wd_timer_writefn, s); |
|
| 390 |
omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 391 | 391 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
| 392 | 392 |
|
| 393 | 393 |
return s; |
| ... | ... | |
| 489 | 489 |
omap_timer_clk_setup(&s->timer); |
| 490 | 490 |
|
| 491 | 491 |
iomemtype = cpu_register_io_memory(omap_os_timer_readfn, |
| 492 |
omap_os_timer_writefn, s); |
|
| 492 |
omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 493 | 493 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 494 | 494 |
|
| 495 | 495 |
return s; |
| ... | ... | |
| 716 | 716 |
struct omap_mpu_state_s *mpu) |
| 717 | 717 |
{
|
| 718 | 718 |
int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn, |
| 719 |
omap_ulpd_pm_writefn, mpu); |
|
| 719 |
omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN);
|
|
| 720 | 720 |
|
| 721 | 721 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 722 | 722 |
omap_ulpd_pm_reset(mpu); |
| ... | ... | |
| 931 | 931 |
struct omap_mpu_state_s *mpu) |
| 932 | 932 |
{
|
| 933 | 933 |
int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn, |
| 934 |
omap_pin_cfg_writefn, mpu); |
|
| 934 |
omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN);
|
|
| 935 | 935 |
|
| 936 | 936 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 937 | 937 |
omap_pin_cfg_reset(mpu); |
| ... | ... | |
| 1001 | 1001 |
static void omap_id_init(struct omap_mpu_state_s *mpu) |
| 1002 | 1002 |
{
|
| 1003 | 1003 |
int iomemtype = cpu_register_io_memory(omap_id_readfn, |
| 1004 |
omap_id_writefn, mpu); |
|
| 1004 |
omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN);
|
|
| 1005 | 1005 |
cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800); |
| 1006 | 1006 |
cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400); |
| 1007 | 1007 |
if (!cpu_is_omap15xx(mpu)) |
| ... | ... | |
| 1084 | 1084 |
struct omap_mpu_state_s *mpu) |
| 1085 | 1085 |
{
|
| 1086 | 1086 |
int iomemtype = cpu_register_io_memory(omap_mpui_readfn, |
| 1087 |
omap_mpui_writefn, mpu); |
|
| 1087 |
omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN);
|
|
| 1088 | 1088 |
|
| 1089 | 1089 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
| 1090 | 1090 |
|
| ... | ... | |
| 1193 | 1193 |
omap_tipb_bridge_reset(s); |
| 1194 | 1194 |
|
| 1195 | 1195 |
iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn, |
| 1196 |
omap_tipb_bridge_writefn, s); |
|
| 1196 |
omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 1197 | 1197 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
| 1198 | 1198 |
|
| 1199 | 1199 |
return s; |
| ... | ... | |
| 1299 | 1299 |
struct omap_mpu_state_s *mpu) |
| 1300 | 1300 |
{
|
| 1301 | 1301 |
int iomemtype = cpu_register_io_memory(omap_tcmi_readfn, |
| 1302 |
omap_tcmi_writefn, mpu); |
|
| 1302 |
omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
|
|
| 1303 | 1303 |
|
| 1304 | 1304 |
cpu_register_physical_memory(base, 0x100, iomemtype); |
| 1305 | 1305 |
omap_tcmi_reset(mpu); |
| ... | ... | |
| 1372 | 1372 |
omap_clk clk) |
| 1373 | 1373 |
{
|
| 1374 | 1374 |
int iomemtype = cpu_register_io_memory(omap_dpll_readfn, |
| 1375 |
omap_dpll_writefn, s); |
|
| 1375 |
omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 1376 | 1376 |
|
| 1377 | 1377 |
s->dpll = clk; |
| 1378 | 1378 |
omap_dpll_reset(s); |
| ... | ... | |
| 1776 | 1776 |
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s) |
| 1777 | 1777 |
{
|
| 1778 | 1778 |
int iomemtype[2] = {
|
| 1779 |
cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s), |
|
| 1780 |
cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s), |
|
| 1779 |
cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s, |
|
| 1780 |
DEVICE_NATIVE_ENDIAN), |
|
| 1781 |
cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s, |
|
| 1782 |
DEVICE_NATIVE_ENDIAN), |
|
| 1781 | 1783 |
}; |
| 1782 | 1784 |
|
| 1783 | 1785 |
s->clkm.arm_idlect1 = 0x03ff; |
| ... | ... | |
| 2031 | 2033 |
omap_mpuio_reset(s); |
| 2032 | 2034 |
|
| 2033 | 2035 |
iomemtype = cpu_register_io_memory(omap_mpuio_readfn, |
| 2034 |
omap_mpuio_writefn, s); |
|
| 2036 |
omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 2035 | 2037 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 2036 | 2038 |
|
| 2037 | 2039 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
| ... | ... | |
| 2216 | 2218 |
omap_uwire_reset(s); |
| 2217 | 2219 |
|
| 2218 | 2220 |
iomemtype = cpu_register_io_memory(omap_uwire_readfn, |
| 2219 |
omap_uwire_writefn, s); |
|
| 2221 |
omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 2220 | 2222 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 2221 | 2223 |
|
| 2222 | 2224 |
return s; |
| ... | ... | |
| 2317 | 2319 |
omap_pwl_reset(s); |
| 2318 | 2320 |
|
| 2319 | 2321 |
iomemtype = cpu_register_io_memory(omap_pwl_readfn, |
| 2320 |
omap_pwl_writefn, s); |
|
| 2322 |
omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 2321 | 2323 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 2322 | 2324 |
|
| 2323 | 2325 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
| ... | ... | |
| 2412 | 2414 |
omap_pwt_reset(s); |
| 2413 | 2415 |
|
| 2414 | 2416 |
iomemtype = cpu_register_io_memory(omap_pwt_readfn, |
| 2415 |
omap_pwt_writefn, s); |
|
| 2417 |
omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 2416 | 2418 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 2417 | 2419 |
} |
| 2418 | 2420 |
|
| ... | ... | |
| 2825 | 2827 |
omap_rtc_reset(s); |
| 2826 | 2828 |
|
| 2827 | 2829 |
iomemtype = cpu_register_io_memory(omap_rtc_readfn, |
| 2828 |
omap_rtc_writefn, s); |
|
| 2830 |
omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 2829 | 2831 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 2830 | 2832 |
|
| 2831 | 2833 |
return s; |
| ... | ... | |
| 3347 | 3349 |
omap_mcbsp_reset(s); |
| 3348 | 3350 |
|
| 3349 | 3351 |
iomemtype = cpu_register_io_memory(omap_mcbsp_readfn, |
| 3350 |
omap_mcbsp_writefn, s); |
|
| 3352 |
omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 3351 | 3353 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 3352 | 3354 |
|
| 3353 | 3355 |
return s; |
| ... | ... | |
| 3519 | 3521 |
omap_lpg_reset(s); |
| 3520 | 3522 |
|
| 3521 | 3523 |
iomemtype = cpu_register_io_memory(omap_lpg_readfn, |
| 3522 |
omap_lpg_writefn, s); |
|
| 3524 |
omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
|
|
| 3523 | 3525 |
cpu_register_physical_memory(base, 0x800, iomemtype); |
| 3524 | 3526 |
|
| 3525 | 3527 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); |
| ... | ... | |
| 3552 | 3554 |
static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu) |
| 3553 | 3555 |
{
|
| 3554 | 3556 |
int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn, |
| 3555 |
omap_mpui_io_writefn, mpu); |
|
| 3557 |
omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
|
|
| 3556 | 3558 |
cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype); |
| 3557 | 3559 |
} |
| 3558 | 3560 |
|
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