root / tcg / ia64 / tcg-target.c @ 255108c0
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1 | 477ba620 | Aurelien Jarno | /*
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2 | 477ba620 | Aurelien Jarno | * Tiny Code Generator for QEMU
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3 | 477ba620 | Aurelien Jarno | *
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4 | 477ba620 | Aurelien Jarno | * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
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5 | 477ba620 | Aurelien Jarno | * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
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6 | 477ba620 | Aurelien Jarno | *
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7 | 477ba620 | Aurelien Jarno | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 477ba620 | Aurelien Jarno | * of this software and associated documentation files (the "Software"), to deal
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9 | 477ba620 | Aurelien Jarno | * in the Software without restriction, including without limitation the rights
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10 | 477ba620 | Aurelien Jarno | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 477ba620 | Aurelien Jarno | * copies of the Software, and to permit persons to whom the Software is
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12 | 477ba620 | Aurelien Jarno | * furnished to do so, subject to the following conditions:
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13 | 477ba620 | Aurelien Jarno | *
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14 | 477ba620 | Aurelien Jarno | * The above copyright notice and this permission notice shall be included in
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15 | 477ba620 | Aurelien Jarno | * all copies or substantial portions of the Software.
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16 | 477ba620 | Aurelien Jarno | *
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17 | 477ba620 | Aurelien Jarno | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 477ba620 | Aurelien Jarno | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 477ba620 | Aurelien Jarno | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 477ba620 | Aurelien Jarno | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 477ba620 | Aurelien Jarno | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 477ba620 | Aurelien Jarno | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 477ba620 | Aurelien Jarno | * THE SOFTWARE.
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24 | 477ba620 | Aurelien Jarno | */
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25 | 477ba620 | Aurelien Jarno | |
26 | 477ba620 | Aurelien Jarno | /*
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27 | 477ba620 | Aurelien Jarno | * Register definitions
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28 | 477ba620 | Aurelien Jarno | */
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29 | 477ba620 | Aurelien Jarno | |
30 | 477ba620 | Aurelien Jarno | #ifndef NDEBUG
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31 | 477ba620 | Aurelien Jarno | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
32 | 477ba620 | Aurelien Jarno | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
33 | 477ba620 | Aurelien Jarno | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
34 | 477ba620 | Aurelien Jarno | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
35 | 477ba620 | Aurelien Jarno | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
36 | 477ba620 | Aurelien Jarno | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
37 | 477ba620 | Aurelien Jarno | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
38 | 477ba620 | Aurelien Jarno | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", |
39 | 477ba620 | Aurelien Jarno | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", |
40 | 477ba620 | Aurelien Jarno | }; |
41 | 477ba620 | Aurelien Jarno | #endif
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42 | 477ba620 | Aurelien Jarno | |
43 | 6781d08d | Richard Henderson | #ifdef CONFIG_USE_GUEST_BASE
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44 | 6781d08d | Richard Henderson | #define TCG_GUEST_BASE_REG TCG_REG_R55
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45 | 6781d08d | Richard Henderson | #else
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46 | 6781d08d | Richard Henderson | #define TCG_GUEST_BASE_REG TCG_REG_R0
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47 | 6781d08d | Richard Henderson | #endif
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48 | 255108c0 | Richard Henderson | #ifndef GUEST_BASE
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49 | 255108c0 | Richard Henderson | #define GUEST_BASE 0 |
50 | 255108c0 | Richard Henderson | #endif
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51 | 6781d08d | Richard Henderson | |
52 | 477ba620 | Aurelien Jarno | /* Branch registers */
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53 | 477ba620 | Aurelien Jarno | enum {
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54 | 477ba620 | Aurelien Jarno | TCG_REG_B0 = 0,
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55 | 477ba620 | Aurelien Jarno | TCG_REG_B1, |
56 | 477ba620 | Aurelien Jarno | TCG_REG_B2, |
57 | 477ba620 | Aurelien Jarno | TCG_REG_B3, |
58 | 477ba620 | Aurelien Jarno | TCG_REG_B4, |
59 | 477ba620 | Aurelien Jarno | TCG_REG_B5, |
60 | 477ba620 | Aurelien Jarno | TCG_REG_B6, |
61 | 477ba620 | Aurelien Jarno | TCG_REG_B7, |
62 | 477ba620 | Aurelien Jarno | }; |
63 | 477ba620 | Aurelien Jarno | |
64 | 477ba620 | Aurelien Jarno | /* Floating point registers */
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65 | 477ba620 | Aurelien Jarno | enum {
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66 | 477ba620 | Aurelien Jarno | TCG_REG_F0 = 0,
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67 | 477ba620 | Aurelien Jarno | TCG_REG_F1, |
68 | 477ba620 | Aurelien Jarno | TCG_REG_F2, |
69 | 477ba620 | Aurelien Jarno | TCG_REG_F3, |
70 | 477ba620 | Aurelien Jarno | TCG_REG_F4, |
71 | 477ba620 | Aurelien Jarno | TCG_REG_F5, |
72 | 477ba620 | Aurelien Jarno | TCG_REG_F6, |
73 | 477ba620 | Aurelien Jarno | TCG_REG_F7, |
74 | 477ba620 | Aurelien Jarno | TCG_REG_F8, |
75 | 477ba620 | Aurelien Jarno | TCG_REG_F9, |
76 | 477ba620 | Aurelien Jarno | TCG_REG_F10, |
77 | 477ba620 | Aurelien Jarno | TCG_REG_F11, |
78 | 477ba620 | Aurelien Jarno | TCG_REG_F12, |
79 | 477ba620 | Aurelien Jarno | TCG_REG_F13, |
80 | 477ba620 | Aurelien Jarno | TCG_REG_F14, |
81 | 477ba620 | Aurelien Jarno | TCG_REG_F15, |
82 | 477ba620 | Aurelien Jarno | }; |
83 | 477ba620 | Aurelien Jarno | |
84 | 477ba620 | Aurelien Jarno | /* Predicate registers */
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85 | 477ba620 | Aurelien Jarno | enum {
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86 | 477ba620 | Aurelien Jarno | TCG_REG_P0 = 0,
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87 | 477ba620 | Aurelien Jarno | TCG_REG_P1, |
88 | 477ba620 | Aurelien Jarno | TCG_REG_P2, |
89 | 477ba620 | Aurelien Jarno | TCG_REG_P3, |
90 | 477ba620 | Aurelien Jarno | TCG_REG_P4, |
91 | 477ba620 | Aurelien Jarno | TCG_REG_P5, |
92 | 477ba620 | Aurelien Jarno | TCG_REG_P6, |
93 | 477ba620 | Aurelien Jarno | TCG_REG_P7, |
94 | 477ba620 | Aurelien Jarno | TCG_REG_P8, |
95 | 477ba620 | Aurelien Jarno | TCG_REG_P9, |
96 | 477ba620 | Aurelien Jarno | TCG_REG_P10, |
97 | 477ba620 | Aurelien Jarno | TCG_REG_P11, |
98 | 477ba620 | Aurelien Jarno | TCG_REG_P12, |
99 | 477ba620 | Aurelien Jarno | TCG_REG_P13, |
100 | 477ba620 | Aurelien Jarno | TCG_REG_P14, |
101 | 477ba620 | Aurelien Jarno | TCG_REG_P15, |
102 | 477ba620 | Aurelien Jarno | }; |
103 | 477ba620 | Aurelien Jarno | |
104 | 477ba620 | Aurelien Jarno | /* Application registers */
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105 | 477ba620 | Aurelien Jarno | enum {
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106 | 477ba620 | Aurelien Jarno | TCG_REG_PFS = 64,
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107 | 477ba620 | Aurelien Jarno | }; |
108 | 477ba620 | Aurelien Jarno | |
109 | 477ba620 | Aurelien Jarno | static const int tcg_target_reg_alloc_order[] = { |
110 | 477ba620 | Aurelien Jarno | TCG_REG_R34, |
111 | 477ba620 | Aurelien Jarno | TCG_REG_R35, |
112 | 477ba620 | Aurelien Jarno | TCG_REG_R36, |
113 | 477ba620 | Aurelien Jarno | TCG_REG_R37, |
114 | 477ba620 | Aurelien Jarno | TCG_REG_R38, |
115 | 477ba620 | Aurelien Jarno | TCG_REG_R39, |
116 | 477ba620 | Aurelien Jarno | TCG_REG_R40, |
117 | 477ba620 | Aurelien Jarno | TCG_REG_R41, |
118 | 477ba620 | Aurelien Jarno | TCG_REG_R42, |
119 | 477ba620 | Aurelien Jarno | TCG_REG_R43, |
120 | 477ba620 | Aurelien Jarno | TCG_REG_R44, |
121 | 477ba620 | Aurelien Jarno | TCG_REG_R45, |
122 | 477ba620 | Aurelien Jarno | TCG_REG_R46, |
123 | 477ba620 | Aurelien Jarno | TCG_REG_R47, |
124 | 477ba620 | Aurelien Jarno | TCG_REG_R48, |
125 | 477ba620 | Aurelien Jarno | TCG_REG_R49, |
126 | 477ba620 | Aurelien Jarno | TCG_REG_R50, |
127 | 477ba620 | Aurelien Jarno | TCG_REG_R51, |
128 | 477ba620 | Aurelien Jarno | TCG_REG_R52, |
129 | 477ba620 | Aurelien Jarno | TCG_REG_R53, |
130 | 477ba620 | Aurelien Jarno | TCG_REG_R54, |
131 | 477ba620 | Aurelien Jarno | TCG_REG_R55, |
132 | 477ba620 | Aurelien Jarno | TCG_REG_R14, |
133 | 477ba620 | Aurelien Jarno | TCG_REG_R15, |
134 | 477ba620 | Aurelien Jarno | TCG_REG_R16, |
135 | 477ba620 | Aurelien Jarno | TCG_REG_R17, |
136 | 477ba620 | Aurelien Jarno | TCG_REG_R18, |
137 | 477ba620 | Aurelien Jarno | TCG_REG_R19, |
138 | 477ba620 | Aurelien Jarno | TCG_REG_R20, |
139 | 477ba620 | Aurelien Jarno | TCG_REG_R21, |
140 | 477ba620 | Aurelien Jarno | TCG_REG_R22, |
141 | 477ba620 | Aurelien Jarno | TCG_REG_R23, |
142 | 477ba620 | Aurelien Jarno | TCG_REG_R24, |
143 | 477ba620 | Aurelien Jarno | TCG_REG_R25, |
144 | 477ba620 | Aurelien Jarno | TCG_REG_R26, |
145 | 477ba620 | Aurelien Jarno | TCG_REG_R27, |
146 | 477ba620 | Aurelien Jarno | TCG_REG_R28, |
147 | 477ba620 | Aurelien Jarno | TCG_REG_R29, |
148 | 477ba620 | Aurelien Jarno | TCG_REG_R30, |
149 | 477ba620 | Aurelien Jarno | TCG_REG_R31, |
150 | 477ba620 | Aurelien Jarno | TCG_REG_R56, |
151 | 477ba620 | Aurelien Jarno | TCG_REG_R57, |
152 | 477ba620 | Aurelien Jarno | TCG_REG_R58, |
153 | 477ba620 | Aurelien Jarno | TCG_REG_R59, |
154 | 477ba620 | Aurelien Jarno | TCG_REG_R60, |
155 | 477ba620 | Aurelien Jarno | TCG_REG_R61, |
156 | 477ba620 | Aurelien Jarno | TCG_REG_R62, |
157 | 477ba620 | Aurelien Jarno | TCG_REG_R63, |
158 | 477ba620 | Aurelien Jarno | TCG_REG_R8, |
159 | 477ba620 | Aurelien Jarno | TCG_REG_R9, |
160 | 477ba620 | Aurelien Jarno | TCG_REG_R10, |
161 | 477ba620 | Aurelien Jarno | TCG_REG_R11 |
162 | 477ba620 | Aurelien Jarno | }; |
163 | 477ba620 | Aurelien Jarno | |
164 | 477ba620 | Aurelien Jarno | static const int tcg_target_call_iarg_regs[8] = { |
165 | 477ba620 | Aurelien Jarno | TCG_REG_R56, |
166 | 477ba620 | Aurelien Jarno | TCG_REG_R57, |
167 | 477ba620 | Aurelien Jarno | TCG_REG_R58, |
168 | 477ba620 | Aurelien Jarno | TCG_REG_R59, |
169 | 477ba620 | Aurelien Jarno | TCG_REG_R60, |
170 | 477ba620 | Aurelien Jarno | TCG_REG_R61, |
171 | 477ba620 | Aurelien Jarno | TCG_REG_R62, |
172 | 477ba620 | Aurelien Jarno | TCG_REG_R63, |
173 | 477ba620 | Aurelien Jarno | }; |
174 | 477ba620 | Aurelien Jarno | |
175 | 477ba620 | Aurelien Jarno | static const int tcg_target_call_oarg_regs[2] = { |
176 | 477ba620 | Aurelien Jarno | TCG_REG_R8, |
177 | 477ba620 | Aurelien Jarno | TCG_REG_R9 |
178 | 477ba620 | Aurelien Jarno | }; |
179 | 477ba620 | Aurelien Jarno | |
180 | 477ba620 | Aurelien Jarno | /* maximum number of register used for input function arguments */
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181 | 477ba620 | Aurelien Jarno | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
182 | 477ba620 | Aurelien Jarno | { |
183 | 477ba620 | Aurelien Jarno | return 8; |
184 | 477ba620 | Aurelien Jarno | } |
185 | 477ba620 | Aurelien Jarno | |
186 | 477ba620 | Aurelien Jarno | /*
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187 | 477ba620 | Aurelien Jarno | * opcode formation
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188 | 477ba620 | Aurelien Jarno | */
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189 | 477ba620 | Aurelien Jarno | |
190 | 477ba620 | Aurelien Jarno | /* bundle templates: stops (double bar in the IA64 manual) are marked with
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191 | 477ba620 | Aurelien Jarno | an uppercase letter. */
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192 | 477ba620 | Aurelien Jarno | enum {
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193 | 477ba620 | Aurelien Jarno | mii = 0x00,
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194 | 477ba620 | Aurelien Jarno | miI = 0x01,
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195 | 477ba620 | Aurelien Jarno | mIi = 0x02,
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196 | 477ba620 | Aurelien Jarno | mII = 0x03,
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197 | 477ba620 | Aurelien Jarno | mlx = 0x04,
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198 | 477ba620 | Aurelien Jarno | mLX = 0x05,
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199 | 477ba620 | Aurelien Jarno | mmi = 0x08,
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200 | 477ba620 | Aurelien Jarno | mmI = 0x09,
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201 | 477ba620 | Aurelien Jarno | Mmi = 0x0a,
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202 | 477ba620 | Aurelien Jarno | MmI = 0x0b,
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203 | 477ba620 | Aurelien Jarno | mfi = 0x0c,
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204 | 477ba620 | Aurelien Jarno | mfI = 0x0d,
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205 | 477ba620 | Aurelien Jarno | mmf = 0x0e,
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206 | 477ba620 | Aurelien Jarno | mmF = 0x0f,
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207 | 477ba620 | Aurelien Jarno | mib = 0x10,
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208 | 477ba620 | Aurelien Jarno | miB = 0x11,
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209 | 477ba620 | Aurelien Jarno | mbb = 0x12,
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210 | 477ba620 | Aurelien Jarno | mbB = 0x13,
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211 | 477ba620 | Aurelien Jarno | bbb = 0x16,
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212 | 477ba620 | Aurelien Jarno | bbB = 0x17,
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213 | 477ba620 | Aurelien Jarno | mmb = 0x18,
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214 | 477ba620 | Aurelien Jarno | mmB = 0x19,
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215 | 477ba620 | Aurelien Jarno | mfb = 0x1c,
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216 | 477ba620 | Aurelien Jarno | mfB = 0x1d,
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217 | 477ba620 | Aurelien Jarno | }; |
218 | 477ba620 | Aurelien Jarno | |
219 | 477ba620 | Aurelien Jarno | enum {
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220 | 477ba620 | Aurelien Jarno | OPC_ADD_A1 = 0x10000000000ull,
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221 | 477ba620 | Aurelien Jarno | OPC_AND_A1 = 0x10060000000ull,
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222 | 477ba620 | Aurelien Jarno | OPC_AND_A3 = 0x10160000000ull,
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223 | 477ba620 | Aurelien Jarno | OPC_ANDCM_A1 = 0x10068000000ull,
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224 | 477ba620 | Aurelien Jarno | OPC_ANDCM_A3 = 0x10168000000ull,
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225 | 477ba620 | Aurelien Jarno | OPC_ADDS_A4 = 0x10800000000ull,
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226 | 477ba620 | Aurelien Jarno | OPC_ADDL_A5 = 0x12000000000ull,
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227 | 477ba620 | Aurelien Jarno | OPC_ALLOC_M34 = 0x02c00000000ull,
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228 | 477ba620 | Aurelien Jarno | OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
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229 | 477ba620 | Aurelien Jarno | OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
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230 | 477ba620 | Aurelien Jarno | OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
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231 | 477ba620 | Aurelien Jarno | OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
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232 | 477ba620 | Aurelien Jarno | OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
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233 | 477ba620 | Aurelien Jarno | OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
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234 | 477ba620 | Aurelien Jarno | OPC_CMP_LT_A6 = 0x18000000000ull,
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235 | 477ba620 | Aurelien Jarno | OPC_CMP_LTU_A6 = 0x1a000000000ull,
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236 | 477ba620 | Aurelien Jarno | OPC_CMP_EQ_A6 = 0x1c000000000ull,
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237 | 477ba620 | Aurelien Jarno | OPC_CMP4_LT_A6 = 0x18400000000ull,
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238 | 477ba620 | Aurelien Jarno | OPC_CMP4_LTU_A6 = 0x1a400000000ull,
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239 | 477ba620 | Aurelien Jarno | OPC_CMP4_EQ_A6 = 0x1c400000000ull,
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240 | 477ba620 | Aurelien Jarno | OPC_DEP_Z_I12 = 0x0a600000000ull,
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241 | 477ba620 | Aurelien Jarno | OPC_EXTR_I11 = 0x0a400002000ull,
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242 | 477ba620 | Aurelien Jarno | OPC_EXTR_U_I11 = 0x0a400000000ull,
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243 | 477ba620 | Aurelien Jarno | OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
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244 | 477ba620 | Aurelien Jarno | OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
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245 | 477ba620 | Aurelien Jarno | OPC_FCVT_XF_F11 = 0x000e0000000ull,
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246 | 477ba620 | Aurelien Jarno | OPC_FMA_S1_F1 = 0x10400000000ull,
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247 | 477ba620 | Aurelien Jarno | OPC_FNMA_S1_F1 = 0x18400000000ull,
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248 | 477ba620 | Aurelien Jarno | OPC_FRCPA_S1_F6 = 0x00600000000ull,
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249 | 477ba620 | Aurelien Jarno | OPC_GETF_SIG_M19 = 0x08708000000ull,
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250 | 477ba620 | Aurelien Jarno | OPC_LD1_M1 = 0x08000000000ull,
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251 | 477ba620 | Aurelien Jarno | OPC_LD1_M3 = 0x0a000000000ull,
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252 | 477ba620 | Aurelien Jarno | OPC_LD2_M1 = 0x08040000000ull,
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253 | 477ba620 | Aurelien Jarno | OPC_LD2_M3 = 0x0a040000000ull,
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254 | 477ba620 | Aurelien Jarno | OPC_LD4_M1 = 0x08080000000ull,
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255 | 477ba620 | Aurelien Jarno | OPC_LD4_M3 = 0x0a080000000ull,
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256 | 477ba620 | Aurelien Jarno | OPC_LD8_M1 = 0x080c0000000ull,
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257 | 477ba620 | Aurelien Jarno | OPC_LD8_M3 = 0x0a0c0000000ull,
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258 | 477ba620 | Aurelien Jarno | OPC_MUX1_I3 = 0x0eca0000000ull,
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259 | 477ba620 | Aurelien Jarno | OPC_NOP_B9 = 0x04008000000ull,
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260 | 477ba620 | Aurelien Jarno | OPC_NOP_F16 = 0x00008000000ull,
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261 | 477ba620 | Aurelien Jarno | OPC_NOP_I18 = 0x00008000000ull,
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262 | 477ba620 | Aurelien Jarno | OPC_NOP_M48 = 0x00008000000ull,
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263 | 477ba620 | Aurelien Jarno | OPC_MOV_I21 = 0x00e00100000ull,
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264 | 477ba620 | Aurelien Jarno | OPC_MOV_RET_I21 = 0x00e00500000ull,
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265 | 477ba620 | Aurelien Jarno | OPC_MOV_I22 = 0x00188000000ull,
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266 | 477ba620 | Aurelien Jarno | OPC_MOV_I_I26 = 0x00150000000ull,
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267 | 477ba620 | Aurelien Jarno | OPC_MOVL_X2 = 0x0c000000000ull,
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268 | 477ba620 | Aurelien Jarno | OPC_OR_A1 = 0x10070000000ull,
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269 | 477ba620 | Aurelien Jarno | OPC_SETF_EXP_M18 = 0x0c748000000ull,
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270 | 477ba620 | Aurelien Jarno | OPC_SETF_SIG_M18 = 0x0c708000000ull,
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271 | 477ba620 | Aurelien Jarno | OPC_SHL_I7 = 0x0f240000000ull,
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272 | 477ba620 | Aurelien Jarno | OPC_SHR_I5 = 0x0f220000000ull,
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273 | 477ba620 | Aurelien Jarno | OPC_SHR_U_I5 = 0x0f200000000ull,
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274 | 477ba620 | Aurelien Jarno | OPC_SHRP_I10 = 0x0ac00000000ull,
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275 | 477ba620 | Aurelien Jarno | OPC_SXT1_I29 = 0x000a0000000ull,
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276 | 477ba620 | Aurelien Jarno | OPC_SXT2_I29 = 0x000a8000000ull,
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277 | 477ba620 | Aurelien Jarno | OPC_SXT4_I29 = 0x000b0000000ull,
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278 | 477ba620 | Aurelien Jarno | OPC_ST1_M4 = 0x08c00000000ull,
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279 | 477ba620 | Aurelien Jarno | OPC_ST2_M4 = 0x08c40000000ull,
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280 | 477ba620 | Aurelien Jarno | OPC_ST4_M4 = 0x08c80000000ull,
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281 | 477ba620 | Aurelien Jarno | OPC_ST8_M4 = 0x08cc0000000ull,
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282 | 477ba620 | Aurelien Jarno | OPC_SUB_A1 = 0x10028000000ull,
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283 | 477ba620 | Aurelien Jarno | OPC_SUB_A3 = 0x10128000000ull,
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284 | 477ba620 | Aurelien Jarno | OPC_UNPACK4_L_I2 = 0x0f860000000ull,
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285 | 477ba620 | Aurelien Jarno | OPC_XMA_L_F2 = 0x1d000000000ull,
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286 | 477ba620 | Aurelien Jarno | OPC_XOR_A1 = 0x10078000000ull,
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287 | 477ba620 | Aurelien Jarno | OPC_ZXT1_I29 = 0x00080000000ull,
|
288 | 477ba620 | Aurelien Jarno | OPC_ZXT2_I29 = 0x00088000000ull,
|
289 | 477ba620 | Aurelien Jarno | OPC_ZXT4_I29 = 0x00090000000ull,
|
290 | 477ba620 | Aurelien Jarno | }; |
291 | 477ba620 | Aurelien Jarno | |
292 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1, |
293 | 477ba620 | Aurelien Jarno | int r2, int r3) |
294 | 477ba620 | Aurelien Jarno | { |
295 | 477ba620 | Aurelien Jarno | return opc
|
296 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
297 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
298 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
299 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
300 | 477ba620 | Aurelien Jarno | } |
301 | 477ba620 | Aurelien Jarno | |
302 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1, |
303 | 477ba620 | Aurelien Jarno | uint64_t imm, int r3)
|
304 | 477ba620 | Aurelien Jarno | { |
305 | 477ba620 | Aurelien Jarno | return opc
|
306 | 477ba620 | Aurelien Jarno | | ((imm & 0x80) << 29) /* s */ |
307 | 477ba620 | Aurelien Jarno | | ((imm & 0x7f) << 13) /* imm7b */ |
308 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
309 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
310 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
311 | 477ba620 | Aurelien Jarno | } |
312 | 477ba620 | Aurelien Jarno | |
313 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1, |
314 | 477ba620 | Aurelien Jarno | uint64_t imm, int r3)
|
315 | 477ba620 | Aurelien Jarno | { |
316 | 477ba620 | Aurelien Jarno | return opc
|
317 | 477ba620 | Aurelien Jarno | | ((imm & 0x2000) << 23) /* s */ |
318 | 477ba620 | Aurelien Jarno | | ((imm & 0x1f80) << 20) /* imm6d */ |
319 | 477ba620 | Aurelien Jarno | | ((imm & 0x007f) << 13) /* imm7b */ |
320 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
321 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
322 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
323 | 477ba620 | Aurelien Jarno | } |
324 | 477ba620 | Aurelien Jarno | |
325 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1, |
326 | 477ba620 | Aurelien Jarno | uint64_t imm, int r3)
|
327 | 477ba620 | Aurelien Jarno | { |
328 | 477ba620 | Aurelien Jarno | return opc
|
329 | 477ba620 | Aurelien Jarno | | ((imm & 0x200000) << 15) /* s */ |
330 | 477ba620 | Aurelien Jarno | | ((imm & 0x1f0000) << 6) /* imm5c */ |
331 | 477ba620 | Aurelien Jarno | | ((imm & 0x00ff80) << 20) /* imm9d */ |
332 | 477ba620 | Aurelien Jarno | | ((imm & 0x00007f) << 13) /* imm7b */ |
333 | 477ba620 | Aurelien Jarno | | ((r3 & 0x03) << 20) |
334 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
335 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
336 | 477ba620 | Aurelien Jarno | } |
337 | 477ba620 | Aurelien Jarno | |
338 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1, |
339 | 477ba620 | Aurelien Jarno | int p2, int r2, int r3) |
340 | 477ba620 | Aurelien Jarno | { |
341 | 477ba620 | Aurelien Jarno | return opc
|
342 | 477ba620 | Aurelien Jarno | | ((p2 & 0x3f) << 27) |
343 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
344 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
345 | 477ba620 | Aurelien Jarno | | ((p1 & 0x3f) << 6) |
346 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
347 | 477ba620 | Aurelien Jarno | } |
348 | 477ba620 | Aurelien Jarno | |
349 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm) |
350 | 477ba620 | Aurelien Jarno | { |
351 | 477ba620 | Aurelien Jarno | return opc
|
352 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) << 16) /* s */ |
353 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffff) << 13) /* imm20b */ |
354 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
355 | 477ba620 | Aurelien Jarno | } |
356 | 477ba620 | Aurelien Jarno | |
357 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2) |
358 | 477ba620 | Aurelien Jarno | { |
359 | 477ba620 | Aurelien Jarno | return opc
|
360 | 477ba620 | Aurelien Jarno | | ((b2 & 0x7) << 13) |
361 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
362 | 477ba620 | Aurelien Jarno | } |
363 | 477ba620 | Aurelien Jarno | |
364 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2) |
365 | 477ba620 | Aurelien Jarno | { |
366 | 477ba620 | Aurelien Jarno | return opc
|
367 | 477ba620 | Aurelien Jarno | | ((b2 & 0x7) << 13) |
368 | 477ba620 | Aurelien Jarno | | ((b1 & 0x7) << 6) |
369 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
370 | 477ba620 | Aurelien Jarno | } |
371 | 477ba620 | Aurelien Jarno | |
372 | 477ba620 | Aurelien Jarno | |
373 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm) |
374 | 477ba620 | Aurelien Jarno | { |
375 | 477ba620 | Aurelien Jarno | return opc
|
376 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) << 16) /* i */ |
377 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffff) << 6) /* imm20a */ |
378 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
379 | 477ba620 | Aurelien Jarno | } |
380 | 477ba620 | Aurelien Jarno | |
381 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1, |
382 | 477ba620 | Aurelien Jarno | int f3, int f4, int f2) |
383 | 477ba620 | Aurelien Jarno | { |
384 | 477ba620 | Aurelien Jarno | return opc
|
385 | 477ba620 | Aurelien Jarno | | ((f4 & 0x7f) << 27) |
386 | 477ba620 | Aurelien Jarno | | ((f3 & 0x7f) << 20) |
387 | 477ba620 | Aurelien Jarno | | ((f2 & 0x7f) << 13) |
388 | 477ba620 | Aurelien Jarno | | ((f1 & 0x7f) << 6) |
389 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
390 | 477ba620 | Aurelien Jarno | } |
391 | 477ba620 | Aurelien Jarno | |
392 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1, |
393 | 477ba620 | Aurelien Jarno | int f3, int f4, int f2) |
394 | 477ba620 | Aurelien Jarno | { |
395 | 477ba620 | Aurelien Jarno | return opc
|
396 | 477ba620 | Aurelien Jarno | | ((f4 & 0x7f) << 27) |
397 | 477ba620 | Aurelien Jarno | | ((f3 & 0x7f) << 20) |
398 | 477ba620 | Aurelien Jarno | | ((f2 & 0x7f) << 13) |
399 | 477ba620 | Aurelien Jarno | | ((f1 & 0x7f) << 6) |
400 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
401 | 477ba620 | Aurelien Jarno | } |
402 | 477ba620 | Aurelien Jarno | |
403 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1, |
404 | 477ba620 | Aurelien Jarno | int p2, int f2, int f3) |
405 | 477ba620 | Aurelien Jarno | { |
406 | 477ba620 | Aurelien Jarno | return opc
|
407 | 477ba620 | Aurelien Jarno | | ((p2 & 0x3f) << 27) |
408 | 477ba620 | Aurelien Jarno | | ((f3 & 0x7f) << 20) |
409 | 477ba620 | Aurelien Jarno | | ((f2 & 0x7f) << 13) |
410 | 477ba620 | Aurelien Jarno | | ((f1 & 0x7f) << 6) |
411 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
412 | 477ba620 | Aurelien Jarno | } |
413 | 477ba620 | Aurelien Jarno | |
414 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2) |
415 | 477ba620 | Aurelien Jarno | { |
416 | 477ba620 | Aurelien Jarno | return opc
|
417 | 477ba620 | Aurelien Jarno | | ((f2 & 0x7f) << 13) |
418 | 477ba620 | Aurelien Jarno | | ((f1 & 0x7f) << 6) |
419 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
420 | 477ba620 | Aurelien Jarno | } |
421 | 477ba620 | Aurelien Jarno | |
422 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2) |
423 | 477ba620 | Aurelien Jarno | { |
424 | 477ba620 | Aurelien Jarno | return opc
|
425 | 477ba620 | Aurelien Jarno | | ((f2 & 0x7f) << 13) |
426 | 477ba620 | Aurelien Jarno | | ((f1 & 0x7f) << 6) |
427 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
428 | 477ba620 | Aurelien Jarno | } |
429 | 477ba620 | Aurelien Jarno | |
430 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm) |
431 | 477ba620 | Aurelien Jarno | { |
432 | 477ba620 | Aurelien Jarno | return opc
|
433 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) << 16) /* i */ |
434 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffff) << 6) /* imm20a */ |
435 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
436 | 477ba620 | Aurelien Jarno | } |
437 | 477ba620 | Aurelien Jarno | |
438 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1, |
439 | 477ba620 | Aurelien Jarno | int r2, int r3) |
440 | 477ba620 | Aurelien Jarno | { |
441 | 477ba620 | Aurelien Jarno | return opc
|
442 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
443 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
444 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
445 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
446 | 477ba620 | Aurelien Jarno | } |
447 | 477ba620 | Aurelien Jarno | |
448 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1, |
449 | 477ba620 | Aurelien Jarno | int r2, int mbtype) |
450 | 477ba620 | Aurelien Jarno | { |
451 | 477ba620 | Aurelien Jarno | return opc
|
452 | 477ba620 | Aurelien Jarno | | ((mbtype & 0x0f) << 20) |
453 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
454 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
455 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
456 | 477ba620 | Aurelien Jarno | } |
457 | 477ba620 | Aurelien Jarno | |
458 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1, |
459 | 477ba620 | Aurelien Jarno | int r3, int r2) |
460 | 477ba620 | Aurelien Jarno | { |
461 | 477ba620 | Aurelien Jarno | return opc
|
462 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
463 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
464 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
465 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
466 | 477ba620 | Aurelien Jarno | } |
467 | 477ba620 | Aurelien Jarno | |
468 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1, |
469 | 477ba620 | Aurelien Jarno | int r2, int r3) |
470 | 477ba620 | Aurelien Jarno | { |
471 | 477ba620 | Aurelien Jarno | return opc
|
472 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
473 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
474 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
475 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
476 | 477ba620 | Aurelien Jarno | } |
477 | 477ba620 | Aurelien Jarno | |
478 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1, |
479 | 477ba620 | Aurelien Jarno | int r2, int r3, uint64_t count) |
480 | 477ba620 | Aurelien Jarno | { |
481 | 477ba620 | Aurelien Jarno | return opc
|
482 | 477ba620 | Aurelien Jarno | | ((count & 0x3f) << 27) |
483 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
484 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
485 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
486 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
487 | 477ba620 | Aurelien Jarno | } |
488 | 477ba620 | Aurelien Jarno | |
489 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1, |
490 | 477ba620 | Aurelien Jarno | int r3, uint64_t pos, uint64_t len)
|
491 | 477ba620 | Aurelien Jarno | { |
492 | 477ba620 | Aurelien Jarno | return opc
|
493 | 477ba620 | Aurelien Jarno | | ((len & 0x3f) << 27) |
494 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
495 | 477ba620 | Aurelien Jarno | | ((pos & 0x3f) << 14) |
496 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
497 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
498 | 477ba620 | Aurelien Jarno | } |
499 | 477ba620 | Aurelien Jarno | |
500 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1, |
501 | 477ba620 | Aurelien Jarno | int r2, uint64_t pos, uint64_t len)
|
502 | 477ba620 | Aurelien Jarno | { |
503 | 477ba620 | Aurelien Jarno | return opc
|
504 | 477ba620 | Aurelien Jarno | | ((len & 0x3f) << 27) |
505 | 477ba620 | Aurelien Jarno | | ((pos & 0x3f) << 20) |
506 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
507 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
508 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
509 | 477ba620 | Aurelien Jarno | } |
510 | 477ba620 | Aurelien Jarno | |
511 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm) |
512 | 477ba620 | Aurelien Jarno | { |
513 | 477ba620 | Aurelien Jarno | return opc
|
514 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) << 16) /* i */ |
515 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffff) << 6) /* imm20a */ |
516 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
517 | 477ba620 | Aurelien Jarno | } |
518 | 477ba620 | Aurelien Jarno | |
519 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1, |
520 | 477ba620 | Aurelien Jarno | int r2, uint64_t imm)
|
521 | 477ba620 | Aurelien Jarno | { |
522 | 477ba620 | Aurelien Jarno | return opc
|
523 | 477ba620 | Aurelien Jarno | | ((imm & 0x1ff) << 24) |
524 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
525 | 477ba620 | Aurelien Jarno | | ((b1 & 0x7) << 6) |
526 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
527 | 477ba620 | Aurelien Jarno | } |
528 | 477ba620 | Aurelien Jarno | |
529 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2) |
530 | 477ba620 | Aurelien Jarno | { |
531 | 477ba620 | Aurelien Jarno | return opc
|
532 | 477ba620 | Aurelien Jarno | | ((b2 & 0x7) << 13) |
533 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
534 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
535 | 477ba620 | Aurelien Jarno | } |
536 | 477ba620 | Aurelien Jarno | |
537 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2) |
538 | 477ba620 | Aurelien Jarno | { |
539 | 477ba620 | Aurelien Jarno | return opc
|
540 | 477ba620 | Aurelien Jarno | | ((ar3 & 0x7f) << 20) |
541 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
542 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
543 | 477ba620 | Aurelien Jarno | } |
544 | 477ba620 | Aurelien Jarno | |
545 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3) |
546 | 477ba620 | Aurelien Jarno | { |
547 | 477ba620 | Aurelien Jarno | return opc
|
548 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
549 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
550 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
551 | 477ba620 | Aurelien Jarno | } |
552 | 477ba620 | Aurelien Jarno | |
553 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_l2(uint64_t imm) |
554 | 477ba620 | Aurelien Jarno | { |
555 | 477ba620 | Aurelien Jarno | return (imm & 0x7fffffffffc00000ull) >> 22; |
556 | 477ba620 | Aurelien Jarno | } |
557 | 477ba620 | Aurelien Jarno | |
558 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_l3(uint64_t imm) |
559 | 477ba620 | Aurelien Jarno | { |
560 | 477ba620 | Aurelien Jarno | return (imm & 0x07fffffffff00000ull) >> 18; |
561 | 477ba620 | Aurelien Jarno | } |
562 | 477ba620 | Aurelien Jarno | |
563 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3) |
564 | 477ba620 | Aurelien Jarno | { |
565 | 477ba620 | Aurelien Jarno | return opc
|
566 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
567 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
568 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
569 | 477ba620 | Aurelien Jarno | } |
570 | 477ba620 | Aurelien Jarno | |
571 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1, |
572 | 477ba620 | Aurelien Jarno | int r3, uint64_t imm)
|
573 | 477ba620 | Aurelien Jarno | { |
574 | 477ba620 | Aurelien Jarno | return opc
|
575 | 477ba620 | Aurelien Jarno | | ((imm & 0x100) << 28) /* s */ |
576 | 477ba620 | Aurelien Jarno | | ((imm & 0x080) << 20) /* i */ |
577 | 477ba620 | Aurelien Jarno | | ((imm & 0x07f) << 13) /* imm7b */ |
578 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
579 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
580 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
581 | 477ba620 | Aurelien Jarno | } |
582 | 477ba620 | Aurelien Jarno | |
583 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3) |
584 | 477ba620 | Aurelien Jarno | { |
585 | 477ba620 | Aurelien Jarno | return opc
|
586 | 477ba620 | Aurelien Jarno | | ((r3 & 0x7f) << 20) |
587 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
588 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
589 | 477ba620 | Aurelien Jarno | } |
590 | 477ba620 | Aurelien Jarno | |
591 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2) |
592 | 477ba620 | Aurelien Jarno | { |
593 | 477ba620 | Aurelien Jarno | return opc
|
594 | 477ba620 | Aurelien Jarno | | ((r2 & 0x7f) << 13) |
595 | 477ba620 | Aurelien Jarno | | ((f1 & 0x7f) << 6) |
596 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
597 | 477ba620 | Aurelien Jarno | } |
598 | 477ba620 | Aurelien Jarno | |
599 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2) |
600 | 477ba620 | Aurelien Jarno | { |
601 | 477ba620 | Aurelien Jarno | return opc
|
602 | 477ba620 | Aurelien Jarno | | ((f2 & 0x7f) << 13) |
603 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
604 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
605 | 477ba620 | Aurelien Jarno | } |
606 | 477ba620 | Aurelien Jarno | |
607 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1, |
608 | 477ba620 | Aurelien Jarno | int sof, int sol, int sor) |
609 | 477ba620 | Aurelien Jarno | { |
610 | 477ba620 | Aurelien Jarno | return opc
|
611 | 477ba620 | Aurelien Jarno | | ((sor & 0x0f) << 27) |
612 | 477ba620 | Aurelien Jarno | | ((sol & 0x7f) << 20) |
613 | 477ba620 | Aurelien Jarno | | ((sof & 0x7f) << 13) |
614 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
615 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
616 | 477ba620 | Aurelien Jarno | } |
617 | 477ba620 | Aurelien Jarno | |
618 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm) |
619 | 477ba620 | Aurelien Jarno | { |
620 | 477ba620 | Aurelien Jarno | return opc
|
621 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) << 16) /* i */ |
622 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffff) << 6) /* imm20a */ |
623 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
624 | 477ba620 | Aurelien Jarno | } |
625 | 477ba620 | Aurelien Jarno | |
626 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_x2(int qp, uint64_t opc, |
627 | 477ba620 | Aurelien Jarno | int r1, uint64_t imm)
|
628 | 477ba620 | Aurelien Jarno | { |
629 | 477ba620 | Aurelien Jarno | return opc
|
630 | 477ba620 | Aurelien Jarno | | ((imm & 0x8000000000000000ull) >> 27) /* i */ |
631 | 477ba620 | Aurelien Jarno | | (imm & 0x0000000000200000ull) /* ic */ |
632 | 477ba620 | Aurelien Jarno | | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */ |
633 | 477ba620 | Aurelien Jarno | | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */ |
634 | 477ba620 | Aurelien Jarno | | ((imm & 0x000000000000007full) << 13) /* imm7b */ |
635 | 477ba620 | Aurelien Jarno | | ((r1 & 0x7f) << 6) |
636 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
637 | 477ba620 | Aurelien Jarno | } |
638 | 477ba620 | Aurelien Jarno | |
639 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm) |
640 | 477ba620 | Aurelien Jarno | { |
641 | 477ba620 | Aurelien Jarno | return opc
|
642 | 477ba620 | Aurelien Jarno | | ((imm & 0x0800000000000000ull) >> 23) /* i */ |
643 | 477ba620 | Aurelien Jarno | | ((imm & 0x00000000000fffffull) << 13) /* imm20b */ |
644 | 477ba620 | Aurelien Jarno | | (qp & 0x3f);
|
645 | 477ba620 | Aurelien Jarno | } |
646 | 477ba620 | Aurelien Jarno | |
647 | 477ba620 | Aurelien Jarno | |
648 | 477ba620 | Aurelien Jarno | /*
|
649 | 477ba620 | Aurelien Jarno | * Relocations
|
650 | 477ba620 | Aurelien Jarno | */
|
651 | 477ba620 | Aurelien Jarno | |
652 | 477ba620 | Aurelien Jarno | static inline void reloc_pcrel21b (void *pc, tcg_target_long target) |
653 | 477ba620 | Aurelien Jarno | { |
654 | 477ba620 | Aurelien Jarno | uint64_t imm; |
655 | 477ba620 | Aurelien Jarno | int64_t disp; |
656 | 477ba620 | Aurelien Jarno | int slot;
|
657 | 477ba620 | Aurelien Jarno | |
658 | 477ba620 | Aurelien Jarno | slot = (tcg_target_long) pc & 3;
|
659 | 477ba620 | Aurelien Jarno | pc = (void *)((tcg_target_long) pc & ~3); |
660 | 477ba620 | Aurelien Jarno | |
661 | 477ba620 | Aurelien Jarno | disp = target - (tcg_target_long) pc; |
662 | 477ba620 | Aurelien Jarno | imm = (uint64_t) disp >> 4;
|
663 | 477ba620 | Aurelien Jarno | |
664 | 477ba620 | Aurelien Jarno | switch(slot) {
|
665 | 477ba620 | Aurelien Jarno | case 0: |
666 | 477ba620 | Aurelien Jarno | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull) |
667 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) << 21) /* s */ |
668 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffff) << 18); /* imm20b */ |
669 | 477ba620 | Aurelien Jarno | break;
|
670 | 477ba620 | Aurelien Jarno | case 1: |
671 | 477ba620 | Aurelien Jarno | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull) |
672 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) >> 2) /* s */ |
673 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffe0) >> 5); /* imm20b */ |
674 | 477ba620 | Aurelien Jarno | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull) |
675 | 477ba620 | Aurelien Jarno | | ((imm & 0x00001f) << 59); /* imm20b */ |
676 | 477ba620 | Aurelien Jarno | break;
|
677 | 477ba620 | Aurelien Jarno | case 2: |
678 | 477ba620 | Aurelien Jarno | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull) |
679 | 477ba620 | Aurelien Jarno | | ((imm & 0x100000) << 39) /* s */ |
680 | 477ba620 | Aurelien Jarno | | ((imm & 0x0fffff) << 36); /* imm20b */ |
681 | 477ba620 | Aurelien Jarno | break;
|
682 | 477ba620 | Aurelien Jarno | } |
683 | 477ba620 | Aurelien Jarno | } |
684 | 477ba620 | Aurelien Jarno | |
685 | 477ba620 | Aurelien Jarno | static inline uint64_t get_reloc_pcrel21b (void *pc) |
686 | 477ba620 | Aurelien Jarno | { |
687 | 477ba620 | Aurelien Jarno | int64_t low, high; |
688 | 477ba620 | Aurelien Jarno | int slot;
|
689 | 477ba620 | Aurelien Jarno | |
690 | 477ba620 | Aurelien Jarno | slot = (tcg_target_long) pc & 3;
|
691 | 477ba620 | Aurelien Jarno | pc = (void *)((tcg_target_long) pc & ~3); |
692 | 477ba620 | Aurelien Jarno | |
693 | 477ba620 | Aurelien Jarno | low = (*(uint64_t *)(pc + 0));
|
694 | 477ba620 | Aurelien Jarno | high = (*(uint64_t *)(pc + 8));
|
695 | 477ba620 | Aurelien Jarno | |
696 | 477ba620 | Aurelien Jarno | switch(slot) {
|
697 | 477ba620 | Aurelien Jarno | case 0: |
698 | 477ba620 | Aurelien Jarno | return ((low >> 21) & 0x100000) + /* s */ |
699 | 477ba620 | Aurelien Jarno | ((low >> 18) & 0x0fffff); /* imm20b */ |
700 | 477ba620 | Aurelien Jarno | case 1: |
701 | 477ba620 | Aurelien Jarno | return ((high << 2) & 0x100000) + /* s */ |
702 | 477ba620 | Aurelien Jarno | ((high << 5) & 0x0fffe0) + /* imm20b */ |
703 | 477ba620 | Aurelien Jarno | ((low >> 59) & 0x00001f); /* imm20b */ |
704 | 477ba620 | Aurelien Jarno | case 2: |
705 | 477ba620 | Aurelien Jarno | return ((high >> 39) & 0x100000) + /* s */ |
706 | 477ba620 | Aurelien Jarno | ((high >> 36) & 0x0fffff); /* imm20b */ |
707 | 477ba620 | Aurelien Jarno | default:
|
708 | 477ba620 | Aurelien Jarno | tcg_abort(); |
709 | 477ba620 | Aurelien Jarno | } |
710 | 477ba620 | Aurelien Jarno | } |
711 | 477ba620 | Aurelien Jarno | |
712 | 477ba620 | Aurelien Jarno | static inline void reloc_pcrel60b (void *pc, tcg_target_long target) |
713 | 477ba620 | Aurelien Jarno | { |
714 | 477ba620 | Aurelien Jarno | int64_t disp; |
715 | 477ba620 | Aurelien Jarno | uint64_t imm; |
716 | 477ba620 | Aurelien Jarno | |
717 | 477ba620 | Aurelien Jarno | disp = target - (tcg_target_long) pc; |
718 | 477ba620 | Aurelien Jarno | imm = (uint64_t) disp >> 4;
|
719 | 477ba620 | Aurelien Jarno | |
720 | 477ba620 | Aurelien Jarno | *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull) |
721 | 477ba620 | Aurelien Jarno | | (imm & 0x0800000000000000ull) /* s */ |
722 | 477ba620 | Aurelien Jarno | | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */ |
723 | 477ba620 | Aurelien Jarno | | ((imm & 0x00000000000fffffull) << 36); /* imm20b */ |
724 | 477ba620 | Aurelien Jarno | *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull) |
725 | 477ba620 | Aurelien Jarno | | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */ |
726 | 477ba620 | Aurelien Jarno | } |
727 | 477ba620 | Aurelien Jarno | |
728 | 477ba620 | Aurelien Jarno | static inline uint64_t get_reloc_pcrel60b (void *pc) |
729 | 477ba620 | Aurelien Jarno | { |
730 | 477ba620 | Aurelien Jarno | int64_t low, high; |
731 | 477ba620 | Aurelien Jarno | |
732 | 477ba620 | Aurelien Jarno | low = (*(uint64_t *)(pc + 0));
|
733 | 477ba620 | Aurelien Jarno | high = (*(uint64_t *)(pc + 8));
|
734 | 477ba620 | Aurelien Jarno | |
735 | 477ba620 | Aurelien Jarno | return ((high) & 0x0800000000000000ull) + /* s */ |
736 | 477ba620 | Aurelien Jarno | ((high >> 36) & 0x00000000000fffffull) + /* imm20b */ |
737 | 477ba620 | Aurelien Jarno | ((high << 36) & 0x07fffff000000000ull) + /* imm39 */ |
738 | 477ba620 | Aurelien Jarno | ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */ |
739 | 477ba620 | Aurelien Jarno | } |
740 | 477ba620 | Aurelien Jarno | |
741 | 477ba620 | Aurelien Jarno | |
742 | 477ba620 | Aurelien Jarno | static void patch_reloc(uint8_t *code_ptr, int type, |
743 | 477ba620 | Aurelien Jarno | tcg_target_long value, tcg_target_long addend) |
744 | 477ba620 | Aurelien Jarno | { |
745 | 477ba620 | Aurelien Jarno | value += addend; |
746 | 477ba620 | Aurelien Jarno | switch (type) {
|
747 | 477ba620 | Aurelien Jarno | case R_IA64_PCREL21B:
|
748 | 477ba620 | Aurelien Jarno | reloc_pcrel21b(code_ptr, value); |
749 | 477ba620 | Aurelien Jarno | break;
|
750 | 477ba620 | Aurelien Jarno | case R_IA64_PCREL60B:
|
751 | 477ba620 | Aurelien Jarno | reloc_pcrel60b(code_ptr, value); |
752 | 477ba620 | Aurelien Jarno | default:
|
753 | 477ba620 | Aurelien Jarno | tcg_abort(); |
754 | 477ba620 | Aurelien Jarno | } |
755 | 477ba620 | Aurelien Jarno | } |
756 | 477ba620 | Aurelien Jarno | |
757 | 477ba620 | Aurelien Jarno | /*
|
758 | 477ba620 | Aurelien Jarno | * Constraints
|
759 | 477ba620 | Aurelien Jarno | */
|
760 | 477ba620 | Aurelien Jarno | |
761 | 477ba620 | Aurelien Jarno | /* parse target specific constraints */
|
762 | 477ba620 | Aurelien Jarno | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
763 | 477ba620 | Aurelien Jarno | { |
764 | 477ba620 | Aurelien Jarno | const char *ct_str; |
765 | 477ba620 | Aurelien Jarno | |
766 | 477ba620 | Aurelien Jarno | ct_str = *pct_str; |
767 | 477ba620 | Aurelien Jarno | switch(ct_str[0]) { |
768 | 477ba620 | Aurelien Jarno | case 'r': |
769 | 477ba620 | Aurelien Jarno | ct->ct |= TCG_CT_REG; |
770 | 477ba620 | Aurelien Jarno | tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
771 | 477ba620 | Aurelien Jarno | break;
|
772 | 477ba620 | Aurelien Jarno | case 'I': |
773 | 477ba620 | Aurelien Jarno | ct->ct |= TCG_CT_CONST_S22; |
774 | 477ba620 | Aurelien Jarno | break;
|
775 | 477ba620 | Aurelien Jarno | case 'S': |
776 | 477ba620 | Aurelien Jarno | ct->ct |= TCG_CT_REG; |
777 | 477ba620 | Aurelien Jarno | tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
|
778 | 477ba620 | Aurelien Jarno | #if defined(CONFIG_SOFTMMU)
|
779 | 477ba620 | Aurelien Jarno | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56); |
780 | 477ba620 | Aurelien Jarno | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57); |
781 | 477ba620 | Aurelien Jarno | #endif
|
782 | 477ba620 | Aurelien Jarno | break;
|
783 | 477ba620 | Aurelien Jarno | case 'Z': |
784 | 477ba620 | Aurelien Jarno | /* We are cheating a bit here, using the fact that the register
|
785 | 477ba620 | Aurelien Jarno | r0 is also the register number 0. Hence there is no need
|
786 | 477ba620 | Aurelien Jarno | to check for const_args in each instruction. */
|
787 | 477ba620 | Aurelien Jarno | ct->ct |= TCG_CT_CONST_ZERO; |
788 | 477ba620 | Aurelien Jarno | break;
|
789 | 477ba620 | Aurelien Jarno | default:
|
790 | 477ba620 | Aurelien Jarno | return -1; |
791 | 477ba620 | Aurelien Jarno | } |
792 | 477ba620 | Aurelien Jarno | ct_str++; |
793 | 477ba620 | Aurelien Jarno | *pct_str = ct_str; |
794 | 477ba620 | Aurelien Jarno | return 0; |
795 | 477ba620 | Aurelien Jarno | } |
796 | 477ba620 | Aurelien Jarno | |
797 | 477ba620 | Aurelien Jarno | /* test if a constant matches the constraint */
|
798 | 477ba620 | Aurelien Jarno | static inline int tcg_target_const_match(tcg_target_long val, |
799 | 477ba620 | Aurelien Jarno | const TCGArgConstraint *arg_ct)
|
800 | 477ba620 | Aurelien Jarno | { |
801 | 477ba620 | Aurelien Jarno | int ct;
|
802 | 477ba620 | Aurelien Jarno | ct = arg_ct->ct; |
803 | 477ba620 | Aurelien Jarno | if (ct & TCG_CT_CONST)
|
804 | 477ba620 | Aurelien Jarno | return 1; |
805 | 477ba620 | Aurelien Jarno | else if ((ct & TCG_CT_CONST_ZERO) && val == 0) |
806 | 477ba620 | Aurelien Jarno | return 1; |
807 | 477ba620 | Aurelien Jarno | else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10) |
808 | 477ba620 | Aurelien Jarno | return 1; |
809 | 477ba620 | Aurelien Jarno | else
|
810 | 477ba620 | Aurelien Jarno | return 0; |
811 | 477ba620 | Aurelien Jarno | } |
812 | 477ba620 | Aurelien Jarno | |
813 | 477ba620 | Aurelien Jarno | /*
|
814 | 477ba620 | Aurelien Jarno | * Code generation
|
815 | 477ba620 | Aurelien Jarno | */
|
816 | 477ba620 | Aurelien Jarno | |
817 | 477ba620 | Aurelien Jarno | static uint8_t *tb_ret_addr;
|
818 | 477ba620 | Aurelien Jarno | |
819 | 477ba620 | Aurelien Jarno | static inline void tcg_out_bundle(TCGContext *s, int template, |
820 | 477ba620 | Aurelien Jarno | uint64_t slot0, uint64_t slot1, |
821 | 477ba620 | Aurelien Jarno | uint64_t slot2) |
822 | 477ba620 | Aurelien Jarno | { |
823 | 477ba620 | Aurelien Jarno | template &= 0x1f; /* 5 bits */ |
824 | 477ba620 | Aurelien Jarno | slot0 &= 0x1ffffffffffull; /* 41 bits */ |
825 | 477ba620 | Aurelien Jarno | slot1 &= 0x1ffffffffffull; /* 41 bits */ |
826 | 477ba620 | Aurelien Jarno | slot2 &= 0x1ffffffffffull; /* 41 bits */ |
827 | 477ba620 | Aurelien Jarno | |
828 | 477ba620 | Aurelien Jarno | *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template; |
829 | 477ba620 | Aurelien Jarno | *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18); |
830 | 477ba620 | Aurelien Jarno | s->code_ptr += 16;
|
831 | 477ba620 | Aurelien Jarno | } |
832 | 477ba620 | Aurelien Jarno | |
833 | 3b6dac34 | Richard Henderson | static inline void tcg_out_mov(TCGContext *s, TCGType type, |
834 | 3b6dac34 | Richard Henderson | TCGArg ret, TCGArg arg) |
835 | 477ba620 | Aurelien Jarno | { |
836 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmI, |
837 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
838 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
839 | 477ba620 | Aurelien Jarno | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
|
840 | 477ba620 | Aurelien Jarno | } |
841 | 477ba620 | Aurelien Jarno | |
842 | 477ba620 | Aurelien Jarno | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
843 | 477ba620 | Aurelien Jarno | TCGArg reg, tcg_target_long arg) |
844 | 477ba620 | Aurelien Jarno | { |
845 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mLX, |
846 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
847 | 477ba620 | Aurelien Jarno | tcg_opc_l2 (arg), |
848 | 477ba620 | Aurelien Jarno | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg)); |
849 | 477ba620 | Aurelien Jarno | } |
850 | 477ba620 | Aurelien Jarno | |
851 | 477ba620 | Aurelien Jarno | static inline void tcg_out_addi(TCGContext *s, TCGArg reg, tcg_target_long val) |
852 | 477ba620 | Aurelien Jarno | { |
853 | 477ba620 | Aurelien Jarno | if (val == ((int32_t)val << 10) >> 10) { |
854 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
855 | 477ba620 | Aurelien Jarno | tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
856 | 477ba620 | Aurelien Jarno | TCG_REG_R2, val, TCG_REG_R0), |
857 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
858 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg, |
859 | 477ba620 | Aurelien Jarno | reg, TCG_REG_R2)); |
860 | 477ba620 | Aurelien Jarno | } else {
|
861 | 477ba620 | Aurelien Jarno | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, val); |
862 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmI, |
863 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
864 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
865 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg, |
866 | 477ba620 | Aurelien Jarno | reg, TCG_REG_R2)); |
867 | 477ba620 | Aurelien Jarno | } |
868 | 477ba620 | Aurelien Jarno | } |
869 | 477ba620 | Aurelien Jarno | |
870 | 477ba620 | Aurelien Jarno | static void tcg_out_br(TCGContext *s, int label_index) |
871 | 477ba620 | Aurelien Jarno | { |
872 | 477ba620 | Aurelien Jarno | TCGLabel *l = &s->labels[label_index]; |
873 | 477ba620 | Aurelien Jarno | |
874 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmB, |
875 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
876 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
877 | 477ba620 | Aurelien Jarno | tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1, |
878 | 477ba620 | Aurelien Jarno | get_reloc_pcrel21b(s->code_ptr + 2)));
|
879 | 477ba620 | Aurelien Jarno | |
880 | 477ba620 | Aurelien Jarno | if (l->has_value) {
|
881 | 477ba620 | Aurelien Jarno | reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); |
882 | 477ba620 | Aurelien Jarno | } else {
|
883 | 477ba620 | Aurelien Jarno | tcg_out_reloc(s, (s->code_ptr - 16) + 2, |
884 | 477ba620 | Aurelien Jarno | R_IA64_PCREL21B, label_index, 0);
|
885 | 477ba620 | Aurelien Jarno | } |
886 | 477ba620 | Aurelien Jarno | } |
887 | 477ba620 | Aurelien Jarno | |
888 | 477ba620 | Aurelien Jarno | static inline void tcg_out_call(TCGContext *s, TCGArg addr) |
889 | 477ba620 | Aurelien Jarno | { |
890 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
891 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr), |
892 | 477ba620 | Aurelien Jarno | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
|
893 | 477ba620 | Aurelien Jarno | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
894 | 477ba620 | Aurelien Jarno | TCG_REG_B6, TCG_REG_R2, 0));
|
895 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmB, |
896 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3), |
897 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
898 | 477ba620 | Aurelien Jarno | tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5, |
899 | 477ba620 | Aurelien Jarno | TCG_REG_B0, TCG_REG_B6)); |
900 | 477ba620 | Aurelien Jarno | } |
901 | 477ba620 | Aurelien Jarno | |
902 | 477ba620 | Aurelien Jarno | static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg) |
903 | 477ba620 | Aurelien Jarno | { |
904 | 477ba620 | Aurelien Jarno | int64_t disp; |
905 | 477ba620 | Aurelien Jarno | uint64_t imm; |
906 | 477ba620 | Aurelien Jarno | |
907 | 477ba620 | Aurelien Jarno | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg); |
908 | 477ba620 | Aurelien Jarno | |
909 | 477ba620 | Aurelien Jarno | disp = tb_ret_addr - s->code_ptr; |
910 | 477ba620 | Aurelien Jarno | imm = (uint64_t)disp >> 4;
|
911 | 477ba620 | Aurelien Jarno | |
912 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mLX, |
913 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
914 | 477ba620 | Aurelien Jarno | tcg_opc_l3 (imm), |
915 | 477ba620 | Aurelien Jarno | tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm)); |
916 | 477ba620 | Aurelien Jarno | } |
917 | 477ba620 | Aurelien Jarno | |
918 | 477ba620 | Aurelien Jarno | static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg) |
919 | 477ba620 | Aurelien Jarno | { |
920 | 477ba620 | Aurelien Jarno | if (s->tb_jmp_offset) {
|
921 | 477ba620 | Aurelien Jarno | /* direct jump method */
|
922 | 477ba620 | Aurelien Jarno | tcg_abort(); |
923 | 477ba620 | Aurelien Jarno | } else {
|
924 | 477ba620 | Aurelien Jarno | /* indirect jump method */
|
925 | 477ba620 | Aurelien Jarno | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, |
926 | 477ba620 | Aurelien Jarno | (tcg_target_long)(s->tb_next + arg)); |
927 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
928 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, |
929 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R2), |
930 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
931 | 477ba620 | Aurelien Jarno | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, |
932 | 477ba620 | Aurelien Jarno | TCG_REG_R2, 0));
|
933 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmB, |
934 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
935 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
936 | 477ba620 | Aurelien Jarno | tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, |
937 | 477ba620 | Aurelien Jarno | TCG_REG_B6)); |
938 | 477ba620 | Aurelien Jarno | } |
939 | 477ba620 | Aurelien Jarno | s->tb_next_offset[arg] = s->code_ptr - s->code_buf; |
940 | 477ba620 | Aurelien Jarno | } |
941 | 477ba620 | Aurelien Jarno | |
942 | 477ba620 | Aurelien Jarno | static inline void tcg_out_jmp(TCGContext *s, TCGArg addr) |
943 | 477ba620 | Aurelien Jarno | { |
944 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmI, |
945 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
946 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
947 | 477ba620 | Aurelien Jarno | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
|
948 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmB, |
949 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
950 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
951 | 477ba620 | Aurelien Jarno | tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
952 | 477ba620 | Aurelien Jarno | } |
953 | 477ba620 | Aurelien Jarno | |
954 | 477ba620 | Aurelien Jarno | static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, |
955 | 477ba620 | Aurelien Jarno | TCGArg arg1, tcg_target_long arg2) |
956 | 477ba620 | Aurelien Jarno | { |
957 | 477ba620 | Aurelien Jarno | if (arg2 == ((int16_t)arg2 >> 2) << 2) { |
958 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
959 | 477ba620 | Aurelien Jarno | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, |
960 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg2, arg1), |
961 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
962 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
963 | 477ba620 | Aurelien Jarno | } else {
|
964 | 477ba620 | Aurelien Jarno | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); |
965 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
966 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, |
967 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R2, arg1), |
968 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
969 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
970 | 477ba620 | Aurelien Jarno | } |
971 | 477ba620 | Aurelien Jarno | } |
972 | 477ba620 | Aurelien Jarno | |
973 | 477ba620 | Aurelien Jarno | static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, |
974 | 477ba620 | Aurelien Jarno | TCGArg arg1, tcg_target_long arg2) |
975 | 477ba620 | Aurelien Jarno | { |
976 | 477ba620 | Aurelien Jarno | if (arg2 == ((int16_t)arg2 >> 2) << 2) { |
977 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
978 | 477ba620 | Aurelien Jarno | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, |
979 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg2, arg1), |
980 | 477ba620 | Aurelien Jarno | tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
981 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
982 | 477ba620 | Aurelien Jarno | } else {
|
983 | 477ba620 | Aurelien Jarno | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); |
984 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
985 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, |
986 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R2, arg1), |
987 | 477ba620 | Aurelien Jarno | tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), |
988 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
989 | 477ba620 | Aurelien Jarno | } |
990 | 477ba620 | Aurelien Jarno | } |
991 | 477ba620 | Aurelien Jarno | |
992 | 477ba620 | Aurelien Jarno | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGArg arg, |
993 | 477ba620 | Aurelien Jarno | TCGArg arg1, tcg_target_long arg2) |
994 | 477ba620 | Aurelien Jarno | { |
995 | 477ba620 | Aurelien Jarno | if (type == TCG_TYPE_I32) {
|
996 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2); |
997 | 477ba620 | Aurelien Jarno | } else {
|
998 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2); |
999 | 477ba620 | Aurelien Jarno | } |
1000 | 477ba620 | Aurelien Jarno | } |
1001 | 477ba620 | Aurelien Jarno | |
1002 | 477ba620 | Aurelien Jarno | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGArg arg, |
1003 | 477ba620 | Aurelien Jarno | TCGArg arg1, tcg_target_long arg2) |
1004 | 477ba620 | Aurelien Jarno | { |
1005 | 477ba620 | Aurelien Jarno | if (type == TCG_TYPE_I32) {
|
1006 | 477ba620 | Aurelien Jarno | tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2); |
1007 | 477ba620 | Aurelien Jarno | } else {
|
1008 | 477ba620 | Aurelien Jarno | tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2); |
1009 | 477ba620 | Aurelien Jarno | } |
1010 | 477ba620 | Aurelien Jarno | } |
1011 | 477ba620 | Aurelien Jarno | |
1012 | 477ba620 | Aurelien Jarno | static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret, |
1013 | 477ba620 | Aurelien Jarno | TCGArg arg1, int const_arg1,
|
1014 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1015 | 477ba620 | Aurelien Jarno | { |
1016 | 477ba620 | Aurelien Jarno | uint64_t opc1, opc2; |
1017 | 477ba620 | Aurelien Jarno | |
1018 | 477ba620 | Aurelien Jarno | if (const_arg1 && arg1 != 0) { |
1019 | 477ba620 | Aurelien Jarno | opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
1020 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg1, TCG_REG_R0); |
1021 | 477ba620 | Aurelien Jarno | arg1 = TCG_REG_R2; |
1022 | 477ba620 | Aurelien Jarno | } else {
|
1023 | 477ba620 | Aurelien Jarno | opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
1024 | 477ba620 | Aurelien Jarno | } |
1025 | 477ba620 | Aurelien Jarno | |
1026 | 477ba620 | Aurelien Jarno | if (const_arg2 && arg2 != 0) { |
1027 | 477ba620 | Aurelien Jarno | opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, |
1028 | 477ba620 | Aurelien Jarno | TCG_REG_R3, arg2, TCG_REG_R0); |
1029 | 477ba620 | Aurelien Jarno | arg2 = TCG_REG_R3; |
1030 | 477ba620 | Aurelien Jarno | } else {
|
1031 | 477ba620 | Aurelien Jarno | opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
|
1032 | 477ba620 | Aurelien Jarno | } |
1033 | 477ba620 | Aurelien Jarno | |
1034 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1035 | 477ba620 | Aurelien Jarno | opc1, |
1036 | 477ba620 | Aurelien Jarno | opc2, |
1037 | 477ba620 | Aurelien Jarno | tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2)); |
1038 | 477ba620 | Aurelien Jarno | } |
1039 | 477ba620 | Aurelien Jarno | |
1040 | 477ba620 | Aurelien Jarno | static inline void tcg_out_eqv(TCGContext *s, TCGArg ret, |
1041 | 477ba620 | Aurelien Jarno | TCGArg arg1, int const_arg1,
|
1042 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1043 | 477ba620 | Aurelien Jarno | { |
1044 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1045 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1046 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2), |
1047 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
1048 | 477ba620 | Aurelien Jarno | } |
1049 | 477ba620 | Aurelien Jarno | |
1050 | 477ba620 | Aurelien Jarno | static inline void tcg_out_nand(TCGContext *s, TCGArg ret, |
1051 | 477ba620 | Aurelien Jarno | TCGArg arg1, int const_arg1,
|
1052 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1053 | 477ba620 | Aurelien Jarno | { |
1054 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1055 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1056 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2), |
1057 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
1058 | 477ba620 | Aurelien Jarno | } |
1059 | 477ba620 | Aurelien Jarno | |
1060 | 477ba620 | Aurelien Jarno | static inline void tcg_out_nor(TCGContext *s, TCGArg ret, |
1061 | 477ba620 | Aurelien Jarno | TCGArg arg1, int const_arg1,
|
1062 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1063 | 477ba620 | Aurelien Jarno | { |
1064 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1065 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1066 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2), |
1067 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
|
1068 | 477ba620 | Aurelien Jarno | } |
1069 | 477ba620 | Aurelien Jarno | |
1070 | 477ba620 | Aurelien Jarno | static inline void tcg_out_orc(TCGContext *s, TCGArg ret, |
1071 | 477ba620 | Aurelien Jarno | TCGArg arg1, int const_arg1,
|
1072 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1073 | 477ba620 | Aurelien Jarno | { |
1074 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1075 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1076 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
|
1077 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2)); |
1078 | 477ba620 | Aurelien Jarno | } |
1079 | 477ba620 | Aurelien Jarno | |
1080 | 477ba620 | Aurelien Jarno | static inline void tcg_out_mul(TCGContext *s, TCGArg ret, |
1081 | 477ba620 | Aurelien Jarno | TCGArg arg1, TCGArg arg2) |
1082 | 477ba620 | Aurelien Jarno | { |
1083 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmI, |
1084 | 477ba620 | Aurelien Jarno | tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1), |
1085 | 477ba620 | Aurelien Jarno | tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2), |
1086 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1087 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmF, |
1088 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1089 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1090 | 477ba620 | Aurelien Jarno | tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6, |
1091 | 477ba620 | Aurelien Jarno | TCG_REG_F7, TCG_REG_F0)); |
1092 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1093 | 477ba620 | Aurelien Jarno | tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6), |
1094 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1095 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1096 | 477ba620 | Aurelien Jarno | } |
1097 | 477ba620 | Aurelien Jarno | |
1098 | 477ba620 | Aurelien Jarno | static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1099 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1100 | 477ba620 | Aurelien Jarno | { |
1101 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1102 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1103 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1104 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1105 | 477ba620 | Aurelien Jarno | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
1106 | 477ba620 | Aurelien Jarno | ret, arg1, arg2, 31 - arg2));
|
1107 | 477ba620 | Aurelien Jarno | } else {
|
1108 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1109 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, |
1110 | 477ba620 | Aurelien Jarno | TCG_REG_R3, 0x1f, arg2),
|
1111 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1), |
1112 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, |
1113 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R3)); |
1114 | 477ba620 | Aurelien Jarno | } |
1115 | 477ba620 | Aurelien Jarno | } |
1116 | 477ba620 | Aurelien Jarno | |
1117 | 477ba620 | Aurelien Jarno | static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1118 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1119 | 477ba620 | Aurelien Jarno | { |
1120 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1121 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1122 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1123 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1124 | 477ba620 | Aurelien Jarno | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, |
1125 | 477ba620 | Aurelien Jarno | ret, arg1, arg2, 63 - arg2));
|
1126 | 477ba620 | Aurelien Jarno | } else {
|
1127 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1128 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1129 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1130 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2)); |
1131 | 477ba620 | Aurelien Jarno | } |
1132 | 477ba620 | Aurelien Jarno | } |
1133 | 477ba620 | Aurelien Jarno | |
1134 | 477ba620 | Aurelien Jarno | static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1135 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1136 | 477ba620 | Aurelien Jarno | { |
1137 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1138 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1139 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1140 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1141 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
1142 | 477ba620 | Aurelien Jarno | arg1, 63 - arg2, 31 - arg2)); |
1143 | 477ba620 | Aurelien Jarno | } else {
|
1144 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1145 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1146 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2, |
1147 | 477ba620 | Aurelien Jarno | 0x1f, arg2),
|
1148 | 477ba620 | Aurelien Jarno | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, |
1149 | 477ba620 | Aurelien Jarno | arg1, TCG_REG_R2)); |
1150 | 477ba620 | Aurelien Jarno | } |
1151 | 477ba620 | Aurelien Jarno | } |
1152 | 477ba620 | Aurelien Jarno | |
1153 | 477ba620 | Aurelien Jarno | static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1154 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1155 | 477ba620 | Aurelien Jarno | { |
1156 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1157 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1158 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1159 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1160 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, |
1161 | 477ba620 | Aurelien Jarno | arg1, 63 - arg2, 63 - arg2)); |
1162 | 477ba620 | Aurelien Jarno | } else {
|
1163 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1164 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1165 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1166 | 477ba620 | Aurelien Jarno | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, |
1167 | 477ba620 | Aurelien Jarno | arg1, arg2)); |
1168 | 477ba620 | Aurelien Jarno | } |
1169 | 477ba620 | Aurelien Jarno | } |
1170 | 477ba620 | Aurelien Jarno | |
1171 | 477ba620 | Aurelien Jarno | static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1172 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1173 | 477ba620 | Aurelien Jarno | { |
1174 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1175 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1176 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1177 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1178 | 477ba620 | Aurelien Jarno | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1179 | 477ba620 | Aurelien Jarno | arg1, arg2, 31 - arg2));
|
1180 | 477ba620 | Aurelien Jarno | } else {
|
1181 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1182 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
1183 | 477ba620 | Aurelien Jarno | 0x1f, arg2),
|
1184 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1), |
1185 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1186 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R3)); |
1187 | 477ba620 | Aurelien Jarno | } |
1188 | 477ba620 | Aurelien Jarno | } |
1189 | 477ba620 | Aurelien Jarno | |
1190 | 477ba620 | Aurelien Jarno | static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1191 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1192 | 477ba620 | Aurelien Jarno | { |
1193 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1194 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1195 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1196 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1197 | 477ba620 | Aurelien Jarno | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1198 | 477ba620 | Aurelien Jarno | arg1, arg2, 63 - arg2));
|
1199 | 477ba620 | Aurelien Jarno | } else {
|
1200 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1201 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1202 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1203 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1204 | 477ba620 | Aurelien Jarno | arg1, arg2)); |
1205 | 477ba620 | Aurelien Jarno | } |
1206 | 477ba620 | Aurelien Jarno | } |
1207 | 477ba620 | Aurelien Jarno | |
1208 | 477ba620 | Aurelien Jarno | static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1209 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1210 | 477ba620 | Aurelien Jarno | { |
1211 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1212 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1213 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1214 | 477ba620 | Aurelien Jarno | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1215 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg1, arg1), |
1216 | 477ba620 | Aurelien Jarno | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1217 | 477ba620 | Aurelien Jarno | TCG_REG_R2, 32 - arg2, 31)); |
1218 | 477ba620 | Aurelien Jarno | } else {
|
1219 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1220 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1221 | 477ba620 | Aurelien Jarno | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1222 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg1, arg1), |
1223 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
1224 | 477ba620 | Aurelien Jarno | 0x1f, arg2));
|
1225 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1226 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1227 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3, |
1228 | 477ba620 | Aurelien Jarno | 0x20, TCG_REG_R3),
|
1229 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1230 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R3)); |
1231 | 477ba620 | Aurelien Jarno | } |
1232 | 477ba620 | Aurelien Jarno | } |
1233 | 477ba620 | Aurelien Jarno | |
1234 | 477ba620 | Aurelien Jarno | static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1235 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1236 | 477ba620 | Aurelien Jarno | { |
1237 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1238 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1239 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1240 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1241 | 477ba620 | Aurelien Jarno | tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
1242 | 477ba620 | Aurelien Jarno | arg1, 0x40 - arg2));
|
1243 | 477ba620 | Aurelien Jarno | } else {
|
1244 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1245 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, |
1246 | 477ba620 | Aurelien Jarno | 0x40, arg2),
|
1247 | 477ba620 | Aurelien Jarno | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3, |
1248 | 477ba620 | Aurelien Jarno | arg1, arg2), |
1249 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2, |
1250 | 477ba620 | Aurelien Jarno | arg1, TCG_REG_R2)); |
1251 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1252 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1253 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1254 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
1255 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R3)); |
1256 | 477ba620 | Aurelien Jarno | } |
1257 | 477ba620 | Aurelien Jarno | } |
1258 | 477ba620 | Aurelien Jarno | |
1259 | 477ba620 | Aurelien Jarno | static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, |
1260 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1261 | 477ba620 | Aurelien Jarno | { |
1262 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1263 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1264 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1265 | 477ba620 | Aurelien Jarno | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1266 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg1, arg1), |
1267 | 477ba620 | Aurelien Jarno | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, |
1268 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg2, 31));
|
1269 | 477ba620 | Aurelien Jarno | } else {
|
1270 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1271 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, |
1272 | 477ba620 | Aurelien Jarno | 0x1f, arg2),
|
1273 | 477ba620 | Aurelien Jarno | tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, |
1274 | 477ba620 | Aurelien Jarno | TCG_REG_R2, arg1, arg1), |
1275 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, |
1276 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R3)); |
1277 | 477ba620 | Aurelien Jarno | } |
1278 | 477ba620 | Aurelien Jarno | } |
1279 | 477ba620 | Aurelien Jarno | |
1280 | 477ba620 | Aurelien Jarno | static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, |
1281 | 477ba620 | Aurelien Jarno | TCGArg arg2, int const_arg2)
|
1282 | 477ba620 | Aurelien Jarno | { |
1283 | 477ba620 | Aurelien Jarno | if (const_arg2) {
|
1284 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1285 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1286 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1287 | 477ba620 | Aurelien Jarno | tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, |
1288 | 477ba620 | Aurelien Jarno | arg1, arg2)); |
1289 | 477ba620 | Aurelien Jarno | } else {
|
1290 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1291 | 477ba620 | Aurelien Jarno | tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, |
1292 | 477ba620 | Aurelien Jarno | 0x40, arg2),
|
1293 | 477ba620 | Aurelien Jarno | tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3, |
1294 | 477ba620 | Aurelien Jarno | arg1, arg2), |
1295 | 477ba620 | Aurelien Jarno | tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2, |
1296 | 477ba620 | Aurelien Jarno | arg1, TCG_REG_R2)); |
1297 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1298 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1299 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1300 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, |
1301 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R3)); |
1302 | 477ba620 | Aurelien Jarno | } |
1303 | 477ba620 | Aurelien Jarno | } |
1304 | 477ba620 | Aurelien Jarno | |
1305 | 477ba620 | Aurelien Jarno | static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29, |
1306 | 477ba620 | Aurelien Jarno | TCGArg ret, TCGArg arg) |
1307 | 477ba620 | Aurelien Jarno | { |
1308 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1309 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1310 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1311 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg)); |
1312 | 477ba620 | Aurelien Jarno | } |
1313 | 477ba620 | Aurelien Jarno | |
1314 | 477ba620 | Aurelien Jarno | static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg) |
1315 | 477ba620 | Aurelien Jarno | { |
1316 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1317 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1318 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15), |
1319 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
1320 | 477ba620 | Aurelien Jarno | } |
1321 | 477ba620 | Aurelien Jarno | |
1322 | 477ba620 | Aurelien Jarno | static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg) |
1323 | 477ba620 | Aurelien Jarno | { |
1324 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1325 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1326 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31), |
1327 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
|
1328 | 477ba620 | Aurelien Jarno | } |
1329 | 477ba620 | Aurelien Jarno | |
1330 | 477ba620 | Aurelien Jarno | static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg) |
1331 | 477ba620 | Aurelien Jarno | { |
1332 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1333 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1334 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1335 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
|
1336 | 477ba620 | Aurelien Jarno | } |
1337 | 477ba620 | Aurelien Jarno | |
1338 | 477ba620 | Aurelien Jarno | static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1, |
1339 | 477ba620 | Aurelien Jarno | TCGArg arg2, int cmp4)
|
1340 | 477ba620 | Aurelien Jarno | { |
1341 | 477ba620 | Aurelien Jarno | uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6; |
1342 | 477ba620 | Aurelien Jarno | |
1343 | 477ba620 | Aurelien Jarno | if (cmp4) {
|
1344 | 477ba620 | Aurelien Jarno | opc_eq_a6 = OPC_CMP4_EQ_A6; |
1345 | 477ba620 | Aurelien Jarno | opc_lt_a6 = OPC_CMP4_LT_A6; |
1346 | 477ba620 | Aurelien Jarno | opc_ltu_a6 = OPC_CMP4_LTU_A6; |
1347 | 477ba620 | Aurelien Jarno | } else {
|
1348 | 477ba620 | Aurelien Jarno | opc_eq_a6 = OPC_CMP_EQ_A6; |
1349 | 477ba620 | Aurelien Jarno | opc_lt_a6 = OPC_CMP_LT_A6; |
1350 | 477ba620 | Aurelien Jarno | opc_ltu_a6 = OPC_CMP_LTU_A6; |
1351 | 477ba620 | Aurelien Jarno | } |
1352 | 477ba620 | Aurelien Jarno | |
1353 | 477ba620 | Aurelien Jarno | switch (cond) {
|
1354 | 477ba620 | Aurelien Jarno | case TCG_COND_EQ:
|
1355 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
1356 | 477ba620 | Aurelien Jarno | case TCG_COND_NE:
|
1357 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
1358 | 477ba620 | Aurelien Jarno | case TCG_COND_LT:
|
1359 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
1360 | 477ba620 | Aurelien Jarno | case TCG_COND_LTU:
|
1361 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
|
1362 | 477ba620 | Aurelien Jarno | case TCG_COND_GE:
|
1363 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
1364 | 477ba620 | Aurelien Jarno | case TCG_COND_GEU:
|
1365 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
|
1366 | 477ba620 | Aurelien Jarno | case TCG_COND_LE:
|
1367 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
1368 | 477ba620 | Aurelien Jarno | case TCG_COND_LEU:
|
1369 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
|
1370 | 477ba620 | Aurelien Jarno | case TCG_COND_GT:
|
1371 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
1372 | 477ba620 | Aurelien Jarno | case TCG_COND_GTU:
|
1373 | 477ba620 | Aurelien Jarno | return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
|
1374 | 477ba620 | Aurelien Jarno | default:
|
1375 | 477ba620 | Aurelien Jarno | tcg_abort(); |
1376 | 477ba620 | Aurelien Jarno | break;
|
1377 | 477ba620 | Aurelien Jarno | } |
1378 | 477ba620 | Aurelien Jarno | } |
1379 | 477ba620 | Aurelien Jarno | |
1380 | 477ba620 | Aurelien Jarno | static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1, |
1381 | 477ba620 | Aurelien Jarno | int const_arg1, TCGArg arg2, int const_arg2, |
1382 | 477ba620 | Aurelien Jarno | int label_index, int cmp4) |
1383 | 477ba620 | Aurelien Jarno | { |
1384 | 477ba620 | Aurelien Jarno | TCGLabel *l = &s->labels[label_index]; |
1385 | 477ba620 | Aurelien Jarno | uint64_t opc1, opc2; |
1386 | 477ba620 | Aurelien Jarno | |
1387 | 477ba620 | Aurelien Jarno | if (const_arg1 && arg1 != 0) { |
1388 | 477ba620 | Aurelien Jarno | opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, |
1389 | 477ba620 | Aurelien Jarno | arg1, TCG_REG_R0); |
1390 | 477ba620 | Aurelien Jarno | arg1 = TCG_REG_R2; |
1391 | 477ba620 | Aurelien Jarno | } else {
|
1392 | 477ba620 | Aurelien Jarno | opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
1393 | 477ba620 | Aurelien Jarno | } |
1394 | 477ba620 | Aurelien Jarno | |
1395 | 477ba620 | Aurelien Jarno | if (const_arg2 && arg2 != 0) { |
1396 | 477ba620 | Aurelien Jarno | opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3, |
1397 | 477ba620 | Aurelien Jarno | arg2, TCG_REG_R0); |
1398 | 477ba620 | Aurelien Jarno | arg2 = TCG_REG_R3; |
1399 | 477ba620 | Aurelien Jarno | } else {
|
1400 | 477ba620 | Aurelien Jarno | opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
|
1401 | 477ba620 | Aurelien Jarno | } |
1402 | 477ba620 | Aurelien Jarno | |
1403 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1404 | 477ba620 | Aurelien Jarno | opc1, |
1405 | 477ba620 | Aurelien Jarno | opc2, |
1406 | 477ba620 | Aurelien Jarno | tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4)); |
1407 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmB, |
1408 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1409 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1410 | 477ba620 | Aurelien Jarno | tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1, |
1411 | 477ba620 | Aurelien Jarno | get_reloc_pcrel21b(s->code_ptr + 2)));
|
1412 | 477ba620 | Aurelien Jarno | |
1413 | 477ba620 | Aurelien Jarno | if (l->has_value) {
|
1414 | 477ba620 | Aurelien Jarno | reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value); |
1415 | 477ba620 | Aurelien Jarno | } else {
|
1416 | 477ba620 | Aurelien Jarno | tcg_out_reloc(s, (s->code_ptr - 16) + 2, |
1417 | 477ba620 | Aurelien Jarno | R_IA64_PCREL21B, label_index, 0);
|
1418 | 477ba620 | Aurelien Jarno | } |
1419 | 477ba620 | Aurelien Jarno | } |
1420 | 477ba620 | Aurelien Jarno | |
1421 | 477ba620 | Aurelien Jarno | static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret, |
1422 | 477ba620 | Aurelien Jarno | TCGArg arg1, TCGArg arg2, int cmp4)
|
1423 | 477ba620 | Aurelien Jarno | { |
1424 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
1425 | 477ba620 | Aurelien Jarno | tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), |
1426 | 477ba620 | Aurelien Jarno | tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
|
1427 | 477ba620 | Aurelien Jarno | tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
|
1428 | 477ba620 | Aurelien Jarno | } |
1429 | 477ba620 | Aurelien Jarno | |
1430 | 477ba620 | Aurelien Jarno | #if defined(CONFIG_SOFTMMU)
|
1431 | 477ba620 | Aurelien Jarno | |
1432 | 477ba620 | Aurelien Jarno | #include "../../softmmu_defs.h" |
1433 | 477ba620 | Aurelien Jarno | |
1434 | 477ba620 | Aurelien Jarno | /* Load and compare a TLB entry, and return the result in (p6, p7).
|
1435 | 477ba620 | Aurelien Jarno | R2 is loaded with the address of the addend TLB entry.
|
1436 | 477ba620 | Aurelien Jarno | R56 is loaded with the address, zero extented on 32-bit targets. */
|
1437 | 477ba620 | Aurelien Jarno | static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg, |
1438 | 477ba620 | Aurelien Jarno | int s_bits, uint64_t offset_rw,
|
1439 | 477ba620 | Aurelien Jarno | uint64_t offset_addend) |
1440 | 477ba620 | Aurelien Jarno | { |
1441 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1442 | 477ba620 | Aurelien Jarno | tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3, |
1443 | 477ba620 | Aurelien Jarno | TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
1444 | 477ba620 | Aurelien Jarno | TCG_REG_R0), |
1445 | 477ba620 | Aurelien Jarno | tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2, |
1446 | 477ba620 | Aurelien Jarno | addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
|
1447 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2, |
1448 | 477ba620 | Aurelien Jarno | TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
|
1449 | 477ba620 | Aurelien Jarno | 63 - CPU_TLB_ENTRY_BITS));
|
1450 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1451 | 477ba620 | Aurelien Jarno | tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2, |
1452 | 477ba620 | Aurelien Jarno | offset_rw, TCG_REG_R2), |
1453 | 477ba620 | Aurelien Jarno | #if TARGET_LONG_BITS == 32 |
1454 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R56, addr_reg), |
1455 | 477ba620 | Aurelien Jarno | #else
|
1456 | 477ba620 | Aurelien Jarno | tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R56, |
1457 | 477ba620 | Aurelien Jarno | 0, addr_reg),
|
1458 | 477ba620 | Aurelien Jarno | #endif
|
1459 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1460 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_AREG0)); |
1461 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1462 | 477ba620 | Aurelien Jarno | tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R57, |
1463 | 477ba620 | Aurelien Jarno | TCG_REG_R2, offset_addend - offset_rw), |
1464 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3, |
1465 | 477ba620 | Aurelien Jarno | TCG_REG_R3, TCG_REG_R56), |
1466 | 477ba620 | Aurelien Jarno | tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6, |
1467 | 477ba620 | Aurelien Jarno | TCG_REG_P7, TCG_REG_R3, TCG_REG_R57)); |
1468 | 477ba620 | Aurelien Jarno | } |
1469 | 477ba620 | Aurelien Jarno | |
1470 | 477ba620 | Aurelien Jarno | static void *qemu_ld_helpers[4] = { |
1471 | 477ba620 | Aurelien Jarno | __ldb_mmu, |
1472 | 477ba620 | Aurelien Jarno | __ldw_mmu, |
1473 | 477ba620 | Aurelien Jarno | __ldl_mmu, |
1474 | 477ba620 | Aurelien Jarno | __ldq_mmu, |
1475 | 477ba620 | Aurelien Jarno | }; |
1476 | 477ba620 | Aurelien Jarno | |
1477 | 477ba620 | Aurelien Jarno | static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
1478 | 477ba620 | Aurelien Jarno | { |
1479 | 477ba620 | Aurelien Jarno | int addr_reg, data_reg, mem_index, s_bits, bswap;
|
1480 | 477ba620 | Aurelien Jarno | uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
|
1481 | 477ba620 | Aurelien Jarno | uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, |
1482 | 477ba620 | Aurelien Jarno | OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
|
1483 | 477ba620 | Aurelien Jarno | |
1484 | 477ba620 | Aurelien Jarno | data_reg = *args++; |
1485 | 477ba620 | Aurelien Jarno | addr_reg = *args++; |
1486 | 477ba620 | Aurelien Jarno | mem_index = *args; |
1487 | 477ba620 | Aurelien Jarno | s_bits = opc & 3;
|
1488 | 477ba620 | Aurelien Jarno | |
1489 | 477ba620 | Aurelien Jarno | #ifdef TARGET_WORDS_BIGENDIAN
|
1490 | 477ba620 | Aurelien Jarno | bswap = 1;
|
1491 | 477ba620 | Aurelien Jarno | #else
|
1492 | 477ba620 | Aurelien Jarno | bswap = 0;
|
1493 | 477ba620 | Aurelien Jarno | #endif
|
1494 | 477ba620 | Aurelien Jarno | |
1495 | 477ba620 | Aurelien Jarno | /* Read the TLB entry */
|
1496 | 477ba620 | Aurelien Jarno | tcg_out_qemu_tlb(s, addr_reg, s_bits, |
1497 | 477ba620 | Aurelien Jarno | offsetof(CPUState, tlb_table[mem_index][0].addr_read),
|
1498 | 477ba620 | Aurelien Jarno | offsetof(CPUState, tlb_table[mem_index][0].addend));
|
1499 | 477ba620 | Aurelien Jarno | |
1500 | 477ba620 | Aurelien Jarno | /* P6 is the fast path, and P7 the slow path */
|
1501 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mLX, |
1502 | 477ba620 | Aurelien Jarno | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R57, |
1503 | 477ba620 | Aurelien Jarno | mem_index, TCG_REG_R0), |
1504 | 477ba620 | Aurelien Jarno | tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]), |
1505 | 477ba620 | Aurelien Jarno | tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, |
1506 | 477ba620 | Aurelien Jarno | (tcg_target_long) qemu_ld_helpers[s_bits])); |
1507 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
1508 | 477ba620 | Aurelien Jarno | tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, |
1509 | 477ba620 | Aurelien Jarno | TCG_REG_R2, 8),
|
1510 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, |
1511 | 477ba620 | Aurelien Jarno | TCG_REG_R3, TCG_REG_R56), |
1512 | 477ba620 | Aurelien Jarno | tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
1513 | 477ba620 | Aurelien Jarno | TCG_REG_R3, 0));
|
1514 | 477ba620 | Aurelien Jarno | if (bswap && s_bits == 1) { |
1515 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
1516 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
1517 | 477ba620 | Aurelien Jarno | TCG_REG_R8, TCG_REG_R3), |
1518 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
1519 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1520 | 477ba620 | Aurelien Jarno | TCG_REG_R8, TCG_REG_R8, 15, 15)); |
1521 | 477ba620 | Aurelien Jarno | } else if (bswap && s_bits == 2) { |
1522 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
1523 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
1524 | 477ba620 | Aurelien Jarno | TCG_REG_R8, TCG_REG_R3), |
1525 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
1526 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1527 | 477ba620 | Aurelien Jarno | TCG_REG_R8, TCG_REG_R8, 31, 31)); |
1528 | 477ba620 | Aurelien Jarno | } else {
|
1529 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmI, |
1530 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], |
1531 | 477ba620 | Aurelien Jarno | TCG_REG_R8, TCG_REG_R3), |
1532 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), |
1533 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1534 | 477ba620 | Aurelien Jarno | } |
1535 | 477ba620 | Aurelien Jarno | if (!bswap || s_bits == 0) { |
1536 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miB, |
1537 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1538 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1539 | 477ba620 | Aurelien Jarno | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1540 | 477ba620 | Aurelien Jarno | TCG_REG_B0, TCG_REG_B6)); |
1541 | 477ba620 | Aurelien Jarno | } else {
|
1542 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miB, |
1543 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1544 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1545 | 477ba620 | Aurelien Jarno | TCG_REG_R8, TCG_REG_R8, 0xb),
|
1546 | 477ba620 | Aurelien Jarno | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1547 | 477ba620 | Aurelien Jarno | TCG_REG_B0, TCG_REG_B6)); |
1548 | 477ba620 | Aurelien Jarno | } |
1549 | 477ba620 | Aurelien Jarno | |
1550 | 477ba620 | Aurelien Jarno | if (opc == 3) { |
1551 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1552 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1553 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1554 | 477ba620 | Aurelien Jarno | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
1555 | 477ba620 | Aurelien Jarno | data_reg, 0, TCG_REG_R8));
|
1556 | 477ba620 | Aurelien Jarno | } else {
|
1557 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1558 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1559 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1560 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc], |
1561 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R8)); |
1562 | 477ba620 | Aurelien Jarno | } |
1563 | 477ba620 | Aurelien Jarno | } |
1564 | 477ba620 | Aurelien Jarno | |
1565 | 477ba620 | Aurelien Jarno | static void *qemu_st_helpers[4] = { |
1566 | 477ba620 | Aurelien Jarno | __stb_mmu, |
1567 | 477ba620 | Aurelien Jarno | __stw_mmu, |
1568 | 477ba620 | Aurelien Jarno | __stl_mmu, |
1569 | 477ba620 | Aurelien Jarno | __stq_mmu, |
1570 | 477ba620 | Aurelien Jarno | }; |
1571 | 477ba620 | Aurelien Jarno | |
1572 | 477ba620 | Aurelien Jarno | static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
1573 | 477ba620 | Aurelien Jarno | { |
1574 | 477ba620 | Aurelien Jarno | int addr_reg, data_reg, mem_index, bswap;
|
1575 | 477ba620 | Aurelien Jarno | uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
|
1576 | 477ba620 | Aurelien Jarno | |
1577 | 477ba620 | Aurelien Jarno | data_reg = *args++; |
1578 | 477ba620 | Aurelien Jarno | addr_reg = *args++; |
1579 | 477ba620 | Aurelien Jarno | mem_index = *args; |
1580 | 477ba620 | Aurelien Jarno | |
1581 | 477ba620 | Aurelien Jarno | #ifdef TARGET_WORDS_BIGENDIAN
|
1582 | 477ba620 | Aurelien Jarno | bswap = 1;
|
1583 | 477ba620 | Aurelien Jarno | #else
|
1584 | 477ba620 | Aurelien Jarno | bswap = 0;
|
1585 | 477ba620 | Aurelien Jarno | #endif
|
1586 | 477ba620 | Aurelien Jarno | |
1587 | 477ba620 | Aurelien Jarno | tcg_out_qemu_tlb(s, addr_reg, opc, |
1588 | 477ba620 | Aurelien Jarno | offsetof(CPUState, tlb_table[mem_index][0].addr_write),
|
1589 | 477ba620 | Aurelien Jarno | offsetof(CPUState, tlb_table[mem_index][0].addend));
|
1590 | 477ba620 | Aurelien Jarno | |
1591 | 477ba620 | Aurelien Jarno | /* P6 is the fast path, and P7 the slow path */
|
1592 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mLX, |
1593 | 477ba620 | Aurelien Jarno | tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R57, |
1594 | 477ba620 | Aurelien Jarno | 0, data_reg),
|
1595 | 477ba620 | Aurelien Jarno | tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]), |
1596 | 477ba620 | Aurelien Jarno | tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, |
1597 | 477ba620 | Aurelien Jarno | (tcg_target_long) qemu_st_helpers[opc])); |
1598 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, MmI, |
1599 | 477ba620 | Aurelien Jarno | tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, |
1600 | 477ba620 | Aurelien Jarno | TCG_REG_R2, 8),
|
1601 | 477ba620 | Aurelien Jarno | tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3, |
1602 | 477ba620 | Aurelien Jarno | TCG_REG_R3, TCG_REG_R56), |
1603 | 477ba620 | Aurelien Jarno | tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, |
1604 | 477ba620 | Aurelien Jarno | TCG_REG_R3, 0));
|
1605 | 477ba620 | Aurelien Jarno | |
1606 | 477ba620 | Aurelien Jarno | if (!bswap || opc == 0) { |
1607 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1608 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1609 | 477ba620 | Aurelien Jarno | TCG_REG_R1, TCG_REG_R2), |
1610 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1611 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1612 | 477ba620 | Aurelien Jarno | } else if (opc == 1) { |
1613 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1614 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1615 | 477ba620 | Aurelien Jarno | TCG_REG_R1, TCG_REG_R2), |
1616 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1617 | 477ba620 | Aurelien Jarno | TCG_REG_R2, data_reg, 15, 15), |
1618 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1619 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R2, 0xb));
|
1620 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R2; |
1621 | 477ba620 | Aurelien Jarno | } else if (opc == 2) { |
1622 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1623 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1624 | 477ba620 | Aurelien Jarno | TCG_REG_R1, TCG_REG_R2), |
1625 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, |
1626 | 477ba620 | Aurelien Jarno | TCG_REG_R2, data_reg, 31, 31), |
1627 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1628 | 477ba620 | Aurelien Jarno | TCG_REG_R2, TCG_REG_R2, 0xb));
|
1629 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R2; |
1630 | 477ba620 | Aurelien Jarno | } else if (opc == 3) { |
1631 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1632 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, |
1633 | 477ba620 | Aurelien Jarno | TCG_REG_R1, TCG_REG_R2), |
1634 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1635 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, |
1636 | 477ba620 | Aurelien Jarno | TCG_REG_R2, data_reg, 0xb));
|
1637 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R2; |
1638 | 477ba620 | Aurelien Jarno | } |
1639 | 477ba620 | Aurelien Jarno | |
1640 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miB, |
1641 | 477ba620 | Aurelien Jarno | tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc], |
1642 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R3), |
1643 | 477ba620 | Aurelien Jarno | tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, |
1644 | 477ba620 | Aurelien Jarno | mem_index, TCG_REG_R0), |
1645 | 477ba620 | Aurelien Jarno | tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5, |
1646 | 477ba620 | Aurelien Jarno | TCG_REG_B0, TCG_REG_B6)); |
1647 | 477ba620 | Aurelien Jarno | } |
1648 | 477ba620 | Aurelien Jarno | |
1649 | 477ba620 | Aurelien Jarno | #else /* !CONFIG_SOFTMMU */ |
1650 | 477ba620 | Aurelien Jarno | |
1651 | 477ba620 | Aurelien Jarno | static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) |
1652 | 477ba620 | Aurelien Jarno | { |
1653 | 6781d08d | Richard Henderson | static uint64_t const opc_ld_m1[4] = { |
1654 | 6781d08d | Richard Henderson | OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 |
1655 | 6781d08d | Richard Henderson | }; |
1656 | 6781d08d | Richard Henderson | static uint64_t const opc_sxt_i29[4] = { |
1657 | 6781d08d | Richard Henderson | OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
|
1658 | 6781d08d | Richard Henderson | }; |
1659 | 477ba620 | Aurelien Jarno | int addr_reg, data_reg, mem_index, s_bits, bswap;
|
1660 | 477ba620 | Aurelien Jarno | |
1661 | 477ba620 | Aurelien Jarno | data_reg = *args++; |
1662 | 477ba620 | Aurelien Jarno | addr_reg = *args++; |
1663 | 477ba620 | Aurelien Jarno | mem_index = *args; |
1664 | 477ba620 | Aurelien Jarno | s_bits = opc & 3;
|
1665 | 477ba620 | Aurelien Jarno | |
1666 | 477ba620 | Aurelien Jarno | #ifdef TARGET_WORDS_BIGENDIAN
|
1667 | 477ba620 | Aurelien Jarno | bswap = 1;
|
1668 | 477ba620 | Aurelien Jarno | #else
|
1669 | 477ba620 | Aurelien Jarno | bswap = 0;
|
1670 | 477ba620 | Aurelien Jarno | #endif
|
1671 | 477ba620 | Aurelien Jarno | |
1672 | 477ba620 | Aurelien Jarno | #if TARGET_LONG_BITS == 32 |
1673 | 6781d08d | Richard Henderson | if (GUEST_BASE != 0) { |
1674 | 6781d08d | Richard Henderson | tcg_out_bundle(s, mII, |
1675 | 6781d08d | Richard Henderson | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1676 | 6781d08d | Richard Henderson | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1677 | 6781d08d | Richard Henderson | TCG_REG_R3, addr_reg), |
1678 | 6781d08d | Richard Henderson | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1679 | 6781d08d | Richard Henderson | TCG_GUEST_BASE_REG, TCG_REG_R3)); |
1680 | 6781d08d | Richard Henderson | } else {
|
1681 | 6781d08d | Richard Henderson | tcg_out_bundle(s, miI, |
1682 | 6781d08d | Richard Henderson | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1683 | 6781d08d | Richard Henderson | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1684 | 6781d08d | Richard Henderson | TCG_REG_R2, addr_reg), |
1685 | 6781d08d | Richard Henderson | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1686 | 6781d08d | Richard Henderson | } |
1687 | 477ba620 | Aurelien Jarno | |
1688 | 477ba620 | Aurelien Jarno | if (!bswap || s_bits == 0) { |
1689 | 477ba620 | Aurelien Jarno | if (s_bits == opc) {
|
1690 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1691 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1692 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R2), |
1693 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1694 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1695 | 477ba620 | Aurelien Jarno | } else {
|
1696 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1697 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1698 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R2), |
1699 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1700 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1701 | 477ba620 | Aurelien Jarno | data_reg, data_reg)); |
1702 | 477ba620 | Aurelien Jarno | } |
1703 | 477ba620 | Aurelien Jarno | } else if (s_bits == 3) { |
1704 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1705 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1706 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R2), |
1707 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1708 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1709 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 0xb));
|
1710 | 477ba620 | Aurelien Jarno | } else {
|
1711 | 477ba620 | Aurelien Jarno | if (s_bits == 1) { |
1712 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1713 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1714 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R2), |
1715 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1716 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1717 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 15, 15)); |
1718 | 477ba620 | Aurelien Jarno | } else {
|
1719 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1720 | 477ba620 | Aurelien Jarno | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1721 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R2), |
1722 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1723 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1724 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 31, 31)); |
1725 | 477ba620 | Aurelien Jarno | } |
1726 | 477ba620 | Aurelien Jarno | if (opc == s_bits) {
|
1727 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1728 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1729 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1730 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1731 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 0xb));
|
1732 | 477ba620 | Aurelien Jarno | } else {
|
1733 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1734 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1735 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1736 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 0xb),
|
1737 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1738 | 477ba620 | Aurelien Jarno | data_reg, data_reg)); |
1739 | 477ba620 | Aurelien Jarno | } |
1740 | 477ba620 | Aurelien Jarno | } |
1741 | 477ba620 | Aurelien Jarno | #else
|
1742 | 6781d08d | Richard Henderson | if (GUEST_BASE != 0) { |
1743 | 6781d08d | Richard Henderson | tcg_out_bundle(s, MmI, |
1744 | 6781d08d | Richard Henderson | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1745 | 6781d08d | Richard Henderson | TCG_GUEST_BASE_REG, addr_reg), |
1746 | 6781d08d | Richard Henderson | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1747 | 6781d08d | Richard Henderson | data_reg, TCG_REG_R2), |
1748 | 6781d08d | Richard Henderson | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1749 | 6781d08d | Richard Henderson | } else {
|
1750 | 6781d08d | Richard Henderson | tcg_out_bundle(s, mmI, |
1751 | 6781d08d | Richard Henderson | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1752 | 6781d08d | Richard Henderson | tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], |
1753 | 6781d08d | Richard Henderson | data_reg, addr_reg), |
1754 | 6781d08d | Richard Henderson | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1755 | 6781d08d | Richard Henderson | } |
1756 | 477ba620 | Aurelien Jarno | |
1757 | 477ba620 | Aurelien Jarno | if (bswap && s_bits == 1) { |
1758 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1759 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1760 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1761 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 15, 15), |
1762 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1763 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 0xb));
|
1764 | 477ba620 | Aurelien Jarno | } else if (bswap && s_bits == 2) { |
1765 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1766 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1767 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1768 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 31, 31), |
1769 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1770 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 0xb));
|
1771 | 477ba620 | Aurelien Jarno | } else if (bswap && s_bits == 3) { |
1772 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1773 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1774 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1775 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1776 | 477ba620 | Aurelien Jarno | data_reg, data_reg, 0xb));
|
1777 | 477ba620 | Aurelien Jarno | } |
1778 | 477ba620 | Aurelien Jarno | if (s_bits != opc) {
|
1779 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1780 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1781 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1782 | 477ba620 | Aurelien Jarno | tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], |
1783 | 477ba620 | Aurelien Jarno | data_reg, data_reg)); |
1784 | 477ba620 | Aurelien Jarno | } |
1785 | 477ba620 | Aurelien Jarno | #endif
|
1786 | 477ba620 | Aurelien Jarno | } |
1787 | 477ba620 | Aurelien Jarno | |
1788 | 477ba620 | Aurelien Jarno | static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) |
1789 | 477ba620 | Aurelien Jarno | { |
1790 | 6781d08d | Richard Henderson | static uint64_t const opc_st_m4[4] = { |
1791 | 6781d08d | Richard Henderson | OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 |
1792 | 6781d08d | Richard Henderson | }; |
1793 | 477ba620 | Aurelien Jarno | int addr_reg, data_reg, bswap;
|
1794 | 6781d08d | Richard Henderson | #if TARGET_LONG_BITS == 64 |
1795 | 6781d08d | Richard Henderson | uint64_t add_guest_base; |
1796 | 6781d08d | Richard Henderson | #endif
|
1797 | 477ba620 | Aurelien Jarno | |
1798 | 477ba620 | Aurelien Jarno | data_reg = *args++; |
1799 | 477ba620 | Aurelien Jarno | addr_reg = *args++; |
1800 | 477ba620 | Aurelien Jarno | |
1801 | 477ba620 | Aurelien Jarno | #ifdef TARGET_WORDS_BIGENDIAN
|
1802 | 477ba620 | Aurelien Jarno | bswap = 1;
|
1803 | 477ba620 | Aurelien Jarno | #else
|
1804 | 477ba620 | Aurelien Jarno | bswap = 0;
|
1805 | 477ba620 | Aurelien Jarno | #endif
|
1806 | 477ba620 | Aurelien Jarno | |
1807 | 477ba620 | Aurelien Jarno | #if TARGET_LONG_BITS == 32 |
1808 | 6781d08d | Richard Henderson | if (GUEST_BASE != 0) { |
1809 | 6781d08d | Richard Henderson | tcg_out_bundle(s, mII, |
1810 | 6781d08d | Richard Henderson | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1811 | 6781d08d | Richard Henderson | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1812 | 6781d08d | Richard Henderson | TCG_REG_R3, addr_reg), |
1813 | 6781d08d | Richard Henderson | tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1814 | 6781d08d | Richard Henderson | TCG_GUEST_BASE_REG, TCG_REG_R3)); |
1815 | 6781d08d | Richard Henderson | } else {
|
1816 | 6781d08d | Richard Henderson | tcg_out_bundle(s, miI, |
1817 | 6781d08d | Richard Henderson | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1818 | 6781d08d | Richard Henderson | tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, |
1819 | 6781d08d | Richard Henderson | TCG_REG_R3, addr_reg), |
1820 | 6781d08d | Richard Henderson | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1821 | 6781d08d | Richard Henderson | } |
1822 | 6781d08d | Richard Henderson | |
1823 | 477ba620 | Aurelien Jarno | if (bswap) {
|
1824 | 477ba620 | Aurelien Jarno | if (opc == 1) { |
1825 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1826 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1827 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1828 | 477ba620 | Aurelien Jarno | TCG_REG_R3, data_reg, 15, 15), |
1829 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1830 | 477ba620 | Aurelien Jarno | TCG_REG_R3, TCG_REG_R3, 0xb));
|
1831 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R3; |
1832 | 477ba620 | Aurelien Jarno | } else if (opc == 2) { |
1833 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1834 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1835 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1836 | 477ba620 | Aurelien Jarno | TCG_REG_R3, data_reg, 31, 31), |
1837 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1838 | 477ba620 | Aurelien Jarno | TCG_REG_R3, TCG_REG_R3, 0xb));
|
1839 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R3; |
1840 | 477ba620 | Aurelien Jarno | } else if (opc == 3) { |
1841 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1842 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1843 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1844 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1845 | 477ba620 | Aurelien Jarno | TCG_REG_R3, data_reg, 0xb));
|
1846 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R3; |
1847 | 477ba620 | Aurelien Jarno | } |
1848 | 477ba620 | Aurelien Jarno | } |
1849 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mmI, |
1850 | 477ba620 | Aurelien Jarno | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
1851 | 477ba620 | Aurelien Jarno | data_reg, TCG_REG_R2), |
1852 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
1853 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1854 | 477ba620 | Aurelien Jarno | #else
|
1855 | 6781d08d | Richard Henderson | if (GUEST_BASE != 0) { |
1856 | 6781d08d | Richard Henderson | add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, |
1857 | 6781d08d | Richard Henderson | TCG_GUEST_BASE_REG, addr_reg); |
1858 | 6781d08d | Richard Henderson | addr_reg = TCG_REG_R2; |
1859 | 6781d08d | Richard Henderson | } else {
|
1860 | 6781d08d | Richard Henderson | add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
|
1861 | 6781d08d | Richard Henderson | } |
1862 | 6781d08d | Richard Henderson | |
1863 | 477ba620 | Aurelien Jarno | if (!bswap || opc == 0) { |
1864 | 6781d08d | Richard Henderson | tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI), |
1865 | 6781d08d | Richard Henderson | add_guest_base, |
1866 | 477ba620 | Aurelien Jarno | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
1867 | 6781d08d | Richard Henderson | data_reg, addr_reg), |
1868 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1869 | 477ba620 | Aurelien Jarno | } else {
|
1870 | 477ba620 | Aurelien Jarno | if (opc == 1) { |
1871 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1872 | 6781d08d | Richard Henderson | add_guest_base, |
1873 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1874 | 477ba620 | Aurelien Jarno | TCG_REG_R3, data_reg, 15, 15), |
1875 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1876 | 477ba620 | Aurelien Jarno | TCG_REG_R3, TCG_REG_R3, 0xb));
|
1877 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R3; |
1878 | 477ba620 | Aurelien Jarno | } else if (opc == 2) { |
1879 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
1880 | 6781d08d | Richard Henderson | add_guest_base, |
1881 | 477ba620 | Aurelien Jarno | tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, |
1882 | 477ba620 | Aurelien Jarno | TCG_REG_R3, data_reg, 31, 31), |
1883 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1884 | 477ba620 | Aurelien Jarno | TCG_REG_R3, TCG_REG_R3, 0xb));
|
1885 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R3; |
1886 | 477ba620 | Aurelien Jarno | } else if (opc == 3) { |
1887 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1888 | 6781d08d | Richard Henderson | add_guest_base, |
1889 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1890 | 477ba620 | Aurelien Jarno | tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, |
1891 | 477ba620 | Aurelien Jarno | TCG_REG_R3, data_reg, 0xb));
|
1892 | 477ba620 | Aurelien Jarno | data_reg = TCG_REG_R3; |
1893 | 477ba620 | Aurelien Jarno | } |
1894 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
1895 | 477ba620 | Aurelien Jarno | tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], |
1896 | 6781d08d | Richard Henderson | data_reg, addr_reg), |
1897 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
|
1898 | 477ba620 | Aurelien Jarno | tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
1899 | 477ba620 | Aurelien Jarno | } |
1900 | 477ba620 | Aurelien Jarno | #endif
|
1901 | 477ba620 | Aurelien Jarno | } |
1902 | 477ba620 | Aurelien Jarno | |
1903 | 477ba620 | Aurelien Jarno | #endif
|
1904 | 477ba620 | Aurelien Jarno | |
1905 | 477ba620 | Aurelien Jarno | static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, |
1906 | 477ba620 | Aurelien Jarno | const TCGArg *args, const int *const_args) |
1907 | 477ba620 | Aurelien Jarno | { |
1908 | 477ba620 | Aurelien Jarno | switch(opc) {
|
1909 | 477ba620 | Aurelien Jarno | case INDEX_op_exit_tb:
|
1910 | 477ba620 | Aurelien Jarno | tcg_out_exit_tb(s, args[0]);
|
1911 | 477ba620 | Aurelien Jarno | break;
|
1912 | 477ba620 | Aurelien Jarno | case INDEX_op_br:
|
1913 | 477ba620 | Aurelien Jarno | tcg_out_br(s, args[0]);
|
1914 | 477ba620 | Aurelien Jarno | break;
|
1915 | 477ba620 | Aurelien Jarno | case INDEX_op_call:
|
1916 | 477ba620 | Aurelien Jarno | tcg_out_call(s, args[0]);
|
1917 | 477ba620 | Aurelien Jarno | break;
|
1918 | 477ba620 | Aurelien Jarno | case INDEX_op_goto_tb:
|
1919 | 477ba620 | Aurelien Jarno | tcg_out_goto_tb(s, args[0]);
|
1920 | 477ba620 | Aurelien Jarno | break;
|
1921 | 477ba620 | Aurelien Jarno | case INDEX_op_jmp:
|
1922 | 477ba620 | Aurelien Jarno | tcg_out_jmp(s, args[0]);
|
1923 | 477ba620 | Aurelien Jarno | break;
|
1924 | 477ba620 | Aurelien Jarno | |
1925 | 477ba620 | Aurelien Jarno | case INDEX_op_movi_i32:
|
1926 | 477ba620 | Aurelien Jarno | tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); |
1927 | 477ba620 | Aurelien Jarno | break;
|
1928 | 477ba620 | Aurelien Jarno | case INDEX_op_movi_i64:
|
1929 | 477ba620 | Aurelien Jarno | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
1930 | 477ba620 | Aurelien Jarno | break;
|
1931 | 477ba620 | Aurelien Jarno | |
1932 | 477ba620 | Aurelien Jarno | case INDEX_op_ld8u_i32:
|
1933 | 477ba620 | Aurelien Jarno | case INDEX_op_ld8u_i64:
|
1934 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); |
1935 | 477ba620 | Aurelien Jarno | break;
|
1936 | 477ba620 | Aurelien Jarno | case INDEX_op_ld8s_i32:
|
1937 | 477ba620 | Aurelien Jarno | case INDEX_op_ld8s_i64:
|
1938 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); |
1939 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]); |
1940 | 477ba620 | Aurelien Jarno | break;
|
1941 | 477ba620 | Aurelien Jarno | case INDEX_op_ld16u_i32:
|
1942 | 477ba620 | Aurelien Jarno | case INDEX_op_ld16u_i64:
|
1943 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); |
1944 | 477ba620 | Aurelien Jarno | break;
|
1945 | 477ba620 | Aurelien Jarno | case INDEX_op_ld16s_i32:
|
1946 | 477ba620 | Aurelien Jarno | case INDEX_op_ld16s_i64:
|
1947 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); |
1948 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]); |
1949 | 477ba620 | Aurelien Jarno | break;
|
1950 | 477ba620 | Aurelien Jarno | case INDEX_op_ld_i32:
|
1951 | 477ba620 | Aurelien Jarno | case INDEX_op_ld32u_i64:
|
1952 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); |
1953 | 477ba620 | Aurelien Jarno | break;
|
1954 | 477ba620 | Aurelien Jarno | case INDEX_op_ld32s_i64:
|
1955 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); |
1956 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]); |
1957 | 477ba620 | Aurelien Jarno | break;
|
1958 | 477ba620 | Aurelien Jarno | case INDEX_op_ld_i64:
|
1959 | 477ba620 | Aurelien Jarno | tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]); |
1960 | 477ba620 | Aurelien Jarno | break;
|
1961 | 477ba620 | Aurelien Jarno | case INDEX_op_st8_i32:
|
1962 | 477ba620 | Aurelien Jarno | case INDEX_op_st8_i64:
|
1963 | 477ba620 | Aurelien Jarno | tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]); |
1964 | 477ba620 | Aurelien Jarno | break;
|
1965 | 477ba620 | Aurelien Jarno | case INDEX_op_st16_i32:
|
1966 | 477ba620 | Aurelien Jarno | case INDEX_op_st16_i64:
|
1967 | 477ba620 | Aurelien Jarno | tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]); |
1968 | 477ba620 | Aurelien Jarno | break;
|
1969 | 477ba620 | Aurelien Jarno | case INDEX_op_st_i32:
|
1970 | 477ba620 | Aurelien Jarno | case INDEX_op_st32_i64:
|
1971 | 477ba620 | Aurelien Jarno | tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]); |
1972 | 477ba620 | Aurelien Jarno | break;
|
1973 | 477ba620 | Aurelien Jarno | case INDEX_op_st_i64:
|
1974 | 477ba620 | Aurelien Jarno | tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]); |
1975 | 477ba620 | Aurelien Jarno | break;
|
1976 | 477ba620 | Aurelien Jarno | |
1977 | 477ba620 | Aurelien Jarno | case INDEX_op_add_i32:
|
1978 | 477ba620 | Aurelien Jarno | case INDEX_op_add_i64:
|
1979 | 477ba620 | Aurelien Jarno | tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1], |
1980 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
1981 | 477ba620 | Aurelien Jarno | break;
|
1982 | 477ba620 | Aurelien Jarno | case INDEX_op_sub_i32:
|
1983 | 477ba620 | Aurelien Jarno | case INDEX_op_sub_i64:
|
1984 | 477ba620 | Aurelien Jarno | tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1], |
1985 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
1986 | 477ba620 | Aurelien Jarno | break;
|
1987 | 477ba620 | Aurelien Jarno | |
1988 | 477ba620 | Aurelien Jarno | case INDEX_op_and_i32:
|
1989 | 477ba620 | Aurelien Jarno | case INDEX_op_and_i64:
|
1990 | 477ba620 | Aurelien Jarno | tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1], |
1991 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
1992 | 477ba620 | Aurelien Jarno | break;
|
1993 | 477ba620 | Aurelien Jarno | case INDEX_op_andc_i32:
|
1994 | 477ba620 | Aurelien Jarno | case INDEX_op_andc_i64:
|
1995 | 477ba620 | Aurelien Jarno | tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1], |
1996 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
1997 | 477ba620 | Aurelien Jarno | break;
|
1998 | 477ba620 | Aurelien Jarno | case INDEX_op_eqv_i32:
|
1999 | 477ba620 | Aurelien Jarno | case INDEX_op_eqv_i64:
|
2000 | 477ba620 | Aurelien Jarno | tcg_out_eqv(s, args[0], args[1], const_args[1], |
2001 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
2002 | 477ba620 | Aurelien Jarno | break;
|
2003 | 477ba620 | Aurelien Jarno | case INDEX_op_nand_i32:
|
2004 | 477ba620 | Aurelien Jarno | case INDEX_op_nand_i64:
|
2005 | 477ba620 | Aurelien Jarno | tcg_out_nand(s, args[0], args[1], const_args[1], |
2006 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
2007 | 477ba620 | Aurelien Jarno | break;
|
2008 | 477ba620 | Aurelien Jarno | case INDEX_op_nor_i32:
|
2009 | 477ba620 | Aurelien Jarno | case INDEX_op_nor_i64:
|
2010 | 477ba620 | Aurelien Jarno | tcg_out_nor(s, args[0], args[1], const_args[1], |
2011 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
2012 | 477ba620 | Aurelien Jarno | break;
|
2013 | 477ba620 | Aurelien Jarno | case INDEX_op_or_i32:
|
2014 | 477ba620 | Aurelien Jarno | case INDEX_op_or_i64:
|
2015 | 477ba620 | Aurelien Jarno | tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1], |
2016 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
2017 | 477ba620 | Aurelien Jarno | break;
|
2018 | 477ba620 | Aurelien Jarno | case INDEX_op_orc_i32:
|
2019 | 477ba620 | Aurelien Jarno | case INDEX_op_orc_i64:
|
2020 | 477ba620 | Aurelien Jarno | tcg_out_orc(s, args[0], args[1], const_args[1], |
2021 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
2022 | 477ba620 | Aurelien Jarno | break;
|
2023 | 477ba620 | Aurelien Jarno | case INDEX_op_xor_i32:
|
2024 | 477ba620 | Aurelien Jarno | case INDEX_op_xor_i64:
|
2025 | 477ba620 | Aurelien Jarno | tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1], |
2026 | 477ba620 | Aurelien Jarno | args[2], const_args[2]); |
2027 | 477ba620 | Aurelien Jarno | break;
|
2028 | 477ba620 | Aurelien Jarno | |
2029 | 477ba620 | Aurelien Jarno | case INDEX_op_mul_i32:
|
2030 | 477ba620 | Aurelien Jarno | case INDEX_op_mul_i64:
|
2031 | 477ba620 | Aurelien Jarno | tcg_out_mul(s, args[0], args[1], args[2]); |
2032 | 477ba620 | Aurelien Jarno | break;
|
2033 | 477ba620 | Aurelien Jarno | |
2034 | 477ba620 | Aurelien Jarno | case INDEX_op_sar_i32:
|
2035 | 477ba620 | Aurelien Jarno | tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]); |
2036 | 477ba620 | Aurelien Jarno | break;
|
2037 | 477ba620 | Aurelien Jarno | case INDEX_op_sar_i64:
|
2038 | 477ba620 | Aurelien Jarno | tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]); |
2039 | 477ba620 | Aurelien Jarno | break;
|
2040 | 477ba620 | Aurelien Jarno | case INDEX_op_shl_i32:
|
2041 | 477ba620 | Aurelien Jarno | tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]); |
2042 | 477ba620 | Aurelien Jarno | break;
|
2043 | 477ba620 | Aurelien Jarno | case INDEX_op_shl_i64:
|
2044 | 477ba620 | Aurelien Jarno | tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]); |
2045 | 477ba620 | Aurelien Jarno | break;
|
2046 | 477ba620 | Aurelien Jarno | case INDEX_op_shr_i32:
|
2047 | 477ba620 | Aurelien Jarno | tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]); |
2048 | 477ba620 | Aurelien Jarno | break;
|
2049 | 477ba620 | Aurelien Jarno | case INDEX_op_shr_i64:
|
2050 | 477ba620 | Aurelien Jarno | tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]); |
2051 | 477ba620 | Aurelien Jarno | break;
|
2052 | 477ba620 | Aurelien Jarno | case INDEX_op_rotl_i32:
|
2053 | 477ba620 | Aurelien Jarno | tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]); |
2054 | 477ba620 | Aurelien Jarno | break;
|
2055 | 477ba620 | Aurelien Jarno | case INDEX_op_rotl_i64:
|
2056 | 477ba620 | Aurelien Jarno | tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]); |
2057 | 477ba620 | Aurelien Jarno | break;
|
2058 | 477ba620 | Aurelien Jarno | case INDEX_op_rotr_i32:
|
2059 | 477ba620 | Aurelien Jarno | tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]); |
2060 | 477ba620 | Aurelien Jarno | break;
|
2061 | 477ba620 | Aurelien Jarno | case INDEX_op_rotr_i64:
|
2062 | 477ba620 | Aurelien Jarno | tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]); |
2063 | 477ba620 | Aurelien Jarno | break;
|
2064 | 477ba620 | Aurelien Jarno | |
2065 | 477ba620 | Aurelien Jarno | case INDEX_op_ext8s_i32:
|
2066 | 477ba620 | Aurelien Jarno | case INDEX_op_ext8s_i64:
|
2067 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]); |
2068 | 477ba620 | Aurelien Jarno | break;
|
2069 | 477ba620 | Aurelien Jarno | case INDEX_op_ext8u_i32:
|
2070 | 477ba620 | Aurelien Jarno | case INDEX_op_ext8u_i64:
|
2071 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]); |
2072 | 477ba620 | Aurelien Jarno | break;
|
2073 | 477ba620 | Aurelien Jarno | case INDEX_op_ext16s_i32:
|
2074 | 477ba620 | Aurelien Jarno | case INDEX_op_ext16s_i64:
|
2075 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]); |
2076 | 477ba620 | Aurelien Jarno | break;
|
2077 | 477ba620 | Aurelien Jarno | case INDEX_op_ext16u_i32:
|
2078 | 477ba620 | Aurelien Jarno | case INDEX_op_ext16u_i64:
|
2079 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]); |
2080 | 477ba620 | Aurelien Jarno | break;
|
2081 | 477ba620 | Aurelien Jarno | case INDEX_op_ext32s_i64:
|
2082 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]); |
2083 | 477ba620 | Aurelien Jarno | break;
|
2084 | 477ba620 | Aurelien Jarno | case INDEX_op_ext32u_i64:
|
2085 | 477ba620 | Aurelien Jarno | tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]); |
2086 | 477ba620 | Aurelien Jarno | break;
|
2087 | 477ba620 | Aurelien Jarno | |
2088 | 477ba620 | Aurelien Jarno | case INDEX_op_bswap16_i32:
|
2089 | 477ba620 | Aurelien Jarno | case INDEX_op_bswap16_i64:
|
2090 | 477ba620 | Aurelien Jarno | tcg_out_bswap16(s, args[0], args[1]); |
2091 | 477ba620 | Aurelien Jarno | break;
|
2092 | 477ba620 | Aurelien Jarno | case INDEX_op_bswap32_i32:
|
2093 | 477ba620 | Aurelien Jarno | case INDEX_op_bswap32_i64:
|
2094 | 477ba620 | Aurelien Jarno | tcg_out_bswap32(s, args[0], args[1]); |
2095 | 477ba620 | Aurelien Jarno | break;
|
2096 | 477ba620 | Aurelien Jarno | case INDEX_op_bswap64_i64:
|
2097 | 477ba620 | Aurelien Jarno | tcg_out_bswap64(s, args[0], args[1]); |
2098 | 477ba620 | Aurelien Jarno | break;
|
2099 | 477ba620 | Aurelien Jarno | |
2100 | 477ba620 | Aurelien Jarno | case INDEX_op_brcond_i32:
|
2101 | 477ba620 | Aurelien Jarno | tcg_out_brcond(s, args[2], args[0], const_args[0], |
2102 | 477ba620 | Aurelien Jarno | args[1], const_args[1], args[3], 1); |
2103 | 477ba620 | Aurelien Jarno | break;
|
2104 | 477ba620 | Aurelien Jarno | case INDEX_op_brcond_i64:
|
2105 | 477ba620 | Aurelien Jarno | tcg_out_brcond(s, args[2], args[0], const_args[0], |
2106 | 477ba620 | Aurelien Jarno | args[1], const_args[1], args[3], 0); |
2107 | 477ba620 | Aurelien Jarno | break;
|
2108 | 477ba620 | Aurelien Jarno | case INDEX_op_setcond_i32:
|
2109 | 477ba620 | Aurelien Jarno | tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1); |
2110 | 477ba620 | Aurelien Jarno | break;
|
2111 | 477ba620 | Aurelien Jarno | case INDEX_op_setcond_i64:
|
2112 | 477ba620 | Aurelien Jarno | tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0); |
2113 | 477ba620 | Aurelien Jarno | break;
|
2114 | 477ba620 | Aurelien Jarno | |
2115 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_ld8u:
|
2116 | 477ba620 | Aurelien Jarno | tcg_out_qemu_ld(s, args, 0);
|
2117 | 477ba620 | Aurelien Jarno | break;
|
2118 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_ld8s:
|
2119 | 477ba620 | Aurelien Jarno | tcg_out_qemu_ld(s, args, 0 | 4); |
2120 | 477ba620 | Aurelien Jarno | break;
|
2121 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_ld16u:
|
2122 | 477ba620 | Aurelien Jarno | tcg_out_qemu_ld(s, args, 1);
|
2123 | 477ba620 | Aurelien Jarno | break;
|
2124 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_ld16s:
|
2125 | 477ba620 | Aurelien Jarno | tcg_out_qemu_ld(s, args, 1 | 4); |
2126 | 477ba620 | Aurelien Jarno | break;
|
2127 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_ld32u:
|
2128 | 477ba620 | Aurelien Jarno | tcg_out_qemu_ld(s, args, 2);
|
2129 | 477ba620 | Aurelien Jarno | break;
|
2130 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_ld32s:
|
2131 | 477ba620 | Aurelien Jarno | tcg_out_qemu_ld(s, args, 2 | 4); |
2132 | 477ba620 | Aurelien Jarno | break;
|
2133 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_ld64:
|
2134 | 477ba620 | Aurelien Jarno | tcg_out_qemu_ld(s, args, 3);
|
2135 | 477ba620 | Aurelien Jarno | break;
|
2136 | 477ba620 | Aurelien Jarno | |
2137 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_st8:
|
2138 | 477ba620 | Aurelien Jarno | tcg_out_qemu_st(s, args, 0);
|
2139 | 477ba620 | Aurelien Jarno | break;
|
2140 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_st16:
|
2141 | 477ba620 | Aurelien Jarno | tcg_out_qemu_st(s, args, 1);
|
2142 | 477ba620 | Aurelien Jarno | break;
|
2143 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_st32:
|
2144 | 477ba620 | Aurelien Jarno | tcg_out_qemu_st(s, args, 2);
|
2145 | 477ba620 | Aurelien Jarno | break;
|
2146 | 477ba620 | Aurelien Jarno | case INDEX_op_qemu_st64:
|
2147 | 477ba620 | Aurelien Jarno | tcg_out_qemu_st(s, args, 3);
|
2148 | 477ba620 | Aurelien Jarno | break;
|
2149 | 477ba620 | Aurelien Jarno | |
2150 | 477ba620 | Aurelien Jarno | default:
|
2151 | 477ba620 | Aurelien Jarno | tcg_abort(); |
2152 | 477ba620 | Aurelien Jarno | } |
2153 | 477ba620 | Aurelien Jarno | } |
2154 | 477ba620 | Aurelien Jarno | |
2155 | 477ba620 | Aurelien Jarno | static const TCGTargetOpDef ia64_op_defs[] = { |
2156 | 477ba620 | Aurelien Jarno | { INDEX_op_br, { } }, |
2157 | 477ba620 | Aurelien Jarno | { INDEX_op_call, { "r" } },
|
2158 | 477ba620 | Aurelien Jarno | { INDEX_op_exit_tb, { } }, |
2159 | 477ba620 | Aurelien Jarno | { INDEX_op_goto_tb, { } }, |
2160 | 477ba620 | Aurelien Jarno | { INDEX_op_jmp, { "r" } },
|
2161 | 477ba620 | Aurelien Jarno | |
2162 | 477ba620 | Aurelien Jarno | { INDEX_op_mov_i32, { "r", "r" } }, |
2163 | 477ba620 | Aurelien Jarno | { INDEX_op_movi_i32, { "r" } },
|
2164 | 477ba620 | Aurelien Jarno | |
2165 | 477ba620 | Aurelien Jarno | { INDEX_op_ld8u_i32, { "r", "r" } }, |
2166 | 477ba620 | Aurelien Jarno | { INDEX_op_ld8s_i32, { "r", "r" } }, |
2167 | 477ba620 | Aurelien Jarno | { INDEX_op_ld16u_i32, { "r", "r" } }, |
2168 | 477ba620 | Aurelien Jarno | { INDEX_op_ld16s_i32, { "r", "r" } }, |
2169 | 477ba620 | Aurelien Jarno | { INDEX_op_ld_i32, { "r", "r" } }, |
2170 | 477ba620 | Aurelien Jarno | { INDEX_op_st8_i32, { "rZ", "r" } }, |
2171 | 477ba620 | Aurelien Jarno | { INDEX_op_st16_i32, { "rZ", "r" } }, |
2172 | 477ba620 | Aurelien Jarno | { INDEX_op_st_i32, { "rZ", "r" } }, |
2173 | 477ba620 | Aurelien Jarno | |
2174 | 477ba620 | Aurelien Jarno | { INDEX_op_add_i32, { "r", "rI", "rI" } }, |
2175 | 477ba620 | Aurelien Jarno | { INDEX_op_sub_i32, { "r", "rI", "rI" } }, |
2176 | 477ba620 | Aurelien Jarno | |
2177 | 477ba620 | Aurelien Jarno | { INDEX_op_and_i32, { "r", "rI", "rI" } }, |
2178 | 477ba620 | Aurelien Jarno | { INDEX_op_andc_i32, { "r", "rI", "rI" } }, |
2179 | 477ba620 | Aurelien Jarno | { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } }, |
2180 | 477ba620 | Aurelien Jarno | { INDEX_op_nand_i32, { "r", "rZ", "rZ" } }, |
2181 | 477ba620 | Aurelien Jarno | { INDEX_op_nor_i32, { "r", "rZ", "rZ" } }, |
2182 | 477ba620 | Aurelien Jarno | { INDEX_op_or_i32, { "r", "rI", "rI" } }, |
2183 | 477ba620 | Aurelien Jarno | { INDEX_op_orc_i32, { "r", "rZ", "rZ" } }, |
2184 | 477ba620 | Aurelien Jarno | { INDEX_op_xor_i32, { "r", "rI", "rI" } }, |
2185 | 477ba620 | Aurelien Jarno | |
2186 | 477ba620 | Aurelien Jarno | { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, |
2187 | 477ba620 | Aurelien Jarno | |
2188 | 477ba620 | Aurelien Jarno | { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, |
2189 | 477ba620 | Aurelien Jarno | { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, |
2190 | 477ba620 | Aurelien Jarno | { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, |
2191 | 477ba620 | Aurelien Jarno | { INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, |
2192 | 477ba620 | Aurelien Jarno | { INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, |
2193 | 477ba620 | Aurelien Jarno | |
2194 | 477ba620 | Aurelien Jarno | { INDEX_op_ext8s_i32, { "r", "rZ"} }, |
2195 | 477ba620 | Aurelien Jarno | { INDEX_op_ext8u_i32, { "r", "rZ"} }, |
2196 | 477ba620 | Aurelien Jarno | { INDEX_op_ext16s_i32, { "r", "rZ"} }, |
2197 | 477ba620 | Aurelien Jarno | { INDEX_op_ext16u_i32, { "r", "rZ"} }, |
2198 | 477ba620 | Aurelien Jarno | |
2199 | 477ba620 | Aurelien Jarno | { INDEX_op_bswap16_i32, { "r", "rZ" } }, |
2200 | 477ba620 | Aurelien Jarno | { INDEX_op_bswap32_i32, { "r", "rZ" } }, |
2201 | 477ba620 | Aurelien Jarno | |
2202 | 477ba620 | Aurelien Jarno | { INDEX_op_brcond_i32, { "rI", "rI" } }, |
2203 | 477ba620 | Aurelien Jarno | { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, |
2204 | 477ba620 | Aurelien Jarno | |
2205 | 477ba620 | Aurelien Jarno | { INDEX_op_mov_i64, { "r", "r" } }, |
2206 | 477ba620 | Aurelien Jarno | { INDEX_op_movi_i64, { "r" } },
|
2207 | 477ba620 | Aurelien Jarno | |
2208 | 477ba620 | Aurelien Jarno | { INDEX_op_ld8u_i64, { "r", "r" } }, |
2209 | 477ba620 | Aurelien Jarno | { INDEX_op_ld8s_i64, { "r", "r" } }, |
2210 | 477ba620 | Aurelien Jarno | { INDEX_op_ld16u_i64, { "r", "r" } }, |
2211 | 477ba620 | Aurelien Jarno | { INDEX_op_ld16s_i64, { "r", "r" } }, |
2212 | 477ba620 | Aurelien Jarno | { INDEX_op_ld32u_i64, { "r", "r" } }, |
2213 | 477ba620 | Aurelien Jarno | { INDEX_op_ld32s_i64, { "r", "r" } }, |
2214 | 477ba620 | Aurelien Jarno | { INDEX_op_ld_i64, { "r", "r" } }, |
2215 | 477ba620 | Aurelien Jarno | { INDEX_op_st8_i64, { "rZ", "r" } }, |
2216 | 477ba620 | Aurelien Jarno | { INDEX_op_st16_i64, { "rZ", "r" } }, |
2217 | 477ba620 | Aurelien Jarno | { INDEX_op_st32_i64, { "rZ", "r" } }, |
2218 | 477ba620 | Aurelien Jarno | { INDEX_op_st_i64, { "rZ", "r" } }, |
2219 | 477ba620 | Aurelien Jarno | |
2220 | 477ba620 | Aurelien Jarno | { INDEX_op_add_i64, { "r", "rI", "rI" } }, |
2221 | 477ba620 | Aurelien Jarno | { INDEX_op_sub_i64, { "r", "rI", "rI" } }, |
2222 | 477ba620 | Aurelien Jarno | |
2223 | 477ba620 | Aurelien Jarno | { INDEX_op_and_i64, { "r", "rI", "rI" } }, |
2224 | 477ba620 | Aurelien Jarno | { INDEX_op_andc_i64, { "r", "rI", "rI" } }, |
2225 | 477ba620 | Aurelien Jarno | { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } }, |
2226 | 477ba620 | Aurelien Jarno | { INDEX_op_nand_i64, { "r", "rZ", "rZ" } }, |
2227 | 477ba620 | Aurelien Jarno | { INDEX_op_nor_i64, { "r", "rZ", "rZ" } }, |
2228 | 477ba620 | Aurelien Jarno | { INDEX_op_or_i64, { "r", "rI", "rI" } }, |
2229 | 477ba620 | Aurelien Jarno | { INDEX_op_orc_i64, { "r", "rZ", "rZ" } }, |
2230 | 477ba620 | Aurelien Jarno | { INDEX_op_xor_i64, { "r", "rI", "rI" } }, |
2231 | 477ba620 | Aurelien Jarno | |
2232 | 477ba620 | Aurelien Jarno | { INDEX_op_mul_i64, { "r", "rZ", "rZ" } }, |
2233 | 477ba620 | Aurelien Jarno | |
2234 | 477ba620 | Aurelien Jarno | { INDEX_op_sar_i64, { "r", "rZ", "ri" } }, |
2235 | 477ba620 | Aurelien Jarno | { INDEX_op_shl_i64, { "r", "rZ", "ri" } }, |
2236 | 477ba620 | Aurelien Jarno | { INDEX_op_shr_i64, { "r", "rZ", "ri" } }, |
2237 | 477ba620 | Aurelien Jarno | { INDEX_op_rotl_i64, { "r", "rZ", "ri" } }, |
2238 | 477ba620 | Aurelien Jarno | { INDEX_op_rotr_i64, { "r", "rZ", "ri" } }, |
2239 | 477ba620 | Aurelien Jarno | |
2240 | 477ba620 | Aurelien Jarno | { INDEX_op_ext8s_i64, { "r", "rZ"} }, |
2241 | 477ba620 | Aurelien Jarno | { INDEX_op_ext8u_i64, { "r", "rZ"} }, |
2242 | 477ba620 | Aurelien Jarno | { INDEX_op_ext16s_i64, { "r", "rZ"} }, |
2243 | 477ba620 | Aurelien Jarno | { INDEX_op_ext16u_i64, { "r", "rZ"} }, |
2244 | 477ba620 | Aurelien Jarno | { INDEX_op_ext32s_i64, { "r", "rZ"} }, |
2245 | 477ba620 | Aurelien Jarno | { INDEX_op_ext32u_i64, { "r", "rZ"} }, |
2246 | 477ba620 | Aurelien Jarno | |
2247 | 477ba620 | Aurelien Jarno | { INDEX_op_bswap16_i64, { "r", "rZ" } }, |
2248 | 477ba620 | Aurelien Jarno | { INDEX_op_bswap32_i64, { "r", "rZ" } }, |
2249 | 477ba620 | Aurelien Jarno | { INDEX_op_bswap64_i64, { "r", "rZ" } }, |
2250 | 477ba620 | Aurelien Jarno | |
2251 | 477ba620 | Aurelien Jarno | { INDEX_op_brcond_i64, { "rI", "rI" } }, |
2252 | 477ba620 | Aurelien Jarno | { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } }, |
2253 | 477ba620 | Aurelien Jarno | |
2254 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld8u, { "r", "r" } }, |
2255 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld8s, { "r", "r" } }, |
2256 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld16u, { "r", "r" } }, |
2257 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld16s, { "r", "r" } }, |
2258 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld32, { "r", "r" } }, |
2259 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld32u, { "r", "r" } }, |
2260 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld32s, { "r", "r" } }, |
2261 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_ld64, { "r", "r" } }, |
2262 | 477ba620 | Aurelien Jarno | |
2263 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_st8, { "SZ", "r" } }, |
2264 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_st16, { "SZ", "r" } }, |
2265 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_st32, { "SZ", "r" } }, |
2266 | 477ba620 | Aurelien Jarno | { INDEX_op_qemu_st64, { "SZ", "r" } }, |
2267 | 477ba620 | Aurelien Jarno | |
2268 | 477ba620 | Aurelien Jarno | { -1 },
|
2269 | 477ba620 | Aurelien Jarno | }; |
2270 | 477ba620 | Aurelien Jarno | |
2271 | 477ba620 | Aurelien Jarno | /* Generate global QEMU prologue and epilogue code */
|
2272 | e4d58b41 | Richard Henderson | static void tcg_target_qemu_prologue(TCGContext *s) |
2273 | 477ba620 | Aurelien Jarno | { |
2274 | 477ba620 | Aurelien Jarno | int frame_size;
|
2275 | 477ba620 | Aurelien Jarno | |
2276 | 477ba620 | Aurelien Jarno | /* reserve some stack space */
|
2277 | 477ba620 | Aurelien Jarno | frame_size = TCG_STATIC_CALL_ARGS_SIZE; |
2278 | 477ba620 | Aurelien Jarno | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
2279 | 477ba620 | Aurelien Jarno | ~(TCG_TARGET_STACK_ALIGN - 1);
|
2280 | 477ba620 | Aurelien Jarno | |
2281 | 477ba620 | Aurelien Jarno | /* First emit adhoc function descriptor */
|
2282 | 477ba620 | Aurelien Jarno | *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */ |
2283 | 477ba620 | Aurelien Jarno | s->code_ptr += 16; /* skip GP */ |
2284 | 477ba620 | Aurelien Jarno | |
2285 | 477ba620 | Aurelien Jarno | /* prologue */
|
2286 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, mII, |
2287 | 477ba620 | Aurelien Jarno | tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34, |
2288 | 477ba620 | Aurelien Jarno | TCG_REG_R33, 32, 24, 0), |
2289 | 477ba620 | Aurelien Jarno | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
2290 | 477ba620 | Aurelien Jarno | TCG_REG_B6, TCG_REG_R32, 0),
|
2291 | 477ba620 | Aurelien Jarno | tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, |
2292 | 477ba620 | Aurelien Jarno | TCG_REG_R32, TCG_REG_B0)); |
2293 | 6781d08d | Richard Henderson | |
2294 | 6781d08d | Richard Henderson | /* ??? If GUEST_BASE < 0x200000, we could load the register via
|
2295 | 6781d08d | Richard Henderson | an ADDL in the M slot of the next bundle. */
|
2296 | 6781d08d | Richard Henderson | if (GUEST_BASE != 0) { |
2297 | 6781d08d | Richard Henderson | tcg_out_bundle(s, mlx, |
2298 | 6781d08d | Richard Henderson | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
2299 | 6781d08d | Richard Henderson | tcg_opc_l2 (GUEST_BASE), |
2300 | 6781d08d | Richard Henderson | tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, |
2301 | 6781d08d | Richard Henderson | TCG_GUEST_BASE_REG, GUEST_BASE)); |
2302 | 6781d08d | Richard Henderson | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
2303 | 6781d08d | Richard Henderson | } |
2304 | 6781d08d | Richard Henderson | |
2305 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miB, |
2306 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
2307 | 477ba620 | Aurelien Jarno | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
2308 | 477ba620 | Aurelien Jarno | TCG_REG_R12, -frame_size, TCG_REG_R12), |
2309 | 477ba620 | Aurelien Jarno | tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); |
2310 | 477ba620 | Aurelien Jarno | |
2311 | 477ba620 | Aurelien Jarno | /* epilogue */
|
2312 | 477ba620 | Aurelien Jarno | tb_ret_addr = s->code_ptr; |
2313 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miI, |
2314 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
2315 | 477ba620 | Aurelien Jarno | tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, |
2316 | 477ba620 | Aurelien Jarno | TCG_REG_B0, TCG_REG_R32, 0),
|
2317 | 477ba620 | Aurelien Jarno | tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, |
2318 | 477ba620 | Aurelien Jarno | TCG_REG_R12, frame_size, TCG_REG_R12)); |
2319 | 477ba620 | Aurelien Jarno | tcg_out_bundle(s, miB, |
2320 | 477ba620 | Aurelien Jarno | tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
2321 | 477ba620 | Aurelien Jarno | tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26, |
2322 | 477ba620 | Aurelien Jarno | TCG_REG_PFS, TCG_REG_R33), |
2323 | 477ba620 | Aurelien Jarno | tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4, |
2324 | 477ba620 | Aurelien Jarno | TCG_REG_B0)); |
2325 | 477ba620 | Aurelien Jarno | } |
2326 | 477ba620 | Aurelien Jarno | |
2327 | e4d58b41 | Richard Henderson | static void tcg_target_init(TCGContext *s) |
2328 | 477ba620 | Aurelien Jarno | { |
2329 | 477ba620 | Aurelien Jarno | tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], |
2330 | 477ba620 | Aurelien Jarno | 0xffffffffffffffffull);
|
2331 | 477ba620 | Aurelien Jarno | tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], |
2332 | 477ba620 | Aurelien Jarno | 0xffffffffffffffffull);
|
2333 | 477ba620 | Aurelien Jarno | |
2334 | 7221f058 | Richard Henderson | tcg_regset_clear(tcg_target_call_clobber_regs); |
2335 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); |
2336 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); |
2337 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); |
2338 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); |
2339 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); |
2340 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15); |
2341 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16); |
2342 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17); |
2343 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18); |
2344 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19); |
2345 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20); |
2346 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21); |
2347 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22); |
2348 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23); |
2349 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24); |
2350 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25); |
2351 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26); |
2352 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27); |
2353 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28); |
2354 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29); |
2355 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30); |
2356 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31); |
2357 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56); |
2358 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57); |
2359 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58); |
2360 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59); |
2361 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60); |
2362 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61); |
2363 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62); |
2364 | 7221f058 | Richard Henderson | tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63); |
2365 | 7221f058 | Richard Henderson | |
2366 | 7221f058 | Richard Henderson | tcg_regset_clear(s->reserved_regs); |
2367 | 477ba620 | Aurelien Jarno | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
|
2368 | 477ba620 | Aurelien Jarno | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
|
2369 | 477ba620 | Aurelien Jarno | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
|
2370 | 477ba620 | Aurelien Jarno | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
|
2371 | 477ba620 | Aurelien Jarno | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
|
2372 | 7221f058 | Richard Henderson | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
|
2373 | 477ba620 | Aurelien Jarno | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
|
2374 | 477ba620 | Aurelien Jarno | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* PFS */
|
2375 | 477ba620 | Aurelien Jarno | |
2376 | 7221f058 | Richard Henderson | /* The following 3 are not in use, are call-saved, but *not* saved
|
2377 | 7221f058 | Richard Henderson | by the prologue. Therefore we cannot use them without modifying
|
2378 | 7221f058 | Richard Henderson | the prologue. There doesn't seem to be any good reason to use
|
2379 | 7221f058 | Richard Henderson | these as opposed to the windowed registers. */
|
2380 | 7221f058 | Richard Henderson | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4); |
2381 | 7221f058 | Richard Henderson | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5); |
2382 | 7221f058 | Richard Henderson | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6); |
2383 | 7221f058 | Richard Henderson | |
2384 | 477ba620 | Aurelien Jarno | tcg_add_target_add_op_defs(ia64_op_defs); |
2385 | 477ba620 | Aurelien Jarno | } |