root / target-sparc / translate.c @ 25517f99
History | View | Annotate | Download (186.8 kB)
1 | 7a3f1944 | bellard | /*
|
---|---|---|---|
2 | 7a3f1944 | bellard | SPARC translation
|
3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
|
5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
|
6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
|
8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
|
9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
|
10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
|
11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
|
13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 | 7a3f1944 | bellard | Lesser General Public License for more details.
|
16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
|
18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
|
19 | fad6cb1a | aurel32 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
|
20 | 7a3f1944 | bellard | */
|
21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | #include <stdarg.h> |
23 | 7a3f1944 | bellard | #include <stdlib.h> |
24 | 7a3f1944 | bellard | #include <stdio.h> |
25 | 7a3f1944 | bellard | #include <string.h> |
26 | 7a3f1944 | bellard | #include <inttypes.h> |
27 | 7a3f1944 | bellard | |
28 | 7a3f1944 | bellard | #include "cpu.h" |
29 | 7a3f1944 | bellard | #include "exec-all.h" |
30 | 7a3f1944 | bellard | #include "disas.h" |
31 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
32 | 57fec1fe | bellard | #include "tcg-op.h" |
33 | 7a3f1944 | bellard | |
34 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
35 | a7812ae4 | pbrook | #include "helper.h" |
36 | a7812ae4 | pbrook | |
37 | 7a3f1944 | bellard | #define DEBUG_DISAS
|
38 | 7a3f1944 | bellard | |
39 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
40 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
41 | 72cbca10 | bellard | according to jump_pc[T2] */
|
42 | 72cbca10 | bellard | |
43 | 1a2fb1c0 | blueswir1 | /* global register indexes */
|
44 | a7812ae4 | pbrook | static TCGv_ptr cpu_env, cpu_regwptr;
|
45 | 25517f99 | Paul Brook | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
|
46 | 25517f99 | Paul Brook | static TCGv_i32 cpu_cc_op;
|
47 | a7812ae4 | pbrook | static TCGv_i32 cpu_psr;
|
48 | a7812ae4 | pbrook | static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
49 | 255e1fcb | blueswir1 | static TCGv cpu_y;
|
50 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
51 | 255e1fcb | blueswir1 | static TCGv cpu_tbr;
|
52 | 255e1fcb | blueswir1 | #endif
|
53 | 6ae20372 | blueswir1 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
|
54 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
55 | a7812ae4 | pbrook | static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
|
56 | a7812ae4 | pbrook | static TCGv cpu_gsr;
|
57 | 255e1fcb | blueswir1 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
|
58 | a7812ae4 | pbrook | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
|
59 | a7812ae4 | pbrook | static TCGv_i32 cpu_softint;
|
60 | 255e1fcb | blueswir1 | #else
|
61 | 255e1fcb | blueswir1 | static TCGv cpu_wim;
|
62 | dc99a3f2 | blueswir1 | #endif
|
63 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
|
64 | a7812ae4 | pbrook | static TCGv cpu_tmp0;
|
65 | a7812ae4 | pbrook | static TCGv_i32 cpu_tmp32;
|
66 | a7812ae4 | pbrook | static TCGv_i64 cpu_tmp64;
|
67 | 714547bb | blueswir1 | /* Floating point registers */
|
68 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpr[TARGET_FPREGS];
|
69 | 1a2fb1c0 | blueswir1 | |
70 | 2e70f6ef | pbrook | #include "gen-icount.h" |
71 | 2e70f6ef | pbrook | |
72 | 7a3f1944 | bellard | typedef struct DisasContext { |
73 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
|
74 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
|
75 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
76 | cf495bcf | bellard | int is_br;
|
77 | e8af50a3 | bellard | int mem_idx;
|
78 | a80dde08 | bellard | int fpu_enabled;
|
79 | 2cade6a3 | blueswir1 | int address_mask_32bit;
|
80 | 8393617c | Blue Swirl | uint32_t cc_op; /* current CC operation */
|
81 | cf495bcf | bellard | struct TranslationBlock *tb;
|
82 | 5578ceab | blueswir1 | sparc_def_t *def; |
83 | 7a3f1944 | bellard | } DisasContext; |
84 | 7a3f1944 | bellard | |
85 | 3475187d | bellard | // This function uses non-native bit order
|
86 | dc1a6971 | Blue Swirl | #define GET_FIELD(X, FROM, TO) \
|
87 | dc1a6971 | Blue Swirl | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
88 | 7a3f1944 | bellard | |
89 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
|
90 | dc1a6971 | Blue Swirl | #define GET_FIELD_SP(X, FROM, TO) \
|
91 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
92 | 3475187d | bellard | |
93 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
94 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
95 | 3475187d | bellard | |
96 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
97 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
98 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
99 | 3475187d | bellard | #else
|
100 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
101 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
102 | 3475187d | bellard | #endif
|
103 | 3475187d | bellard | |
104 | b158a785 | blueswir1 | #define UA2005_HTRAP_MASK 0xff |
105 | b158a785 | blueswir1 | #define V8_TRAP_MASK 0x7f |
106 | b158a785 | blueswir1 | |
107 | 3475187d | bellard | static int sign_extend(int x, int len) |
108 | 3475187d | bellard | { |
109 | 3475187d | bellard | len = 32 - len;
|
110 | 3475187d | bellard | return (x << len) >> len;
|
111 | 3475187d | bellard | } |
112 | 3475187d | bellard | |
113 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
114 | 7a3f1944 | bellard | |
115 | ff07ec83 | blueswir1 | /* floating point registers moves */
|
116 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
117 | ff07ec83 | blueswir1 | { |
118 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + |
119 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
120 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
|
121 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
122 | ff07ec83 | blueswir1 | } |
123 | ff07ec83 | blueswir1 | |
124 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
125 | ff07ec83 | blueswir1 | { |
126 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + |
127 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
128 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
|
129 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
130 | ff07ec83 | blueswir1 | } |
131 | ff07ec83 | blueswir1 | |
132 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
133 | ff07ec83 | blueswir1 | { |
134 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + |
135 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
136 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
|
137 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
138 | ff07ec83 | blueswir1 | } |
139 | ff07ec83 | blueswir1 | |
140 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
141 | ff07ec83 | blueswir1 | { |
142 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + |
143 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
144 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
|
145 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
146 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
|
147 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
148 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
|
149 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
150 | ff07ec83 | blueswir1 | } |
151 | ff07ec83 | blueswir1 | |
152 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
153 | ff07ec83 | blueswir1 | { |
154 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + |
155 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
156 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
|
157 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
158 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
|
159 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
160 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
|
161 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
162 | ff07ec83 | blueswir1 | } |
163 | ff07ec83 | blueswir1 | |
164 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
165 | ff07ec83 | blueswir1 | { |
166 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + |
167 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
168 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
|
169 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
170 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
|
171 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
172 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
|
173 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
174 | ff07ec83 | blueswir1 | } |
175 | 1f587329 | blueswir1 | |
176 | 81ad8ba2 | blueswir1 | /* moves */
|
177 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
178 | 3475187d | bellard | #define supervisor(dc) 0 |
179 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
|
180 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
181 | 81ad8ba2 | blueswir1 | #endif
|
182 | 3475187d | bellard | #else
|
183 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
184 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
|
185 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
186 | 6f27aba6 | blueswir1 | #else
|
187 | 3475187d | bellard | #endif
|
188 | 81ad8ba2 | blueswir1 | #endif
|
189 | 81ad8ba2 | blueswir1 | |
190 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
191 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
|
192 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
|
193 | 1a2fb1c0 | blueswir1 | #else
|
194 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
195 | 2cade6a3 | blueswir1 | #endif
|
196 | 1a2fb1c0 | blueswir1 | #endif
|
197 | 3391c818 | blueswir1 | |
198 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
199 | 2cade6a3 | blueswir1 | { |
200 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
201 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
|
202 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
|
203 | 2cade6a3 | blueswir1 | #endif
|
204 | 2cade6a3 | blueswir1 | } |
205 | 2cade6a3 | blueswir1 | |
206 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
207 | 81ad8ba2 | blueswir1 | { |
208 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
209 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
|
210 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
211 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
212 | 1a2fb1c0 | blueswir1 | else {
|
213 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
214 | 81ad8ba2 | blueswir1 | } |
215 | 81ad8ba2 | blueswir1 | } |
216 | 81ad8ba2 | blueswir1 | |
217 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
218 | 81ad8ba2 | blueswir1 | { |
219 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
220 | 1a2fb1c0 | blueswir1 | return;
|
221 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
222 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
223 | 1a2fb1c0 | blueswir1 | else {
|
224 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
225 | 81ad8ba2 | blueswir1 | } |
226 | 81ad8ba2 | blueswir1 | } |
227 | 81ad8ba2 | blueswir1 | |
228 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
229 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
230 | 6e256c93 | bellard | { |
231 | 6e256c93 | bellard | TranslationBlock *tb; |
232 | 6e256c93 | bellard | |
233 | 6e256c93 | bellard | tb = s->tb; |
234 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
|
235 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
236 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
|
237 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
238 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
239 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
240 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
|
241 | 6e256c93 | bellard | } else {
|
242 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
|
243 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
244 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
245 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
246 | 6e256c93 | bellard | } |
247 | 6e256c93 | bellard | } |
248 | 6e256c93 | bellard | |
249 | 19f329ad | blueswir1 | // XXX suboptimal
|
250 | a7812ae4 | pbrook | static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) |
251 | 19f329ad | blueswir1 | { |
252 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
253 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
254 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
255 | 19f329ad | blueswir1 | } |
256 | 19f329ad | blueswir1 | |
257 | a7812ae4 | pbrook | static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) |
258 | 19f329ad | blueswir1 | { |
259 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
260 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
261 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
262 | 19f329ad | blueswir1 | } |
263 | 19f329ad | blueswir1 | |
264 | a7812ae4 | pbrook | static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) |
265 | 19f329ad | blueswir1 | { |
266 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
267 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
268 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
269 | 19f329ad | blueswir1 | } |
270 | 19f329ad | blueswir1 | |
271 | a7812ae4 | pbrook | static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) |
272 | 19f329ad | blueswir1 | { |
273 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
274 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
275 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
276 | 19f329ad | blueswir1 | } |
277 | 19f329ad | blueswir1 | |
278 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
279 | dc99a3f2 | blueswir1 | { |
280 | a7812ae4 | pbrook | TCGv r_temp; |
281 | a7812ae4 | pbrook | TCGv_i32 r_const; |
282 | dc99a3f2 | blueswir1 | int l1;
|
283 | dc99a3f2 | blueswir1 | |
284 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
285 | dc99a3f2 | blueswir1 | |
286 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
287 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
288 | 2576d836 | blueswir1 | tcg_gen_not_tl(r_temp, r_temp); |
289 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
290 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
291 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
292 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
293 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
294 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
295 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
296 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
297 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
298 | dc99a3f2 | blueswir1 | } |
299 | dc99a3f2 | blueswir1 | |
300 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
301 | dc99a3f2 | blueswir1 | { |
302 | dc99a3f2 | blueswir1 | int l1;
|
303 | a7812ae4 | pbrook | TCGv_i32 r_const; |
304 | dc99a3f2 | blueswir1 | |
305 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
306 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
307 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
308 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
309 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
310 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
311 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
312 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
313 | dc99a3f2 | blueswir1 | } |
314 | dc99a3f2 | blueswir1 | |
315 | 41d72852 | Blue Swirl | static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2) |
316 | 41d72852 | Blue Swirl | { |
317 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
318 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
319 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2); |
320 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
321 | 41d72852 | Blue Swirl | } |
322 | 41d72852 | Blue Swirl | |
323 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
324 | dc99a3f2 | blueswir1 | { |
325 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
326 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
327 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
328 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
329 | 41d72852 | Blue Swirl | } |
330 | 41d72852 | Blue Swirl | |
331 | 41d72852 | Blue Swirl | static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2) |
332 | dc99a3f2 | blueswir1 | { |
333 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
334 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
335 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
336 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
337 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
338 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
339 | 41d72852 | Blue Swirl | } |
340 | 41d72852 | Blue Swirl | |
341 | 41d72852 | Blue Swirl | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
342 | 41d72852 | Blue Swirl | { |
343 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
344 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
345 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
346 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
347 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
348 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
349 | dc99a3f2 | blueswir1 | } |
350 | dc99a3f2 | blueswir1 | |
351 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
352 | dc99a3f2 | blueswir1 | { |
353 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
354 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
355 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
356 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
357 | dc99a3f2 | blueswir1 | } |
358 | dc99a3f2 | blueswir1 | |
359 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
360 | dc99a3f2 | blueswir1 | { |
361 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
362 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
363 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
364 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
365 | 5c6a0628 | blueswir1 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
366 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
367 | dc99a3f2 | blueswir1 | } |
368 | dc99a3f2 | blueswir1 | |
369 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
370 | dc99a3f2 | blueswir1 | { |
371 | a7812ae4 | pbrook | TCGv r_temp; |
372 | a7812ae4 | pbrook | TCGv_i32 r_const; |
373 | dc99a3f2 | blueswir1 | int l1;
|
374 | dc99a3f2 | blueswir1 | |
375 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
376 | dc99a3f2 | blueswir1 | |
377 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
378 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
379 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
380 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
381 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
382 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
383 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
384 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
385 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
386 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
387 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
388 | dc99a3f2 | blueswir1 | } |
389 | dc99a3f2 | blueswir1 | |
390 | d4b0d468 | Blue Swirl | static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc) |
391 | 41d72852 | Blue Swirl | { |
392 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
393 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
394 | 719f66a7 | Blue Swirl | if (src2 == 0) { |
395 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, src1); |
396 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
397 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
398 | 719f66a7 | Blue Swirl | } else {
|
399 | 719f66a7 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2); |
400 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
401 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
402 | 719f66a7 | Blue Swirl | } |
403 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
404 | 41d72852 | Blue Swirl | } |
405 | 41d72852 | Blue Swirl | |
406 | 41d72852 | Blue Swirl | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
407 | dc99a3f2 | blueswir1 | { |
408 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
409 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
410 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
411 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
412 | 41d72852 | Blue Swirl | } |
413 | 41d72852 | Blue Swirl | |
414 | 41d72852 | Blue Swirl | static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) |
415 | 41d72852 | Blue Swirl | { |
416 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
417 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
418 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
419 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
420 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
421 | 2ca1d92b | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
422 | 41d72852 | Blue Swirl | } |
423 | 41d72852 | Blue Swirl | |
424 | 41d72852 | Blue Swirl | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
425 | 41d72852 | Blue Swirl | { |
426 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
427 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
428 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
429 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
430 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
431 | 2ca1d92b | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
432 | dc99a3f2 | blueswir1 | } |
433 | dc99a3f2 | blueswir1 | |
434 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
435 | dc99a3f2 | blueswir1 | { |
436 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
437 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
438 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
439 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
440 | dc99a3f2 | blueswir1 | } |
441 | dc99a3f2 | blueswir1 | |
442 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
443 | dc99a3f2 | blueswir1 | { |
444 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
445 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
446 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
447 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
448 | 5c6a0628 | blueswir1 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
449 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
450 | dc99a3f2 | blueswir1 | } |
451 | dc99a3f2 | blueswir1 | |
452 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
453 | d9bdab86 | blueswir1 | { |
454 | 105a1f04 | blueswir1 | TCGv r_temp; |
455 | 6f551262 | blueswir1 | int l1;
|
456 | d9bdab86 | blueswir1 | |
457 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
458 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
459 | d9bdab86 | blueswir1 | |
460 | d9bdab86 | blueswir1 | /* old op:
|
461 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
462 | d9bdab86 | blueswir1 | T1 = 0;
|
463 | d9bdab86 | blueswir1 | */
|
464 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
|
465 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
|
466 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
|
467 | 105a1f04 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
468 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
469 | 6f551262 | blueswir1 | gen_set_label(l1); |
470 | d9bdab86 | blueswir1 | |
471 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
472 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
473 | 105a1f04 | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
|
474 | 105a1f04 | blueswir1 | tcg_gen_shli_tl(r_temp, r_temp, 31);
|
475 | 255e1fcb | blueswir1 | tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
|
476 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
|
477 | 5068cbd9 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
478 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
479 | d9bdab86 | blueswir1 | |
480 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
481 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
482 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
483 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
484 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
485 | d9bdab86 | blueswir1 | |
486 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
487 | d9bdab86 | blueswir1 | // src1 = T0;
|
488 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
489 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
490 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
491 | d9bdab86 | blueswir1 | |
492 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
493 | d9bdab86 | blueswir1 | |
494 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
495 | d9bdab86 | blueswir1 | } |
496 | d9bdab86 | blueswir1 | |
497 | 4af984a7 | blueswir1 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
498 | 8879d139 | blueswir1 | { |
499 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
500 | 8879d139 | blueswir1 | |
501 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
502 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
503 | 8879d139 | blueswir1 | |
504 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp, src2); |
505 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp2, src1); |
506 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
507 | 8879d139 | blueswir1 | |
508 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
509 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
510 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
511 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
512 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
513 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
514 | 8879d139 | blueswir1 | #else
|
515 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
516 | 8879d139 | blueswir1 | #endif
|
517 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
518 | 8879d139 | blueswir1 | } |
519 | 8879d139 | blueswir1 | |
520 | 4af984a7 | blueswir1 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
521 | 8879d139 | blueswir1 | { |
522 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
523 | 8879d139 | blueswir1 | |
524 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
525 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
526 | 8879d139 | blueswir1 | |
527 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp, src2); |
528 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp2, src1); |
529 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
530 | 8879d139 | blueswir1 | |
531 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
532 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
533 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
534 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
535 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
536 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
537 | 8879d139 | blueswir1 | #else
|
538 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
539 | 8879d139 | blueswir1 | #endif
|
540 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
541 | 8879d139 | blueswir1 | } |
542 | 8879d139 | blueswir1 | |
543 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
544 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
545 | 1a7b60e7 | blueswir1 | { |
546 | a7812ae4 | pbrook | TCGv_i32 r_const; |
547 | 1a7b60e7 | blueswir1 | int l1;
|
548 | 1a7b60e7 | blueswir1 | |
549 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
550 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
|
551 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_DIV_ZERO); |
552 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
553 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
554 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
555 | 1a7b60e7 | blueswir1 | } |
556 | 1a7b60e7 | blueswir1 | |
557 | 4af984a7 | blueswir1 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
558 | 1a7b60e7 | blueswir1 | { |
559 | 1a7b60e7 | blueswir1 | int l1, l2;
|
560 | 1a7b60e7 | blueswir1 | |
561 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
562 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
563 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
564 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
565 | 5c6a0628 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
566 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
567 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
|
568 | 4af984a7 | blueswir1 | tcg_gen_movi_i64(dst, INT64_MIN); |
569 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
570 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
571 | 6f551262 | blueswir1 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
572 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
573 | 1a7b60e7 | blueswir1 | } |
574 | 1a7b60e7 | blueswir1 | #endif
|
575 | 1a7b60e7 | blueswir1 | |
576 | 19f329ad | blueswir1 | // 1
|
577 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
578 | 19f329ad | blueswir1 | { |
579 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
580 | 19f329ad | blueswir1 | } |
581 | 19f329ad | blueswir1 | |
582 | 19f329ad | blueswir1 | // Z
|
583 | a7812ae4 | pbrook | static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) |
584 | 19f329ad | blueswir1 | { |
585 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
586 | 19f329ad | blueswir1 | } |
587 | 19f329ad | blueswir1 | |
588 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
589 | a7812ae4 | pbrook | static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) |
590 | 19f329ad | blueswir1 | { |
591 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
592 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
593 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
594 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
595 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
596 | 19f329ad | blueswir1 | } |
597 | 19f329ad | blueswir1 | |
598 | 19f329ad | blueswir1 | // N ^ V
|
599 | a7812ae4 | pbrook | static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) |
600 | 19f329ad | blueswir1 | { |
601 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
602 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
603 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
604 | 19f329ad | blueswir1 | } |
605 | 19f329ad | blueswir1 | |
606 | 19f329ad | blueswir1 | // C | Z
|
607 | a7812ae4 | pbrook | static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) |
608 | 19f329ad | blueswir1 | { |
609 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
610 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
611 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
612 | 19f329ad | blueswir1 | } |
613 | 19f329ad | blueswir1 | |
614 | 19f329ad | blueswir1 | // C
|
615 | a7812ae4 | pbrook | static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) |
616 | 19f329ad | blueswir1 | { |
617 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
618 | 19f329ad | blueswir1 | } |
619 | 19f329ad | blueswir1 | |
620 | 19f329ad | blueswir1 | // V
|
621 | a7812ae4 | pbrook | static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) |
622 | 19f329ad | blueswir1 | { |
623 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
624 | 19f329ad | blueswir1 | } |
625 | 19f329ad | blueswir1 | |
626 | 19f329ad | blueswir1 | // 0
|
627 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
628 | 19f329ad | blueswir1 | { |
629 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
630 | 19f329ad | blueswir1 | } |
631 | 19f329ad | blueswir1 | |
632 | 19f329ad | blueswir1 | // N
|
633 | a7812ae4 | pbrook | static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) |
634 | 19f329ad | blueswir1 | { |
635 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
636 | 19f329ad | blueswir1 | } |
637 | 19f329ad | blueswir1 | |
638 | 19f329ad | blueswir1 | // !Z
|
639 | a7812ae4 | pbrook | static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) |
640 | 19f329ad | blueswir1 | { |
641 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
642 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
643 | 19f329ad | blueswir1 | } |
644 | 19f329ad | blueswir1 | |
645 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
646 | a7812ae4 | pbrook | static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) |
647 | 19f329ad | blueswir1 | { |
648 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
649 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
650 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
651 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
652 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
653 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
654 | 19f329ad | blueswir1 | } |
655 | 19f329ad | blueswir1 | |
656 | 19f329ad | blueswir1 | // !(N ^ V)
|
657 | a7812ae4 | pbrook | static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) |
658 | 19f329ad | blueswir1 | { |
659 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
660 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
661 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
662 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
663 | 19f329ad | blueswir1 | } |
664 | 19f329ad | blueswir1 | |
665 | 19f329ad | blueswir1 | // !(C | Z)
|
666 | a7812ae4 | pbrook | static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) |
667 | 19f329ad | blueswir1 | { |
668 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
669 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
670 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
671 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
672 | 19f329ad | blueswir1 | } |
673 | 19f329ad | blueswir1 | |
674 | 19f329ad | blueswir1 | // !C
|
675 | a7812ae4 | pbrook | static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) |
676 | 19f329ad | blueswir1 | { |
677 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
678 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
679 | 19f329ad | blueswir1 | } |
680 | 19f329ad | blueswir1 | |
681 | 19f329ad | blueswir1 | // !N
|
682 | a7812ae4 | pbrook | static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) |
683 | 19f329ad | blueswir1 | { |
684 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
685 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
686 | 19f329ad | blueswir1 | } |
687 | 19f329ad | blueswir1 | |
688 | 19f329ad | blueswir1 | // !V
|
689 | a7812ae4 | pbrook | static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) |
690 | 19f329ad | blueswir1 | { |
691 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
692 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
693 | 19f329ad | blueswir1 | } |
694 | 19f329ad | blueswir1 | |
695 | 19f329ad | blueswir1 | /*
|
696 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
697 | 19f329ad | blueswir1 | 0 =
|
698 | 19f329ad | blueswir1 | 1 <
|
699 | 19f329ad | blueswir1 | 2 >
|
700 | 19f329ad | blueswir1 | 3 unordered
|
701 | 19f329ad | blueswir1 | */
|
702 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
703 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
704 | 19f329ad | blueswir1 | { |
705 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
706 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
707 | 19f329ad | blueswir1 | } |
708 | 19f329ad | blueswir1 | |
709 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
710 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
711 | 19f329ad | blueswir1 | { |
712 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
713 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
714 | 19f329ad | blueswir1 | } |
715 | 19f329ad | blueswir1 | |
716 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
717 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
718 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
719 | 19f329ad | blueswir1 | { |
720 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
721 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
722 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
723 | 19f329ad | blueswir1 | } |
724 | 19f329ad | blueswir1 | |
725 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
726 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
727 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
728 | 19f329ad | blueswir1 | { |
729 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
730 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
731 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
732 | 19f329ad | blueswir1 | } |
733 | 19f329ad | blueswir1 | |
734 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
735 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
736 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
737 | 19f329ad | blueswir1 | { |
738 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
739 | 19f329ad | blueswir1 | } |
740 | 19f329ad | blueswir1 | |
741 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
742 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
743 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
744 | 19f329ad | blueswir1 | { |
745 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
746 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
747 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
748 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
749 | 19f329ad | blueswir1 | } |
750 | 19f329ad | blueswir1 | |
751 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
752 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
753 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
754 | 19f329ad | blueswir1 | { |
755 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
756 | 19f329ad | blueswir1 | } |
757 | 19f329ad | blueswir1 | |
758 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
759 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
760 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
761 | 19f329ad | blueswir1 | { |
762 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
763 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
764 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
765 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
766 | 19f329ad | blueswir1 | } |
767 | 19f329ad | blueswir1 | |
768 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
769 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
770 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
771 | 19f329ad | blueswir1 | { |
772 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
773 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
774 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
775 | 19f329ad | blueswir1 | } |
776 | 19f329ad | blueswir1 | |
777 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
778 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
779 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
780 | 19f329ad | blueswir1 | { |
781 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
782 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
783 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
784 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
785 | 19f329ad | blueswir1 | } |
786 | 19f329ad | blueswir1 | |
787 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
788 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
789 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
790 | 19f329ad | blueswir1 | { |
791 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
792 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
793 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
794 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
795 | 19f329ad | blueswir1 | } |
796 | 19f329ad | blueswir1 | |
797 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
798 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
799 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
800 | 19f329ad | blueswir1 | { |
801 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
802 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
803 | 19f329ad | blueswir1 | } |
804 | 19f329ad | blueswir1 | |
805 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
806 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
807 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
808 | 19f329ad | blueswir1 | { |
809 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
810 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
811 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
812 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
813 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
814 | 19f329ad | blueswir1 | } |
815 | 19f329ad | blueswir1 | |
816 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
817 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
818 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
819 | 19f329ad | blueswir1 | { |
820 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
821 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
822 | 19f329ad | blueswir1 | } |
823 | 19f329ad | blueswir1 | |
824 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
825 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
826 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
827 | 19f329ad | blueswir1 | { |
828 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
829 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
830 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
831 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
832 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
833 | 19f329ad | blueswir1 | } |
834 | 19f329ad | blueswir1 | |
835 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
836 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
837 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
838 | 19f329ad | blueswir1 | { |
839 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
840 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
841 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
842 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
843 | 19f329ad | blueswir1 | } |
844 | 19f329ad | blueswir1 | |
845 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
846 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
847 | 83469015 | bellard | { |
848 | 83469015 | bellard | int l1;
|
849 | 83469015 | bellard | |
850 | 83469015 | bellard | l1 = gen_new_label(); |
851 | 83469015 | bellard | |
852 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
853 | 83469015 | bellard | |
854 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
855 | 83469015 | bellard | |
856 | 83469015 | bellard | gen_set_label(l1); |
857 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
858 | 83469015 | bellard | } |
859 | 83469015 | bellard | |
860 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
861 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
862 | 83469015 | bellard | { |
863 | 83469015 | bellard | int l1;
|
864 | 83469015 | bellard | |
865 | 83469015 | bellard | l1 = gen_new_label(); |
866 | 83469015 | bellard | |
867 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
868 | 83469015 | bellard | |
869 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
870 | 83469015 | bellard | |
871 | 83469015 | bellard | gen_set_label(l1); |
872 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
873 | 83469015 | bellard | } |
874 | 83469015 | bellard | |
875 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
876 | 19f329ad | blueswir1 | TCGv r_cond) |
877 | 83469015 | bellard | { |
878 | 83469015 | bellard | int l1, l2;
|
879 | 83469015 | bellard | |
880 | 83469015 | bellard | l1 = gen_new_label(); |
881 | 83469015 | bellard | l2 = gen_new_label(); |
882 | 19f329ad | blueswir1 | |
883 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
884 | 83469015 | bellard | |
885 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc1); |
886 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
887 | 83469015 | bellard | |
888 | 83469015 | bellard | gen_set_label(l1); |
889 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc2); |
890 | 83469015 | bellard | gen_set_label(l2); |
891 | 83469015 | bellard | } |
892 | 83469015 | bellard | |
893 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
894 | 4af984a7 | blueswir1 | have been set for a jump */
|
895 | 4af984a7 | blueswir1 | static inline void flush_cond(DisasContext *dc, TCGv cond) |
896 | 83469015 | bellard | { |
897 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
898 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
899 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
900 | 83469015 | bellard | } |
901 | 83469015 | bellard | } |
902 | 83469015 | bellard | |
903 | 4af984a7 | blueswir1 | static inline void save_npc(DisasContext *dc, TCGv cond) |
904 | 72cbca10 | bellard | { |
905 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
906 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
907 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
908 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
909 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
910 | 72cbca10 | bellard | } |
911 | 72cbca10 | bellard | } |
912 | 72cbca10 | bellard | |
913 | 4af984a7 | blueswir1 | static inline void save_state(DisasContext *dc, TCGv cond) |
914 | 72cbca10 | bellard | { |
915 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
916 | 4af984a7 | blueswir1 | save_npc(dc, cond); |
917 | 72cbca10 | bellard | } |
918 | 72cbca10 | bellard | |
919 | 4af984a7 | blueswir1 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
920 | 0bee699e | bellard | { |
921 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
922 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
923 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
924 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
925 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
926 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
927 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
928 | 0bee699e | bellard | } else {
|
929 | 0bee699e | bellard | dc->pc = dc->npc; |
930 | 0bee699e | bellard | } |
931 | 0bee699e | bellard | } |
932 | 0bee699e | bellard | |
933 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
934 | 38bc628b | blueswir1 | { |
935 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
936 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
937 | 38bc628b | blueswir1 | } |
938 | 38bc628b | blueswir1 | |
939 | 8393617c | Blue Swirl | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, |
940 | 8393617c | Blue Swirl | DisasContext *dc) |
941 | 19f329ad | blueswir1 | { |
942 | a7812ae4 | pbrook | TCGv_i32 r_src; |
943 | 3475187d | bellard | |
944 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
945 | 19f329ad | blueswir1 | if (cc)
|
946 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
947 | 19f329ad | blueswir1 | else
|
948 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
949 | 3475187d | bellard | #else
|
950 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
951 | 3475187d | bellard | #endif
|
952 | 8393617c | Blue Swirl | switch (dc->cc_op) {
|
953 | 8393617c | Blue Swirl | case CC_OP_FLAGS:
|
954 | 8393617c | Blue Swirl | break;
|
955 | 8393617c | Blue Swirl | default:
|
956 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
957 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
958 | 8393617c | Blue Swirl | break;
|
959 | 8393617c | Blue Swirl | } |
960 | 19f329ad | blueswir1 | switch (cond) {
|
961 | 19f329ad | blueswir1 | case 0x0: |
962 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
963 | 19f329ad | blueswir1 | break;
|
964 | 19f329ad | blueswir1 | case 0x1: |
965 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
966 | 19f329ad | blueswir1 | break;
|
967 | 19f329ad | blueswir1 | case 0x2: |
968 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
969 | 19f329ad | blueswir1 | break;
|
970 | 19f329ad | blueswir1 | case 0x3: |
971 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
972 | 19f329ad | blueswir1 | break;
|
973 | 19f329ad | blueswir1 | case 0x4: |
974 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
975 | 19f329ad | blueswir1 | break;
|
976 | 19f329ad | blueswir1 | case 0x5: |
977 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
978 | 19f329ad | blueswir1 | break;
|
979 | 19f329ad | blueswir1 | case 0x6: |
980 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
981 | 19f329ad | blueswir1 | break;
|
982 | 19f329ad | blueswir1 | case 0x7: |
983 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
984 | 19f329ad | blueswir1 | break;
|
985 | 19f329ad | blueswir1 | case 0x8: |
986 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
987 | 19f329ad | blueswir1 | break;
|
988 | 19f329ad | blueswir1 | case 0x9: |
989 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
990 | 19f329ad | blueswir1 | break;
|
991 | 19f329ad | blueswir1 | case 0xa: |
992 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
993 | 19f329ad | blueswir1 | break;
|
994 | 19f329ad | blueswir1 | case 0xb: |
995 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
996 | 19f329ad | blueswir1 | break;
|
997 | 19f329ad | blueswir1 | case 0xc: |
998 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
999 | 19f329ad | blueswir1 | break;
|
1000 | 19f329ad | blueswir1 | case 0xd: |
1001 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1002 | 19f329ad | blueswir1 | break;
|
1003 | 19f329ad | blueswir1 | case 0xe: |
1004 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1005 | 19f329ad | blueswir1 | break;
|
1006 | 19f329ad | blueswir1 | case 0xf: |
1007 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1008 | 19f329ad | blueswir1 | break;
|
1009 | 19f329ad | blueswir1 | } |
1010 | 19f329ad | blueswir1 | } |
1011 | 7a3f1944 | bellard | |
1012 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1013 | e8af50a3 | bellard | { |
1014 | 19f329ad | blueswir1 | unsigned int offset; |
1015 | 19f329ad | blueswir1 | |
1016 | 19f329ad | blueswir1 | switch (cc) {
|
1017 | 19f329ad | blueswir1 | default:
|
1018 | 19f329ad | blueswir1 | case 0x0: |
1019 | 19f329ad | blueswir1 | offset = 0;
|
1020 | 19f329ad | blueswir1 | break;
|
1021 | 19f329ad | blueswir1 | case 0x1: |
1022 | 19f329ad | blueswir1 | offset = 32 - 10; |
1023 | 19f329ad | blueswir1 | break;
|
1024 | 19f329ad | blueswir1 | case 0x2: |
1025 | 19f329ad | blueswir1 | offset = 34 - 10; |
1026 | 19f329ad | blueswir1 | break;
|
1027 | 19f329ad | blueswir1 | case 0x3: |
1028 | 19f329ad | blueswir1 | offset = 36 - 10; |
1029 | 19f329ad | blueswir1 | break;
|
1030 | 19f329ad | blueswir1 | } |
1031 | 19f329ad | blueswir1 | |
1032 | 19f329ad | blueswir1 | switch (cond) {
|
1033 | 19f329ad | blueswir1 | case 0x0: |
1034 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1035 | 19f329ad | blueswir1 | break;
|
1036 | 19f329ad | blueswir1 | case 0x1: |
1037 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1038 | 19f329ad | blueswir1 | break;
|
1039 | 19f329ad | blueswir1 | case 0x2: |
1040 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1041 | 19f329ad | blueswir1 | break;
|
1042 | 19f329ad | blueswir1 | case 0x3: |
1043 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1044 | 19f329ad | blueswir1 | break;
|
1045 | 19f329ad | blueswir1 | case 0x4: |
1046 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1047 | 19f329ad | blueswir1 | break;
|
1048 | 19f329ad | blueswir1 | case 0x5: |
1049 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1050 | 19f329ad | blueswir1 | break;
|
1051 | 19f329ad | blueswir1 | case 0x6: |
1052 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1053 | 19f329ad | blueswir1 | break;
|
1054 | 19f329ad | blueswir1 | case 0x7: |
1055 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1056 | 19f329ad | blueswir1 | break;
|
1057 | 19f329ad | blueswir1 | case 0x8: |
1058 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1059 | 19f329ad | blueswir1 | break;
|
1060 | 19f329ad | blueswir1 | case 0x9: |
1061 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1062 | 19f329ad | blueswir1 | break;
|
1063 | 19f329ad | blueswir1 | case 0xa: |
1064 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1065 | 19f329ad | blueswir1 | break;
|
1066 | 19f329ad | blueswir1 | case 0xb: |
1067 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1068 | 19f329ad | blueswir1 | break;
|
1069 | 19f329ad | blueswir1 | case 0xc: |
1070 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1071 | 19f329ad | blueswir1 | break;
|
1072 | 19f329ad | blueswir1 | case 0xd: |
1073 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1074 | 19f329ad | blueswir1 | break;
|
1075 | 19f329ad | blueswir1 | case 0xe: |
1076 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1077 | 19f329ad | blueswir1 | break;
|
1078 | 19f329ad | blueswir1 | case 0xf: |
1079 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1080 | 19f329ad | blueswir1 | break;
|
1081 | 19f329ad | blueswir1 | } |
1082 | e8af50a3 | bellard | } |
1083 | 00f219bf | blueswir1 | |
1084 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1085 | 00f219bf | blueswir1 | // Inverted logic
|
1086 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1087 | 00f219bf | blueswir1 | -1,
|
1088 | 00f219bf | blueswir1 | TCG_COND_NE, |
1089 | 00f219bf | blueswir1 | TCG_COND_GT, |
1090 | 00f219bf | blueswir1 | TCG_COND_GE, |
1091 | 00f219bf | blueswir1 | -1,
|
1092 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1093 | 00f219bf | blueswir1 | TCG_COND_LE, |
1094 | 00f219bf | blueswir1 | TCG_COND_LT, |
1095 | 00f219bf | blueswir1 | }; |
1096 | 19f329ad | blueswir1 | |
1097 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1098 | 19f329ad | blueswir1 | { |
1099 | 19f329ad | blueswir1 | int l1;
|
1100 | 19f329ad | blueswir1 | |
1101 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1102 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1103 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
|
1104 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1105 | 19f329ad | blueswir1 | gen_set_label(l1); |
1106 | 19f329ad | blueswir1 | } |
1107 | 3475187d | bellard | #endif
|
1108 | cf495bcf | bellard | |
1109 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1110 | 4af984a7 | blueswir1 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1111 | 4af984a7 | blueswir1 | TCGv r_cond) |
1112 | 7a3f1944 | bellard | { |
1113 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1114 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1115 | 5fafdf24 | ths | |
1116 | cf495bcf | bellard | if (cond == 0x0) { |
1117 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1118 | 0f8a249a | blueswir1 | if (a) {
|
1119 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1120 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1121 | 0f8a249a | blueswir1 | } else {
|
1122 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1123 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1124 | 0f8a249a | blueswir1 | } |
1125 | cf495bcf | bellard | } else if (cond == 0x8) { |
1126 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1127 | 0f8a249a | blueswir1 | if (a) {
|
1128 | 0f8a249a | blueswir1 | dc->pc = target; |
1129 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1130 | 0f8a249a | blueswir1 | } else {
|
1131 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1132 | 0f8a249a | blueswir1 | dc->npc = target; |
1133 | 0f8a249a | blueswir1 | } |
1134 | cf495bcf | bellard | } else {
|
1135 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1136 | 8393617c | Blue Swirl | gen_cond(r_cond, cc, cond, dc); |
1137 | 0f8a249a | blueswir1 | if (a) {
|
1138 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1139 | cf495bcf | bellard | dc->is_br = 1;
|
1140 | 0f8a249a | blueswir1 | } else {
|
1141 | cf495bcf | bellard | dc->pc = dc->npc; |
1142 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1143 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1144 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1145 | 0f8a249a | blueswir1 | } |
1146 | cf495bcf | bellard | } |
1147 | 7a3f1944 | bellard | } |
1148 | 7a3f1944 | bellard | |
1149 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1150 | 4af984a7 | blueswir1 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1151 | 4af984a7 | blueswir1 | TCGv r_cond) |
1152 | e8af50a3 | bellard | { |
1153 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1154 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1155 | af7bf89b | bellard | |
1156 | e8af50a3 | bellard | if (cond == 0x0) { |
1157 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1158 | 0f8a249a | blueswir1 | if (a) {
|
1159 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1160 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1161 | 0f8a249a | blueswir1 | } else {
|
1162 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1163 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1164 | 0f8a249a | blueswir1 | } |
1165 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1166 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1167 | 0f8a249a | blueswir1 | if (a) {
|
1168 | 0f8a249a | blueswir1 | dc->pc = target; |
1169 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1170 | 0f8a249a | blueswir1 | } else {
|
1171 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1172 | 0f8a249a | blueswir1 | dc->npc = target; |
1173 | 0f8a249a | blueswir1 | } |
1174 | e8af50a3 | bellard | } else {
|
1175 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1176 | 4af984a7 | blueswir1 | gen_fcond(r_cond, cc, cond); |
1177 | 0f8a249a | blueswir1 | if (a) {
|
1178 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1179 | e8af50a3 | bellard | dc->is_br = 1;
|
1180 | 0f8a249a | blueswir1 | } else {
|
1181 | e8af50a3 | bellard | dc->pc = dc->npc; |
1182 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1183 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1184 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1185 | 0f8a249a | blueswir1 | } |
1186 | e8af50a3 | bellard | } |
1187 | e8af50a3 | bellard | } |
1188 | e8af50a3 | bellard | |
1189 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1190 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1191 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1192 | 4af984a7 | blueswir1 | TCGv r_cond, TCGv r_reg) |
1193 | 7a3f1944 | bellard | { |
1194 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1195 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1196 | 3475187d | bellard | |
1197 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1198 | 4af984a7 | blueswir1 | gen_cond_reg(r_cond, cond, r_reg); |
1199 | 3475187d | bellard | if (a) {
|
1200 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1201 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1202 | 3475187d | bellard | } else {
|
1203 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1204 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1205 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1206 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1207 | 3475187d | bellard | } |
1208 | 7a3f1944 | bellard | } |
1209 | 7a3f1944 | bellard | |
1210 | a7812ae4 | pbrook | static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1211 | 7e8c2b6c | blueswir1 | { |
1212 | 714547bb | blueswir1 | switch (fccno) {
|
1213 | 714547bb | blueswir1 | case 0: |
1214 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1215 | 714547bb | blueswir1 | break;
|
1216 | 714547bb | blueswir1 | case 1: |
1217 | a7812ae4 | pbrook | gen_helper_fcmps_fcc1(r_rs1, r_rs2); |
1218 | 714547bb | blueswir1 | break;
|
1219 | 714547bb | blueswir1 | case 2: |
1220 | a7812ae4 | pbrook | gen_helper_fcmps_fcc2(r_rs1, r_rs2); |
1221 | 714547bb | blueswir1 | break;
|
1222 | 714547bb | blueswir1 | case 3: |
1223 | a7812ae4 | pbrook | gen_helper_fcmps_fcc3(r_rs1, r_rs2); |
1224 | 714547bb | blueswir1 | break;
|
1225 | 714547bb | blueswir1 | } |
1226 | 7e8c2b6c | blueswir1 | } |
1227 | 7e8c2b6c | blueswir1 | |
1228 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1229 | 7e8c2b6c | blueswir1 | { |
1230 | a7812ae4 | pbrook | switch (fccno) {
|
1231 | a7812ae4 | pbrook | case 0: |
1232 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1233 | a7812ae4 | pbrook | break;
|
1234 | a7812ae4 | pbrook | case 1: |
1235 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc1(); |
1236 | a7812ae4 | pbrook | break;
|
1237 | a7812ae4 | pbrook | case 2: |
1238 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc2(); |
1239 | a7812ae4 | pbrook | break;
|
1240 | a7812ae4 | pbrook | case 3: |
1241 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc3(); |
1242 | a7812ae4 | pbrook | break;
|
1243 | a7812ae4 | pbrook | } |
1244 | 7e8c2b6c | blueswir1 | } |
1245 | 7e8c2b6c | blueswir1 | |
1246 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1247 | 7e8c2b6c | blueswir1 | { |
1248 | a7812ae4 | pbrook | switch (fccno) {
|
1249 | a7812ae4 | pbrook | case 0: |
1250 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1251 | a7812ae4 | pbrook | break;
|
1252 | a7812ae4 | pbrook | case 1: |
1253 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc1(); |
1254 | a7812ae4 | pbrook | break;
|
1255 | a7812ae4 | pbrook | case 2: |
1256 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc2(); |
1257 | a7812ae4 | pbrook | break;
|
1258 | a7812ae4 | pbrook | case 3: |
1259 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc3(); |
1260 | a7812ae4 | pbrook | break;
|
1261 | a7812ae4 | pbrook | } |
1262 | 7e8c2b6c | blueswir1 | } |
1263 | 7e8c2b6c | blueswir1 | |
1264 | a7812ae4 | pbrook | static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1265 | 7e8c2b6c | blueswir1 | { |
1266 | 714547bb | blueswir1 | switch (fccno) {
|
1267 | 714547bb | blueswir1 | case 0: |
1268 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1269 | 714547bb | blueswir1 | break;
|
1270 | 714547bb | blueswir1 | case 1: |
1271 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc1(r_rs1, r_rs2); |
1272 | 714547bb | blueswir1 | break;
|
1273 | 714547bb | blueswir1 | case 2: |
1274 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc2(r_rs1, r_rs2); |
1275 | 714547bb | blueswir1 | break;
|
1276 | 714547bb | blueswir1 | case 3: |
1277 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc3(r_rs1, r_rs2); |
1278 | 714547bb | blueswir1 | break;
|
1279 | 714547bb | blueswir1 | } |
1280 | 7e8c2b6c | blueswir1 | } |
1281 | 7e8c2b6c | blueswir1 | |
1282 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1283 | 7e8c2b6c | blueswir1 | { |
1284 | a7812ae4 | pbrook | switch (fccno) {
|
1285 | a7812ae4 | pbrook | case 0: |
1286 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1287 | a7812ae4 | pbrook | break;
|
1288 | a7812ae4 | pbrook | case 1: |
1289 | a7812ae4 | pbrook | gen_helper_fcmped_fcc1(); |
1290 | a7812ae4 | pbrook | break;
|
1291 | a7812ae4 | pbrook | case 2: |
1292 | a7812ae4 | pbrook | gen_helper_fcmped_fcc2(); |
1293 | a7812ae4 | pbrook | break;
|
1294 | a7812ae4 | pbrook | case 3: |
1295 | a7812ae4 | pbrook | gen_helper_fcmped_fcc3(); |
1296 | a7812ae4 | pbrook | break;
|
1297 | a7812ae4 | pbrook | } |
1298 | 7e8c2b6c | blueswir1 | } |
1299 | 7e8c2b6c | blueswir1 | |
1300 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1301 | 7e8c2b6c | blueswir1 | { |
1302 | a7812ae4 | pbrook | switch (fccno) {
|
1303 | a7812ae4 | pbrook | case 0: |
1304 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1305 | a7812ae4 | pbrook | break;
|
1306 | a7812ae4 | pbrook | case 1: |
1307 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc1(); |
1308 | a7812ae4 | pbrook | break;
|
1309 | a7812ae4 | pbrook | case 2: |
1310 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc2(); |
1311 | a7812ae4 | pbrook | break;
|
1312 | a7812ae4 | pbrook | case 3: |
1313 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc3(); |
1314 | a7812ae4 | pbrook | break;
|
1315 | a7812ae4 | pbrook | } |
1316 | 7e8c2b6c | blueswir1 | } |
1317 | 7e8c2b6c | blueswir1 | |
1318 | 7e8c2b6c | blueswir1 | #else
|
1319 | 7e8c2b6c | blueswir1 | |
1320 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1321 | 7e8c2b6c | blueswir1 | { |
1322 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1323 | 7e8c2b6c | blueswir1 | } |
1324 | 7e8c2b6c | blueswir1 | |
1325 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1326 | 7e8c2b6c | blueswir1 | { |
1327 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1328 | 7e8c2b6c | blueswir1 | } |
1329 | 7e8c2b6c | blueswir1 | |
1330 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1331 | 7e8c2b6c | blueswir1 | { |
1332 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1333 | 7e8c2b6c | blueswir1 | } |
1334 | 7e8c2b6c | blueswir1 | |
1335 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1336 | 7e8c2b6c | blueswir1 | { |
1337 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1338 | 7e8c2b6c | blueswir1 | } |
1339 | 7e8c2b6c | blueswir1 | |
1340 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1341 | 7e8c2b6c | blueswir1 | { |
1342 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1343 | 7e8c2b6c | blueswir1 | } |
1344 | 7e8c2b6c | blueswir1 | |
1345 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1346 | 7e8c2b6c | blueswir1 | { |
1347 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1348 | 7e8c2b6c | blueswir1 | } |
1349 | 7e8c2b6c | blueswir1 | #endif
|
1350 | 7e8c2b6c | blueswir1 | |
1351 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1352 | 134d77a1 | blueswir1 | { |
1353 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1354 | 2ea815ca | blueswir1 | |
1355 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
1356 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1357 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1358 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1359 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1360 | 134d77a1 | blueswir1 | } |
1361 | 134d77a1 | blueswir1 | |
1362 | 4af984a7 | blueswir1 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
1363 | a80dde08 | bellard | { |
1364 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1365 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1366 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1367 | 2ea815ca | blueswir1 | |
1368 | 4af984a7 | blueswir1 | save_state(dc, r_cond); |
1369 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1370 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1371 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1372 | a80dde08 | bellard | dc->is_br = 1;
|
1373 | a80dde08 | bellard | return 1; |
1374 | a80dde08 | bellard | } |
1375 | a80dde08 | bellard | #endif
|
1376 | a80dde08 | bellard | return 0; |
1377 | a80dde08 | bellard | } |
1378 | a80dde08 | bellard | |
1379 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1380 | 7e8c2b6c | blueswir1 | { |
1381 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
1382 | 7e8c2b6c | blueswir1 | } |
1383 | 7e8c2b6c | blueswir1 | |
1384 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1385 | 7e8c2b6c | blueswir1 | { |
1386 | a7812ae4 | pbrook | gen_helper_clear_float_exceptions(); |
1387 | 7e8c2b6c | blueswir1 | } |
1388 | 7e8c2b6c | blueswir1 | |
1389 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1390 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1391 | a7812ae4 | pbrook | static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr) |
1392 | 1a2fb1c0 | blueswir1 | { |
1393 | 95f9397c | blueswir1 | int asi;
|
1394 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1395 | 1a2fb1c0 | blueswir1 | |
1396 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1397 | a7812ae4 | pbrook | r_asi = tcg_temp_new_i32(); |
1398 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(r_asi, cpu_asi); |
1399 | 1a2fb1c0 | blueswir1 | } else {
|
1400 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1401 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1402 | 1a2fb1c0 | blueswir1 | } |
1403 | 0425bee5 | blueswir1 | return r_asi;
|
1404 | 0425bee5 | blueswir1 | } |
1405 | 0425bee5 | blueswir1 | |
1406 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1407 | 77f193da | blueswir1 | int sign)
|
1408 | 0425bee5 | blueswir1 | { |
1409 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1410 | 0425bee5 | blueswir1 | |
1411 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1412 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1413 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1414 | a7812ae4 | pbrook | gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign); |
1415 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1416 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1417 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1418 | 1a2fb1c0 | blueswir1 | } |
1419 | 1a2fb1c0 | blueswir1 | |
1420 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1421 | 1a2fb1c0 | blueswir1 | { |
1422 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1423 | 1a2fb1c0 | blueswir1 | |
1424 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1425 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1426 | a7812ae4 | pbrook | gen_helper_st_asi(addr, src, r_asi, r_size); |
1427 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1428 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1429 | 1a2fb1c0 | blueswir1 | } |
1430 | 1a2fb1c0 | blueswir1 | |
1431 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1432 | 1a2fb1c0 | blueswir1 | { |
1433 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1434 | 1a2fb1c0 | blueswir1 | |
1435 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1436 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1437 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1438 | a7812ae4 | pbrook | gen_helper_ldf_asi(addr, r_asi, r_size, r_rd); |
1439 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1440 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1441 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1442 | 1a2fb1c0 | blueswir1 | } |
1443 | 1a2fb1c0 | blueswir1 | |
1444 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1445 | 1a2fb1c0 | blueswir1 | { |
1446 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1447 | 1a2fb1c0 | blueswir1 | |
1448 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1449 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1450 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1451 | a7812ae4 | pbrook | gen_helper_stf_asi(addr, r_asi, r_size, r_rd); |
1452 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1453 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1454 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1455 | 1a2fb1c0 | blueswir1 | } |
1456 | 1a2fb1c0 | blueswir1 | |
1457 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1458 | 1a2fb1c0 | blueswir1 | { |
1459 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1460 | 1a2fb1c0 | blueswir1 | |
1461 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1462 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1463 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1464 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1465 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1466 | a7812ae4 | pbrook | gen_helper_st_asi(addr, dst, r_asi, r_size); |
1467 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1468 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1469 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1470 | 1a2fb1c0 | blueswir1 | } |
1471 | 1a2fb1c0 | blueswir1 | |
1472 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1473 | 1a2fb1c0 | blueswir1 | { |
1474 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_rd; |
1475 | 1a2fb1c0 | blueswir1 | |
1476 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1477 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
1478 | a7812ae4 | pbrook | gen_helper_ldda_asi(addr, r_asi, r_rd); |
1479 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1480 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1481 | 0425bee5 | blueswir1 | } |
1482 | 0425bee5 | blueswir1 | |
1483 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1484 | 0425bee5 | blueswir1 | { |
1485 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1486 | a7ec4229 | blueswir1 | |
1487 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1488 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1489 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1490 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1491 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1492 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1493 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1494 | 1a2fb1c0 | blueswir1 | } |
1495 | 1a2fb1c0 | blueswir1 | |
1496 | 77f193da | blueswir1 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1497 | 77f193da | blueswir1 | int rd)
|
1498 | 1a2fb1c0 | blueswir1 | { |
1499 | a7812ae4 | pbrook | TCGv r_val1; |
1500 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1501 | 1a2fb1c0 | blueswir1 | |
1502 | a7812ae4 | pbrook | r_val1 = tcg_temp_new(); |
1503 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1504 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1505 | a7812ae4 | pbrook | gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi); |
1506 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1507 | 2ea815ca | blueswir1 | tcg_temp_free(r_val1); |
1508 | 1a2fb1c0 | blueswir1 | } |
1509 | 1a2fb1c0 | blueswir1 | |
1510 | 77f193da | blueswir1 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1511 | 77f193da | blueswir1 | int rd)
|
1512 | 1a2fb1c0 | blueswir1 | { |
1513 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1514 | 1a2fb1c0 | blueswir1 | |
1515 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1516 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1517 | a7812ae4 | pbrook | gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi); |
1518 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1519 | 1a2fb1c0 | blueswir1 | } |
1520 | 1a2fb1c0 | blueswir1 | |
1521 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1522 | 1a2fb1c0 | blueswir1 | |
1523 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1524 | 77f193da | blueswir1 | int sign)
|
1525 | 1a2fb1c0 | blueswir1 | { |
1526 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1527 | 1a2fb1c0 | blueswir1 | |
1528 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1529 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1530 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1531 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1532 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1533 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1534 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1535 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1536 | 1a2fb1c0 | blueswir1 | } |
1537 | 1a2fb1c0 | blueswir1 | |
1538 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1539 | 1a2fb1c0 | blueswir1 | { |
1540 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1541 | 1a2fb1c0 | blueswir1 | |
1542 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1543 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1544 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1545 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1546 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1547 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1548 | 1a2fb1c0 | blueswir1 | } |
1549 | 1a2fb1c0 | blueswir1 | |
1550 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1551 | 1a2fb1c0 | blueswir1 | { |
1552 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1553 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1554 | 1a2fb1c0 | blueswir1 | |
1555 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1556 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1557 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1558 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1559 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1560 | a7812ae4 | pbrook | r_val = tcg_temp_new_i64(); |
1561 | a7812ae4 | pbrook | tcg_gen_extu_tl_i64(r_val, dst); |
1562 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1563 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1564 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1565 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1566 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1567 | 1a2fb1c0 | blueswir1 | } |
1568 | 1a2fb1c0 | blueswir1 | |
1569 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1570 | 1a2fb1c0 | blueswir1 | { |
1571 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1572 | 1a2fb1c0 | blueswir1 | |
1573 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1574 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1575 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1576 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1577 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1578 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1579 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1580 | db166940 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1581 | db166940 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
1582 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1583 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
1584 | db166940 | blueswir1 | gen_movl_TN_reg(rd, hi); |
1585 | 0425bee5 | blueswir1 | } |
1586 | 0425bee5 | blueswir1 | |
1587 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1588 | 0425bee5 | blueswir1 | { |
1589 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1590 | a7ec4229 | blueswir1 | |
1591 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1592 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1593 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1594 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1595 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1596 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1597 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1598 | 1a2fb1c0 | blueswir1 | } |
1599 | 1a2fb1c0 | blueswir1 | #endif
|
1600 | 1a2fb1c0 | blueswir1 | |
1601 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1602 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1603 | 1a2fb1c0 | blueswir1 | { |
1604 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1605 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1606 | 1a2fb1c0 | blueswir1 | |
1607 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
1608 | 1a2fb1c0 | blueswir1 | |
1609 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
1610 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1611 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
1612 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1613 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1614 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1615 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1616 | 1a2fb1c0 | blueswir1 | } |
1617 | 1a2fb1c0 | blueswir1 | #endif
|
1618 | 1a2fb1c0 | blueswir1 | |
1619 | 9322a4bf | blueswir1 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1620 | 9322a4bf | blueswir1 | { |
1621 | 9322a4bf | blueswir1 | TCGv r_rs1 = def; |
1622 | 9322a4bf | blueswir1 | unsigned int rs1; |
1623 | 9322a4bf | blueswir1 | |
1624 | 9322a4bf | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1625 | 9322a4bf | blueswir1 | if (rs1 == 0) |
1626 | 5c6a0628 | blueswir1 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
1627 | 9322a4bf | blueswir1 | else if (rs1 < 8) |
1628 | 5c6a0628 | blueswir1 | r_rs1 = cpu_gregs[rs1]; |
1629 | 9322a4bf | blueswir1 | else
|
1630 | 9322a4bf | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
1631 | 9322a4bf | blueswir1 | return r_rs1;
|
1632 | 9322a4bf | blueswir1 | } |
1633 | 9322a4bf | blueswir1 | |
1634 | a49d9390 | blueswir1 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1635 | a49d9390 | blueswir1 | { |
1636 | a49d9390 | blueswir1 | TCGv r_rs2 = def; |
1637 | a49d9390 | blueswir1 | |
1638 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
1639 | 67526b20 | Blue Swirl | target_long simm; |
1640 | 67526b20 | Blue Swirl | |
1641 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
1642 | 67526b20 | Blue Swirl | r_rs2 = tcg_const_tl(simm); // XXX how to free?
|
1643 | a49d9390 | blueswir1 | } else { /* register */ |
1644 | 67526b20 | Blue Swirl | unsigned int rs2; |
1645 | 67526b20 | Blue Swirl | |
1646 | a49d9390 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1647 | a49d9390 | blueswir1 | if (rs2 == 0) |
1648 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
1649 | a49d9390 | blueswir1 | else if (rs2 < 8) |
1650 | a49d9390 | blueswir1 | r_rs2 = cpu_gregs[rs2]; |
1651 | a49d9390 | blueswir1 | else
|
1652 | a49d9390 | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); |
1653 | a49d9390 | blueswir1 | } |
1654 | a49d9390 | blueswir1 | return r_rs2;
|
1655 | a49d9390 | blueswir1 | } |
1656 | a49d9390 | blueswir1 | |
1657 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
1658 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1659 | 64a88d5d | blueswir1 | goto illegal_insn;
|
1660 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
1661 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1662 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
1663 | 64a88d5d | blueswir1 | |
1664 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1665 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1666 | cf495bcf | bellard | { |
1667 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1668 | 67526b20 | Blue Swirl | target_long simm; |
1669 | 7a3f1944 | bellard | |
1670 | 8fec2b8c | aliguori | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
1671 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
1672 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1673 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1674 | 7a3f1944 | bellard | |
1675 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1676 | 6ae20372 | blueswir1 | |
1677 | a7812ae4 | pbrook | cpu_src1 = tcg_temp_new(); // const
|
1678 | a7812ae4 | pbrook | cpu_src2 = tcg_temp_new(); // const
|
1679 | 6ae20372 | blueswir1 | |
1680 | cf495bcf | bellard | switch (opc) {
|
1681 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1682 | 0f8a249a | blueswir1 | { |
1683 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1684 | 0f8a249a | blueswir1 | int32_t target; |
1685 | 0f8a249a | blueswir1 | switch (xop) {
|
1686 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1687 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1688 | 0f8a249a | blueswir1 | { |
1689 | 0f8a249a | blueswir1 | int cc;
|
1690 | 0f8a249a | blueswir1 | |
1691 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1692 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1693 | 0f8a249a | blueswir1 | target <<= 2;
|
1694 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1695 | 0f8a249a | blueswir1 | if (cc == 0) |
1696 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1697 | 0f8a249a | blueswir1 | else if (cc == 2) |
1698 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 1, cpu_cond);
|
1699 | 0f8a249a | blueswir1 | else
|
1700 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1701 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1702 | 0f8a249a | blueswir1 | } |
1703 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1704 | 0f8a249a | blueswir1 | { |
1705 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1706 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1707 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1708 | 0f8a249a | blueswir1 | target <<= 2;
|
1709 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1710 | 6ae20372 | blueswir1 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
1711 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1712 | 0f8a249a | blueswir1 | } |
1713 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1714 | 0f8a249a | blueswir1 | { |
1715 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1716 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1717 | a80dde08 | bellard | goto jmp_insn;
|
1718 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1719 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1720 | 0f8a249a | blueswir1 | target <<= 2;
|
1721 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, cc, cpu_cond); |
1722 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1723 | 0f8a249a | blueswir1 | } |
1724 | a4d17f19 | blueswir1 | #else
|
1725 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1726 | 0f8a249a | blueswir1 | { |
1727 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1728 | 0f8a249a | blueswir1 | } |
1729 | 0f8a249a | blueswir1 | #endif
|
1730 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1731 | 0f8a249a | blueswir1 | { |
1732 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1733 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1734 | 0f8a249a | blueswir1 | target <<= 2;
|
1735 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1736 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1737 | 0f8a249a | blueswir1 | } |
1738 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1739 | 0f8a249a | blueswir1 | { |
1740 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1741 | a80dde08 | bellard | goto jmp_insn;
|
1742 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1743 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1744 | 0f8a249a | blueswir1 | target <<= 2;
|
1745 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, 0, cpu_cond);
|
1746 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1747 | 0f8a249a | blueswir1 | } |
1748 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1749 | 0f8a249a | blueswir1 | if (rd) { // nop |
1750 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1751 | 2ea815ca | blueswir1 | TCGv r_const; |
1752 | 2ea815ca | blueswir1 | |
1753 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(value << 10);
|
1754 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1755 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1756 | 0f8a249a | blueswir1 | } |
1757 | 0f8a249a | blueswir1 | break;
|
1758 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1759 | 0f8a249a | blueswir1 | default:
|
1760 | 3475187d | bellard | goto illegal_insn;
|
1761 | 0f8a249a | blueswir1 | } |
1762 | 0f8a249a | blueswir1 | break;
|
1763 | 0f8a249a | blueswir1 | } |
1764 | 0f8a249a | blueswir1 | break;
|
1765 | dc1a6971 | Blue Swirl | case 1: /*CALL*/ |
1766 | dc1a6971 | Blue Swirl | { |
1767 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
1768 | 2ea815ca | blueswir1 | TCGv r_const; |
1769 | cf495bcf | bellard | |
1770 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
1771 | 2ea815ca | blueswir1 | gen_movl_TN_reg(15, r_const);
|
1772 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1773 | 0f8a249a | blueswir1 | target += dc->pc; |
1774 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
1775 | 0f8a249a | blueswir1 | dc->npc = target; |
1776 | 0f8a249a | blueswir1 | } |
1777 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1778 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
1779 | 0f8a249a | blueswir1 | { |
1780 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
1781 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
1782 | cf495bcf | bellard | int cond;
|
1783 | 3475187d | bellard | |
1784 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1785 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
1786 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
1787 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
1788 | cf495bcf | bellard | } else {
|
1789 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
1790 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
1791 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
1792 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
1793 | 6f551262 | blueswir1 | } else
|
1794 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
1795 | cf495bcf | bellard | } |
1796 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
1797 | cf495bcf | bellard | if (cond == 0x8) { |
1798 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1799 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
1800 | b158a785 | blueswir1 | supervisor(dc)) |
1801 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
1802 | b158a785 | blueswir1 | else
|
1803 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
1804 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
1805 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
1806 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
1807 | af7bf89b | bellard | } else if (cond != 0) { |
1808 | a7812ae4 | pbrook | TCGv r_cond = tcg_temp_new(); |
1809 | b158a785 | blueswir1 | int l1;
|
1810 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1811 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
1812 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
1813 | 748b9d8e | blueswir1 | |
1814 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1815 | 0f8a249a | blueswir1 | if (cc == 0) |
1816 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
1817 | 0f8a249a | blueswir1 | else if (cc == 2) |
1818 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
1819 | 0f8a249a | blueswir1 | else
|
1820 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1821 | 3475187d | bellard | #else
|
1822 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1823 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
1824 | 3475187d | bellard | #endif
|
1825 | b158a785 | blueswir1 | l1 = gen_new_label(); |
1826 | b158a785 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1827 | b158a785 | blueswir1 | |
1828 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
1829 | b158a785 | blueswir1 | supervisor(dc)) |
1830 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
1831 | b158a785 | blueswir1 | else
|
1832 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
1833 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
1834 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
1835 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
1836 | b158a785 | blueswir1 | |
1837 | b158a785 | blueswir1 | gen_set_label(l1); |
1838 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
1839 | cf495bcf | bellard | } |
1840 | a80dde08 | bellard | gen_op_next_insn(); |
1841 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1842 | a80dde08 | bellard | dc->is_br = 1;
|
1843 | a80dde08 | bellard | goto jmp_insn;
|
1844 | cf495bcf | bellard | } else if (xop == 0x28) { |
1845 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1846 | cf495bcf | bellard | switch(rs1) {
|
1847 | cf495bcf | bellard | case 0: /* rdy */ |
1848 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
1849 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
1850 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
1851 | 65fe7b09 | blueswir1 | II */
|
1852 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
1853 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
1854 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
1855 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
1856 | 65fe7b09 | blueswir1 | microSPARC II */
|
1857 | 65fe7b09 | blueswir1 | #endif
|
1858 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_y); |
1859 | cf495bcf | bellard | break;
|
1860 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1861 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
1862 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1863 | a7812ae4 | pbrook | gen_helper_rdccr(cpu_dst); |
1864 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1865 | 3475187d | bellard | break;
|
1866 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
1867 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
1868 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1869 | 3475187d | bellard | break;
|
1870 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
1871 | ccd4a219 | blueswir1 | { |
1872 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
1873 | ccd4a219 | blueswir1 | |
1874 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
1875 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
1876 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
1877 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
1878 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
1879 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1880 | ccd4a219 | blueswir1 | } |
1881 | 3475187d | bellard | break;
|
1882 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
1883 | 2ea815ca | blueswir1 | { |
1884 | 2ea815ca | blueswir1 | TCGv r_const; |
1885 | 2ea815ca | blueswir1 | |
1886 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
1887 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1888 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1889 | 2ea815ca | blueswir1 | } |
1890 | 0f8a249a | blueswir1 | break;
|
1891 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
1892 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
1893 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1894 | 3475187d | bellard | break;
|
1895 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
1896 | 65fe7b09 | blueswir1 | break; /* no effect */ |
1897 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
1898 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1899 | 725cb90b | bellard | goto jmp_insn;
|
1900 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_gsr); |
1901 | 725cb90b | bellard | break;
|
1902 | 9d926598 | blueswir1 | case 0x16: /* Softint */ |
1903 | 9d926598 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_softint); |
1904 | 9d926598 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1905 | 9d926598 | blueswir1 | break;
|
1906 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
1907 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tick_cmpr); |
1908 | 83469015 | bellard | break;
|
1909 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
1910 | ccd4a219 | blueswir1 | { |
1911 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
1912 | ccd4a219 | blueswir1 | |
1913 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
1914 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
1915 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
1916 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
1917 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
1918 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1919 | ccd4a219 | blueswir1 | } |
1920 | 83469015 | bellard | break;
|
1921 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
1922 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_stick_cmpr); |
1923 | 83469015 | bellard | break;
|
1924 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
1925 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
1926 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
1927 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
1928 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
1929 | 3475187d | bellard | #endif
|
1930 | 3475187d | bellard | default:
|
1931 | cf495bcf | bellard | goto illegal_insn;
|
1932 | cf495bcf | bellard | } |
1933 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1934 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
1935 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
1936 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
1937 | 0f8a249a | blueswir1 | goto priv_insn;
|
1938 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1939 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1940 | a7812ae4 | pbrook | gen_helper_rdpsr(cpu_dst); |
1941 | e9ebed4d | blueswir1 | #else
|
1942 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
1943 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
1944 | e9ebed4d | blueswir1 | goto priv_insn;
|
1945 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1946 | e9ebed4d | blueswir1 | switch (rs1) {
|
1947 | e9ebed4d | blueswir1 | case 0: // hpstate |
1948 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
1949 | e9ebed4d | blueswir1 | break;
|
1950 | e9ebed4d | blueswir1 | case 1: // htstate |
1951 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
1952 | e9ebed4d | blueswir1 | break;
|
1953 | e9ebed4d | blueswir1 | case 3: // hintp |
1954 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
1955 | e9ebed4d | blueswir1 | break;
|
1956 | e9ebed4d | blueswir1 | case 5: // htba |
1957 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
1958 | e9ebed4d | blueswir1 | break;
|
1959 | e9ebed4d | blueswir1 | case 6: // hver |
1960 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
1961 | e9ebed4d | blueswir1 | break;
|
1962 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
1963 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
1964 | e9ebed4d | blueswir1 | break;
|
1965 | e9ebed4d | blueswir1 | default:
|
1966 | e9ebed4d | blueswir1 | goto illegal_insn;
|
1967 | e9ebed4d | blueswir1 | } |
1968 | e9ebed4d | blueswir1 | #endif
|
1969 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1970 | e8af50a3 | bellard | break;
|
1971 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
1972 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
1973 | 0f8a249a | blueswir1 | goto priv_insn;
|
1974 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1975 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1976 | 0f8a249a | blueswir1 | switch (rs1) {
|
1977 | 0f8a249a | blueswir1 | case 0: // tpc |
1978 | 375ee38b | blueswir1 | { |
1979 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
1980 | 375ee38b | blueswir1 | |
1981 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
1982 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
1983 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
1984 | a7812ae4 | pbrook | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
1985 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
1986 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
1987 | 375ee38b | blueswir1 | } |
1988 | 0f8a249a | blueswir1 | break;
|
1989 | 0f8a249a | blueswir1 | case 1: // tnpc |
1990 | 375ee38b | blueswir1 | { |
1991 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
1992 | 375ee38b | blueswir1 | |
1993 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
1994 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
1995 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
1996 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
1997 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
1998 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
1999 | 375ee38b | blueswir1 | } |
2000 | 0f8a249a | blueswir1 | break;
|
2001 | 0f8a249a | blueswir1 | case 2: // tstate |
2002 | 375ee38b | blueswir1 | { |
2003 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2004 | 375ee38b | blueswir1 | |
2005 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2006 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2007 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2008 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2009 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2010 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2011 | 375ee38b | blueswir1 | } |
2012 | 0f8a249a | blueswir1 | break;
|
2013 | 0f8a249a | blueswir1 | case 3: // tt |
2014 | 375ee38b | blueswir1 | { |
2015 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2016 | 375ee38b | blueswir1 | |
2017 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2018 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2019 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2020 | a7812ae4 | pbrook | tcg_gen_ld_i32(cpu_tmp32, r_tsptr, |
2021 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2022 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2023 | a7812ae4 | pbrook | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2024 | 375ee38b | blueswir1 | } |
2025 | 0f8a249a | blueswir1 | break;
|
2026 | 0f8a249a | blueswir1 | case 4: // tick |
2027 | ccd4a219 | blueswir1 | { |
2028 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2029 | ccd4a219 | blueswir1 | |
2030 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2031 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2032 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2033 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_tmp0, r_tickptr); |
2034 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2035 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2036 | ccd4a219 | blueswir1 | } |
2037 | 0f8a249a | blueswir1 | break;
|
2038 | 0f8a249a | blueswir1 | case 5: // tba |
2039 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
2040 | 0f8a249a | blueswir1 | break;
|
2041 | 0f8a249a | blueswir1 | case 6: // pstate |
2042 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2043 | 77f193da | blueswir1 | offsetof(CPUSPARCState, pstate)); |
2044 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2045 | 0f8a249a | blueswir1 | break;
|
2046 | 0f8a249a | blueswir1 | case 7: // tl |
2047 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2048 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
2049 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2050 | 0f8a249a | blueswir1 | break;
|
2051 | 0f8a249a | blueswir1 | case 8: // pil |
2052 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2053 | 77f193da | blueswir1 | offsetof(CPUSPARCState, psrpil)); |
2054 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2055 | 0f8a249a | blueswir1 | break;
|
2056 | 0f8a249a | blueswir1 | case 9: // cwp |
2057 | a7812ae4 | pbrook | gen_helper_rdcwp(cpu_tmp0); |
2058 | 0f8a249a | blueswir1 | break;
|
2059 | 0f8a249a | blueswir1 | case 10: // cansave |
2060 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2061 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cansave)); |
2062 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2063 | 0f8a249a | blueswir1 | break;
|
2064 | 0f8a249a | blueswir1 | case 11: // canrestore |
2065 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2066 | 77f193da | blueswir1 | offsetof(CPUSPARCState, canrestore)); |
2067 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2068 | 0f8a249a | blueswir1 | break;
|
2069 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2070 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2071 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cleanwin)); |
2072 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2073 | 0f8a249a | blueswir1 | break;
|
2074 | 0f8a249a | blueswir1 | case 13: // otherwin |
2075 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2076 | 77f193da | blueswir1 | offsetof(CPUSPARCState, otherwin)); |
2077 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2078 | 0f8a249a | blueswir1 | break;
|
2079 | 0f8a249a | blueswir1 | case 14: // wstate |
2080 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2081 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wstate)); |
2082 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2083 | 0f8a249a | blueswir1 | break;
|
2084 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2085 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2086 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2087 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
2088 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2089 | e9ebed4d | blueswir1 | break;
|
2090 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2091 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2092 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2093 | e9ebed4d | blueswir1 | goto priv_insn;
|
2094 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); |
2095 | e9ebed4d | blueswir1 | break;
|
2096 | 0f8a249a | blueswir1 | case 31: // ver |
2097 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
2098 | 0f8a249a | blueswir1 | break;
|
2099 | 0f8a249a | blueswir1 | case 15: // fq |
2100 | 0f8a249a | blueswir1 | default:
|
2101 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2102 | 0f8a249a | blueswir1 | } |
2103 | 3475187d | bellard | #else
|
2104 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
2105 | 3475187d | bellard | #endif
|
2106 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2107 | e8af50a3 | bellard | break;
|
2108 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2109 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2110 | c5f2f668 | blueswir1 | save_state(dc, cpu_cond); |
2111 | a7812ae4 | pbrook | gen_helper_flushw(); |
2112 | 3475187d | bellard | #else
|
2113 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2114 | 0f8a249a | blueswir1 | goto priv_insn;
|
2115 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tbr); |
2116 | 3475187d | bellard | #endif
|
2117 | e8af50a3 | bellard | break;
|
2118 | e8af50a3 | bellard | #endif
|
2119 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2120 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2121 | a80dde08 | bellard | goto jmp_insn;
|
2122 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2123 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2124 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2125 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2126 | 0f8a249a | blueswir1 | switch (xop) {
|
2127 | dc1a6971 | Blue Swirl | case 0x1: /* fmovs */ |
2128 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2129 | dc1a6971 | Blue Swirl | break;
|
2130 | dc1a6971 | Blue Swirl | case 0x5: /* fnegs */ |
2131 | dc1a6971 | Blue Swirl | gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); |
2132 | dc1a6971 | Blue Swirl | break;
|
2133 | dc1a6971 | Blue Swirl | case 0x9: /* fabss */ |
2134 | dc1a6971 | Blue Swirl | gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); |
2135 | dc1a6971 | Blue Swirl | break;
|
2136 | dc1a6971 | Blue Swirl | case 0x29: /* fsqrts */ |
2137 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2138 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2139 | dc1a6971 | Blue Swirl | gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
2140 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2141 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2142 | dc1a6971 | Blue Swirl | break;
|
2143 | dc1a6971 | Blue Swirl | case 0x2a: /* fsqrtd */ |
2144 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2145 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2146 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2147 | dc1a6971 | Blue Swirl | gen_helper_fsqrtd(); |
2148 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2149 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2150 | dc1a6971 | Blue Swirl | break;
|
2151 | dc1a6971 | Blue Swirl | case 0x2b: /* fsqrtq */ |
2152 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2153 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2154 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2155 | dc1a6971 | Blue Swirl | gen_helper_fsqrtq(); |
2156 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2157 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2158 | dc1a6971 | Blue Swirl | break;
|
2159 | dc1a6971 | Blue Swirl | case 0x41: /* fadds */ |
2160 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2161 | dc1a6971 | Blue Swirl | gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2162 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2163 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2164 | dc1a6971 | Blue Swirl | break;
|
2165 | dc1a6971 | Blue Swirl | case 0x42: /* faddd */ |
2166 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2167 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2168 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2169 | dc1a6971 | Blue Swirl | gen_helper_faddd(); |
2170 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2171 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2172 | dc1a6971 | Blue Swirl | break;
|
2173 | dc1a6971 | Blue Swirl | case 0x43: /* faddq */ |
2174 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2175 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2176 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2177 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2178 | dc1a6971 | Blue Swirl | gen_helper_faddq(); |
2179 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2180 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2181 | dc1a6971 | Blue Swirl | break;
|
2182 | dc1a6971 | Blue Swirl | case 0x45: /* fsubs */ |
2183 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2184 | dc1a6971 | Blue Swirl | gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2185 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2186 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2187 | dc1a6971 | Blue Swirl | break;
|
2188 | dc1a6971 | Blue Swirl | case 0x46: /* fsubd */ |
2189 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2190 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2191 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2192 | dc1a6971 | Blue Swirl | gen_helper_fsubd(); |
2193 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2194 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2195 | dc1a6971 | Blue Swirl | break;
|
2196 | dc1a6971 | Blue Swirl | case 0x47: /* fsubq */ |
2197 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2198 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2199 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2200 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2201 | dc1a6971 | Blue Swirl | gen_helper_fsubq(); |
2202 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2203 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2204 | dc1a6971 | Blue Swirl | break;
|
2205 | dc1a6971 | Blue Swirl | case 0x49: /* fmuls */ |
2206 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2207 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2208 | dc1a6971 | Blue Swirl | gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2209 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2210 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2211 | dc1a6971 | Blue Swirl | break;
|
2212 | dc1a6971 | Blue Swirl | case 0x4a: /* fmuld */ |
2213 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2214 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2215 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2216 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2217 | dc1a6971 | Blue Swirl | gen_helper_fmuld(); |
2218 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2219 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2220 | dc1a6971 | Blue Swirl | break;
|
2221 | dc1a6971 | Blue Swirl | case 0x4b: /* fmulq */ |
2222 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2223 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2224 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2225 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2226 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2227 | dc1a6971 | Blue Swirl | gen_helper_fmulq(); |
2228 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2229 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2230 | dc1a6971 | Blue Swirl | break;
|
2231 | dc1a6971 | Blue Swirl | case 0x4d: /* fdivs */ |
2232 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2233 | dc1a6971 | Blue Swirl | gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2234 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2235 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2236 | dc1a6971 | Blue Swirl | break;
|
2237 | dc1a6971 | Blue Swirl | case 0x4e: /* fdivd */ |
2238 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2239 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2240 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2241 | dc1a6971 | Blue Swirl | gen_helper_fdivd(); |
2242 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2243 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2244 | dc1a6971 | Blue Swirl | break;
|
2245 | dc1a6971 | Blue Swirl | case 0x4f: /* fdivq */ |
2246 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2247 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2248 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2249 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2250 | dc1a6971 | Blue Swirl | gen_helper_fdivq(); |
2251 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2252 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2253 | dc1a6971 | Blue Swirl | break;
|
2254 | dc1a6971 | Blue Swirl | case 0x69: /* fsmuld */ |
2255 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSMULD); |
2256 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2257 | dc1a6971 | Blue Swirl | gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
2258 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2259 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2260 | dc1a6971 | Blue Swirl | break;
|
2261 | dc1a6971 | Blue Swirl | case 0x6e: /* fdmulq */ |
2262 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2263 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2264 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2265 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2266 | dc1a6971 | Blue Swirl | gen_helper_fdmulq(); |
2267 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2268 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2269 | dc1a6971 | Blue Swirl | break;
|
2270 | dc1a6971 | Blue Swirl | case 0xc4: /* fitos */ |
2271 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2272 | dc1a6971 | Blue Swirl | gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
2273 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2274 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2275 | dc1a6971 | Blue Swirl | break;
|
2276 | dc1a6971 | Blue Swirl | case 0xc6: /* fdtos */ |
2277 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2278 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2279 | dc1a6971 | Blue Swirl | gen_helper_fdtos(cpu_tmp32); |
2280 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2281 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2282 | dc1a6971 | Blue Swirl | break;
|
2283 | dc1a6971 | Blue Swirl | case 0xc7: /* fqtos */ |
2284 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2285 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2286 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2287 | dc1a6971 | Blue Swirl | gen_helper_fqtos(cpu_tmp32); |
2288 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2289 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2290 | dc1a6971 | Blue Swirl | break;
|
2291 | dc1a6971 | Blue Swirl | case 0xc8: /* fitod */ |
2292 | dc1a6971 | Blue Swirl | gen_helper_fitod(cpu_fpr[rs2]); |
2293 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2294 | dc1a6971 | Blue Swirl | break;
|
2295 | dc1a6971 | Blue Swirl | case 0xc9: /* fstod */ |
2296 | dc1a6971 | Blue Swirl | gen_helper_fstod(cpu_fpr[rs2]); |
2297 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2298 | dc1a6971 | Blue Swirl | break;
|
2299 | dc1a6971 | Blue Swirl | case 0xcb: /* fqtod */ |
2300 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2301 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2302 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2303 | dc1a6971 | Blue Swirl | gen_helper_fqtod(); |
2304 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2305 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2306 | dc1a6971 | Blue Swirl | break;
|
2307 | dc1a6971 | Blue Swirl | case 0xcc: /* fitoq */ |
2308 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2309 | dc1a6971 | Blue Swirl | gen_helper_fitoq(cpu_fpr[rs2]); |
2310 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2311 | dc1a6971 | Blue Swirl | break;
|
2312 | dc1a6971 | Blue Swirl | case 0xcd: /* fstoq */ |
2313 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2314 | dc1a6971 | Blue Swirl | gen_helper_fstoq(cpu_fpr[rs2]); |
2315 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2316 | dc1a6971 | Blue Swirl | break;
|
2317 | dc1a6971 | Blue Swirl | case 0xce: /* fdtoq */ |
2318 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2319 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2320 | dc1a6971 | Blue Swirl | gen_helper_fdtoq(); |
2321 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2322 | dc1a6971 | Blue Swirl | break;
|
2323 | dc1a6971 | Blue Swirl | case 0xd1: /* fstoi */ |
2324 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2325 | dc1a6971 | Blue Swirl | gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
2326 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2327 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2328 | dc1a6971 | Blue Swirl | break;
|
2329 | dc1a6971 | Blue Swirl | case 0xd2: /* fdtoi */ |
2330 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2331 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2332 | dc1a6971 | Blue Swirl | gen_helper_fdtoi(cpu_tmp32); |
2333 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2334 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2335 | dc1a6971 | Blue Swirl | break;
|
2336 | dc1a6971 | Blue Swirl | case 0xd3: /* fqtoi */ |
2337 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2338 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2339 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2340 | dc1a6971 | Blue Swirl | gen_helper_fqtoi(cpu_tmp32); |
2341 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2342 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2343 | dc1a6971 | Blue Swirl | break;
|
2344 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2345 | dc1a6971 | Blue Swirl | case 0x2: /* V9 fmovd */ |
2346 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2347 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
2348 | dc1a6971 | Blue Swirl | cpu_fpr[DFPREG(rs2) + 1]);
|
2349 | dc1a6971 | Blue Swirl | break;
|
2350 | dc1a6971 | Blue Swirl | case 0x3: /* V9 fmovq */ |
2351 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2352 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2353 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
|
2354 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 1]);
|
2355 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
|
2356 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 2]);
|
2357 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
|
2358 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 3]);
|
2359 | dc1a6971 | Blue Swirl | break;
|
2360 | dc1a6971 | Blue Swirl | case 0x6: /* V9 fnegd */ |
2361 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2362 | dc1a6971 | Blue Swirl | gen_helper_fnegd(); |
2363 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2364 | dc1a6971 | Blue Swirl | break;
|
2365 | dc1a6971 | Blue Swirl | case 0x7: /* V9 fnegq */ |
2366 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2367 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2368 | dc1a6971 | Blue Swirl | gen_helper_fnegq(); |
2369 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2370 | dc1a6971 | Blue Swirl | break;
|
2371 | dc1a6971 | Blue Swirl | case 0xa: /* V9 fabsd */ |
2372 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2373 | dc1a6971 | Blue Swirl | gen_helper_fabsd(); |
2374 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2375 | dc1a6971 | Blue Swirl | break;
|
2376 | dc1a6971 | Blue Swirl | case 0xb: /* V9 fabsq */ |
2377 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2378 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2379 | dc1a6971 | Blue Swirl | gen_helper_fabsq(); |
2380 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2381 | dc1a6971 | Blue Swirl | break;
|
2382 | dc1a6971 | Blue Swirl | case 0x81: /* V9 fstox */ |
2383 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2384 | dc1a6971 | Blue Swirl | gen_helper_fstox(cpu_fpr[rs2]); |
2385 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2386 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2387 | dc1a6971 | Blue Swirl | break;
|
2388 | dc1a6971 | Blue Swirl | case 0x82: /* V9 fdtox */ |
2389 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2390 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2391 | dc1a6971 | Blue Swirl | gen_helper_fdtox(); |
2392 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2393 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2394 | dc1a6971 | Blue Swirl | break;
|
2395 | dc1a6971 | Blue Swirl | case 0x83: /* V9 fqtox */ |
2396 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2397 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2398 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2399 | dc1a6971 | Blue Swirl | gen_helper_fqtox(); |
2400 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2401 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2402 | dc1a6971 | Blue Swirl | break;
|
2403 | dc1a6971 | Blue Swirl | case 0x84: /* V9 fxtos */ |
2404 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2405 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2406 | dc1a6971 | Blue Swirl | gen_helper_fxtos(cpu_tmp32); |
2407 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2408 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2409 | dc1a6971 | Blue Swirl | break;
|
2410 | dc1a6971 | Blue Swirl | case 0x88: /* V9 fxtod */ |
2411 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2412 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2413 | dc1a6971 | Blue Swirl | gen_helper_fxtod(); |
2414 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2415 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2416 | dc1a6971 | Blue Swirl | break;
|
2417 | dc1a6971 | Blue Swirl | case 0x8c: /* V9 fxtoq */ |
2418 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2419 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2420 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2421 | dc1a6971 | Blue Swirl | gen_helper_fxtoq(); |
2422 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2423 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2424 | dc1a6971 | Blue Swirl | break;
|
2425 | 1f587329 | blueswir1 | #endif
|
2426 | dc1a6971 | Blue Swirl | default:
|
2427 | dc1a6971 | Blue Swirl | goto illegal_insn;
|
2428 | 0f8a249a | blueswir1 | } |
2429 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2430 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2431 | 0f8a249a | blueswir1 | int cond;
|
2432 | 3475187d | bellard | #endif
|
2433 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2434 | a80dde08 | bellard | goto jmp_insn;
|
2435 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2436 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2437 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2438 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2439 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2440 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2441 | dcf24905 | blueswir1 | int l1;
|
2442 | dcf24905 | blueswir1 | |
2443 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2444 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2445 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2446 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2447 | cb63669a | pbrook | 0, l1);
|
2448 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2449 | dcf24905 | blueswir1 | gen_set_label(l1); |
2450 | 0f8a249a | blueswir1 | break;
|
2451 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2452 | dcf24905 | blueswir1 | int l1;
|
2453 | dcf24905 | blueswir1 | |
2454 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2455 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2456 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2457 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2458 | cb63669a | pbrook | 0, l1);
|
2459 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2460 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); |
2461 | dcf24905 | blueswir1 | gen_set_label(l1); |
2462 | 0f8a249a | blueswir1 | break;
|
2463 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2464 | dcf24905 | blueswir1 | int l1;
|
2465 | dcf24905 | blueswir1 | |
2466 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2467 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2468 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2469 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2470 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2471 | cb63669a | pbrook | 0, l1);
|
2472 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2473 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); |
2474 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); |
2475 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); |
2476 | dcf24905 | blueswir1 | gen_set_label(l1); |
2477 | 1f587329 | blueswir1 | break;
|
2478 | 0f8a249a | blueswir1 | } |
2479 | 0f8a249a | blueswir1 | #endif
|
2480 | 0f8a249a | blueswir1 | switch (xop) {
|
2481 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2482 | 714547bb | blueswir1 | #define FMOVSCC(fcc) \
|
2483 | 19f329ad | blueswir1 | { \ |
2484 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2485 | 19f329ad | blueswir1 | int l1; \
|
2486 | 19f329ad | blueswir1 | \ |
2487 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2488 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2489 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2490 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2491 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2492 | cb63669a | pbrook | 0, l1); \
|
2493 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2494 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2495 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2496 | 714547bb | blueswir1 | } |
2497 | 714547bb | blueswir1 | #define FMOVDCC(fcc) \
|
2498 | 714547bb | blueswir1 | { \ |
2499 | 714547bb | blueswir1 | TCGv r_cond; \ |
2500 | 714547bb | blueswir1 | int l1; \
|
2501 | 714547bb | blueswir1 | \ |
2502 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2503 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2504 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2505 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2506 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2507 | 714547bb | blueswir1 | 0, l1); \
|
2508 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2509 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2510 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2511 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2512 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2513 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2514 | 714547bb | blueswir1 | } |
2515 | 714547bb | blueswir1 | #define FMOVQCC(fcc) \
|
2516 | 714547bb | blueswir1 | { \ |
2517 | 714547bb | blueswir1 | TCGv r_cond; \ |
2518 | 714547bb | blueswir1 | int l1; \
|
2519 | 714547bb | blueswir1 | \ |
2520 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2521 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2522 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2523 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2524 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2525 | 714547bb | blueswir1 | 0, l1); \
|
2526 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2527 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2528 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2529 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2530 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2531 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2532 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2533 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2534 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2535 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2536 | 19f329ad | blueswir1 | } |
2537 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2538 | 714547bb | blueswir1 | FMOVSCC(0);
|
2539 | 0f8a249a | blueswir1 | break;
|
2540 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2541 | 714547bb | blueswir1 | FMOVDCC(0);
|
2542 | 0f8a249a | blueswir1 | break;
|
2543 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2544 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2545 | 714547bb | blueswir1 | FMOVQCC(0);
|
2546 | 1f587329 | blueswir1 | break;
|
2547 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2548 | 714547bb | blueswir1 | FMOVSCC(1);
|
2549 | 0f8a249a | blueswir1 | break;
|
2550 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2551 | 714547bb | blueswir1 | FMOVDCC(1);
|
2552 | 0f8a249a | blueswir1 | break;
|
2553 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2554 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2555 | 714547bb | blueswir1 | FMOVQCC(1);
|
2556 | 1f587329 | blueswir1 | break;
|
2557 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2558 | 714547bb | blueswir1 | FMOVSCC(2);
|
2559 | 0f8a249a | blueswir1 | break;
|
2560 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2561 | 714547bb | blueswir1 | FMOVDCC(2);
|
2562 | 0f8a249a | blueswir1 | break;
|
2563 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2564 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2565 | 714547bb | blueswir1 | FMOVQCC(2);
|
2566 | 1f587329 | blueswir1 | break;
|
2567 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2568 | 714547bb | blueswir1 | FMOVSCC(3);
|
2569 | 0f8a249a | blueswir1 | break;
|
2570 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2571 | 714547bb | blueswir1 | FMOVDCC(3);
|
2572 | 0f8a249a | blueswir1 | break;
|
2573 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2574 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2575 | 714547bb | blueswir1 | FMOVQCC(3);
|
2576 | 1f587329 | blueswir1 | break;
|
2577 | 714547bb | blueswir1 | #undef FMOVSCC
|
2578 | 714547bb | blueswir1 | #undef FMOVDCC
|
2579 | 714547bb | blueswir1 | #undef FMOVQCC
|
2580 | 714547bb | blueswir1 | #define FMOVSCC(icc) \
|
2581 | 714547bb | blueswir1 | { \ |
2582 | 714547bb | blueswir1 | TCGv r_cond; \ |
2583 | 714547bb | blueswir1 | int l1; \
|
2584 | 714547bb | blueswir1 | \ |
2585 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2586 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2587 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2588 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2589 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2590 | 714547bb | blueswir1 | 0, l1); \
|
2591 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2592 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2593 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2594 | 714547bb | blueswir1 | } |
2595 | 714547bb | blueswir1 | #define FMOVDCC(icc) \
|
2596 | 714547bb | blueswir1 | { \ |
2597 | 714547bb | blueswir1 | TCGv r_cond; \ |
2598 | 714547bb | blueswir1 | int l1; \
|
2599 | 714547bb | blueswir1 | \ |
2600 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2601 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2602 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2603 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2604 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2605 | 714547bb | blueswir1 | 0, l1); \
|
2606 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2607 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2608 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2609 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2610 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2611 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2612 | 714547bb | blueswir1 | } |
2613 | 714547bb | blueswir1 | #define FMOVQCC(icc) \
|
2614 | 714547bb | blueswir1 | { \ |
2615 | 714547bb | blueswir1 | TCGv r_cond; \ |
2616 | 714547bb | blueswir1 | int l1; \
|
2617 | 714547bb | blueswir1 | \ |
2618 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2619 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2620 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2621 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2622 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2623 | 714547bb | blueswir1 | 0, l1); \
|
2624 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2625 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2626 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2627 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2628 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2629 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2630 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2631 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2632 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2633 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2634 | 714547bb | blueswir1 | } |
2635 | 19f329ad | blueswir1 | |
2636 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2637 | 714547bb | blueswir1 | FMOVSCC(0);
|
2638 | 0f8a249a | blueswir1 | break;
|
2639 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2640 | 714547bb | blueswir1 | FMOVDCC(0);
|
2641 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2642 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2643 | 714547bb | blueswir1 | FMOVQCC(0);
|
2644 | 1f587329 | blueswir1 | break;
|
2645 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2646 | 714547bb | blueswir1 | FMOVSCC(1);
|
2647 | 0f8a249a | blueswir1 | break;
|
2648 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2649 | 714547bb | blueswir1 | FMOVDCC(1);
|
2650 | 0f8a249a | blueswir1 | break;
|
2651 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2652 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2653 | 714547bb | blueswir1 | FMOVQCC(1);
|
2654 | 1f587329 | blueswir1 | break;
|
2655 | 714547bb | blueswir1 | #undef FMOVSCC
|
2656 | 714547bb | blueswir1 | #undef FMOVDCC
|
2657 | 714547bb | blueswir1 | #undef FMOVQCC
|
2658 | 1f587329 | blueswir1 | #endif
|
2659 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2660 | 714547bb | blueswir1 | gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2661 | 0f8a249a | blueswir1 | break;
|
2662 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2663 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2664 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2665 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2666 | 0f8a249a | blueswir1 | break;
|
2667 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2668 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2669 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2670 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2671 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2672 | 1f587329 | blueswir1 | break;
|
2673 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2674 | 714547bb | blueswir1 | gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2675 | 0f8a249a | blueswir1 | break;
|
2676 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2677 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2678 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2679 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2680 | 0f8a249a | blueswir1 | break;
|
2681 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2682 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2683 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2684 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2685 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2686 | 1f587329 | blueswir1 | break;
|
2687 | 0f8a249a | blueswir1 | default:
|
2688 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2689 | 0f8a249a | blueswir1 | } |
2690 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2691 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2692 | e80cfcfc | bellard | |
2693 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2694 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2695 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2696 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2697 | 2ea815ca | blueswir1 | TCGv r_const; |
2698 | 2ea815ca | blueswir1 | |
2699 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2700 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
2701 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2702 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2703 | 0f8a249a | blueswir1 | } else { /* register */ |
2704 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2705 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_dst); |
2706 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2707 | 0f8a249a | blueswir1 | } |
2708 | 0f8a249a | blueswir1 | } else {
|
2709 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2710 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2711 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2712 | 67526b20 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
2713 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2714 | 0f8a249a | blueswir1 | } else { /* register */ |
2715 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2716 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2717 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2718 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2719 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2720 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2721 | 6f551262 | blueswir1 | } else
|
2722 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_src1); |
2723 | 0f8a249a | blueswir1 | } |
2724 | 0f8a249a | blueswir1 | } |
2725 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2726 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2727 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2728 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2729 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2730 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2731 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2732 | 1a2fb1c0 | blueswir1 | } else {
|
2733 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
|
2734 | 1a2fb1c0 | blueswir1 | } |
2735 | 0f8a249a | blueswir1 | } else { /* register */ |
2736 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2737 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2738 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2739 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2740 | 1a2fb1c0 | blueswir1 | } else {
|
2741 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2742 | 1a2fb1c0 | blueswir1 | } |
2743 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2744 | 83469015 | bellard | } |
2745 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2746 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2747 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2748 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2749 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2750 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2751 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2752 | 1a2fb1c0 | blueswir1 | } else {
|
2753 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2754 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2755 | 1a2fb1c0 | blueswir1 | } |
2756 | 0f8a249a | blueswir1 | } else { /* register */ |
2757 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2758 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2759 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2760 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2761 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2762 | 1a2fb1c0 | blueswir1 | } else {
|
2763 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2764 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2765 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2766 | 1a2fb1c0 | blueswir1 | } |
2767 | 83469015 | bellard | } |
2768 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2769 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2770 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2771 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2772 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2773 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2774 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2775 | 1a2fb1c0 | blueswir1 | } else {
|
2776 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2777 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2778 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2779 | 1a2fb1c0 | blueswir1 | } |
2780 | 0f8a249a | blueswir1 | } else { /* register */ |
2781 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2782 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2783 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2784 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2785 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2786 | 1a2fb1c0 | blueswir1 | } else {
|
2787 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2788 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2789 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2790 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2791 | 1a2fb1c0 | blueswir1 | } |
2792 | 83469015 | bellard | } |
2793 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2794 | 83469015 | bellard | #endif
|
2795 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
2796 | cf495bcf | bellard | if (xop < 0x20) { |
2797 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
2798 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
2799 | cf495bcf | bellard | switch (xop & ~0x10) { |
2800 | b89e94af | Blue Swirl | case 0x0: /* add */ |
2801 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2802 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2803 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2804 | 41d72852 | Blue Swirl | gen_op_addi_cc(cpu_dst, cpu_src1, simm); |
2805 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
2806 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
2807 | 41d72852 | Blue Swirl | } else {
|
2808 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
2809 | 41d72852 | Blue Swirl | } |
2810 | 41d72852 | Blue Swirl | } else {
|
2811 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2812 | 41d72852 | Blue Swirl | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
2813 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
2814 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
2815 | 41d72852 | Blue Swirl | } else {
|
2816 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
2817 | 41d72852 | Blue Swirl | } |
2818 | 41d72852 | Blue Swirl | } |
2819 | cf495bcf | bellard | break;
|
2820 | b89e94af | Blue Swirl | case 0x1: /* and */ |
2821 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2822 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2823 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, simm); |
2824 | 41d72852 | Blue Swirl | } else {
|
2825 | 41d72852 | Blue Swirl | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
2826 | 41d72852 | Blue Swirl | } |
2827 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2828 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2829 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2830 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2831 | 41d72852 | Blue Swirl | } |
2832 | cf495bcf | bellard | break;
|
2833 | b89e94af | Blue Swirl | case 0x2: /* or */ |
2834 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2835 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2836 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
2837 | 41d72852 | Blue Swirl | } else {
|
2838 | 41d72852 | Blue Swirl | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2839 | 41d72852 | Blue Swirl | } |
2840 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2841 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2842 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2843 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2844 | 8393617c | Blue Swirl | } |
2845 | 0f8a249a | blueswir1 | break;
|
2846 | b89e94af | Blue Swirl | case 0x3: /* xor */ |
2847 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2848 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2849 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, simm); |
2850 | 41d72852 | Blue Swirl | } else {
|
2851 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
2852 | 41d72852 | Blue Swirl | } |
2853 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2854 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2855 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2856 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2857 | 8393617c | Blue Swirl | } |
2858 | cf495bcf | bellard | break;
|
2859 | b89e94af | Blue Swirl | case 0x4: /* sub */ |
2860 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2861 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2862 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2863 | d4b0d468 | Blue Swirl | gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc); |
2864 | 41d72852 | Blue Swirl | } else {
|
2865 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_dst, cpu_src1, simm); |
2866 | 41d72852 | Blue Swirl | } |
2867 | 41d72852 | Blue Swirl | } else {
|
2868 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2869 | 41d72852 | Blue Swirl | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
2870 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
2871 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
2872 | 41d72852 | Blue Swirl | } else {
|
2873 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
2874 | 41d72852 | Blue Swirl | } |
2875 | 41d72852 | Blue Swirl | } |
2876 | cf495bcf | bellard | break;
|
2877 | b89e94af | Blue Swirl | case 0x5: /* andn */ |
2878 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2879 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2880 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm); |
2881 | 41d72852 | Blue Swirl | } else {
|
2882 | 41d72852 | Blue Swirl | tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); |
2883 | 41d72852 | Blue Swirl | } |
2884 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2885 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2886 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2887 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2888 | 8393617c | Blue Swirl | } |
2889 | cf495bcf | bellard | break;
|
2890 | b89e94af | Blue Swirl | case 0x6: /* orn */ |
2891 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2892 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2893 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm); |
2894 | 41d72852 | Blue Swirl | } else {
|
2895 | 41d72852 | Blue Swirl | tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); |
2896 | 41d72852 | Blue Swirl | } |
2897 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2898 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2899 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2900 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2901 | 8393617c | Blue Swirl | } |
2902 | cf495bcf | bellard | break;
|
2903 | b89e94af | Blue Swirl | case 0x7: /* xorn */ |
2904 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2905 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2906 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm); |
2907 | 41d72852 | Blue Swirl | } else {
|
2908 | 41d72852 | Blue Swirl | tcg_gen_not_tl(cpu_tmp0, cpu_src2); |
2909 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2910 | 41d72852 | Blue Swirl | } |
2911 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2912 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2913 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2914 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2915 | 8393617c | Blue Swirl | } |
2916 | cf495bcf | bellard | break;
|
2917 | b89e94af | Blue Swirl | case 0x8: /* addx, V9 addc */ |
2918 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2919 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2920 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2921 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2922 | 41d72852 | Blue Swirl | gen_op_addxi_cc(cpu_dst, cpu_src1, simm); |
2923 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
2924 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
2925 | 8393617c | Blue Swirl | } else {
|
2926 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2927 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2928 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
2929 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2930 | 41d72852 | Blue Swirl | } |
2931 | 41d72852 | Blue Swirl | } else {
|
2932 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2933 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2934 | 41d72852 | Blue Swirl | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
2935 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
2936 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
2937 | 8393617c | Blue Swirl | } else {
|
2938 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2939 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2940 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
2941 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2942 | 41d72852 | Blue Swirl | } |
2943 | 38bc628b | blueswir1 | } |
2944 | cf495bcf | bellard | break;
|
2945 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
2946 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
2947 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2948 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2949 | 41d72852 | Blue Swirl | tcg_gen_muli_i64(cpu_dst, cpu_src1, simm); |
2950 | 41d72852 | Blue Swirl | } else {
|
2951 | 41d72852 | Blue Swirl | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
2952 | 41d72852 | Blue Swirl | } |
2953 | ded3ab80 | pbrook | break;
|
2954 | ded3ab80 | pbrook | #endif
|
2955 | b89e94af | Blue Swirl | case 0xa: /* umul */ |
2956 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
2957 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
2958 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2959 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2960 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2961 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2962 | 8393617c | Blue Swirl | } |
2963 | cf495bcf | bellard | break;
|
2964 | b89e94af | Blue Swirl | case 0xb: /* smul */ |
2965 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
2966 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
2967 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2968 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2969 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2970 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2971 | 8393617c | Blue Swirl | } |
2972 | cf495bcf | bellard | break;
|
2973 | b89e94af | Blue Swirl | case 0xc: /* subx, V9 subc */ |
2974 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2975 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2976 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2977 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2978 | 41d72852 | Blue Swirl | gen_op_subxi_cc(cpu_dst, cpu_src1, simm); |
2979 | 2ca1d92b | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
2980 | 2ca1d92b | Blue Swirl | dc->cc_op = CC_OP_SUBX; |
2981 | 41d72852 | Blue Swirl | } else {
|
2982 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2983 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2984 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
2985 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2986 | 41d72852 | Blue Swirl | } |
2987 | 41d72852 | Blue Swirl | } else {
|
2988 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2989 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2990 | 41d72852 | Blue Swirl | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
2991 | 2ca1d92b | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
2992 | 2ca1d92b | Blue Swirl | dc->cc_op = CC_OP_SUBX; |
2993 | 41d72852 | Blue Swirl | } else {
|
2994 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2995 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2996 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
2997 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2998 | 41d72852 | Blue Swirl | } |
2999 | 38bc628b | blueswir1 | } |
3000 | cf495bcf | bellard | break;
|
3001 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3002 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3003 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3004 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); |
3005 | 07bf2857 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
3006 | 07bf2857 | blueswir1 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
3007 | ded3ab80 | pbrook | break;
|
3008 | ded3ab80 | pbrook | #endif
|
3009 | b89e94af | Blue Swirl | case 0xe: /* udiv */ |
3010 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3011 | a7812ae4 | pbrook | gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); |
3012 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3013 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3014 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3015 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3016 | 8393617c | Blue Swirl | } |
3017 | cf495bcf | bellard | break;
|
3018 | b89e94af | Blue Swirl | case 0xf: /* sdiv */ |
3019 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3020 | a7812ae4 | pbrook | gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); |
3021 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3022 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3023 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3024 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3025 | 8393617c | Blue Swirl | } |
3026 | cf495bcf | bellard | break;
|
3027 | cf495bcf | bellard | default:
|
3028 | cf495bcf | bellard | goto illegal_insn;
|
3029 | cf495bcf | bellard | } |
3030 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3031 | cf495bcf | bellard | } else {
|
3032 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
3033 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
3034 | cf495bcf | bellard | switch (xop) {
|
3035 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3036 | 6ae20372 | blueswir1 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3037 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3038 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); |
3039 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADD; |
3040 | 0f8a249a | blueswir1 | break;
|
3041 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3042 | 6ae20372 | blueswir1 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3043 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3044 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); |
3045 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUB; |
3046 | 0f8a249a | blueswir1 | break;
|
3047 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3048 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3049 | 6ae20372 | blueswir1 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3050 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3051 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV); |
3052 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADDTV; |
3053 | 0f8a249a | blueswir1 | break;
|
3054 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3055 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3056 | 6ae20372 | blueswir1 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3057 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3058 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV); |
3059 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUBTV; |
3060 | 0f8a249a | blueswir1 | break;
|
3061 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3062 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3063 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3064 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3065 | d084469c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3066 | d084469c | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3067 | cf495bcf | bellard | break;
|
3068 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3069 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3070 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3071 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3072 | 67526b20 | Blue Swirl | tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3073 | e35298cd | blueswir1 | } else { /* register */ |
3074 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3075 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3076 | e35298cd | blueswir1 | } |
3077 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3078 | cf495bcf | bellard | break;
|
3079 | 83469015 | bellard | case 0x26: /* srl */ |
3080 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3081 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3082 | 67526b20 | Blue Swirl | tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3083 | e35298cd | blueswir1 | } else { /* register */ |
3084 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3085 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3086 | e35298cd | blueswir1 | } |
3087 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3088 | cf495bcf | bellard | break;
|
3089 | 83469015 | bellard | case 0x27: /* sra */ |
3090 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3091 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3092 | 67526b20 | Blue Swirl | tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3093 | e35298cd | blueswir1 | } else { /* register */ |
3094 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3095 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3096 | e35298cd | blueswir1 | } |
3097 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3098 | cf495bcf | bellard | break;
|
3099 | 83469015 | bellard | #endif
|
3100 | cf495bcf | bellard | case 0x30: |
3101 | cf495bcf | bellard | { |
3102 | cf495bcf | bellard | switch(rd) {
|
3103 | 3475187d | bellard | case 0: /* wry */ |
3104 | 5068cbd9 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3105 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
3106 | cf495bcf | bellard | break;
|
3107 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3108 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3109 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3110 | 65fe7b09 | blueswir1 | on the microSPARC
|
3111 | 65fe7b09 | blueswir1 | II */
|
3112 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3113 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3114 | 65fe7b09 | blueswir1 | manual, nop on the
|
3115 | 65fe7b09 | blueswir1 | microSPARC II */
|
3116 | 65fe7b09 | blueswir1 | break;
|
3117 | 65fe7b09 | blueswir1 | #else
|
3118 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3119 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3120 | a7812ae4 | pbrook | gen_helper_wrccr(cpu_dst); |
3121 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3122 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3123 | 0f8a249a | blueswir1 | break;
|
3124 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3125 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3126 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
3127 | 0f8a249a | blueswir1 | break;
|
3128 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3129 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3130 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
3131 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3132 | 3299908c | blueswir1 | gen_op_next_insn(); |
3133 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3134 | 3299908c | blueswir1 | dc->is_br = 1;
|
3135 | 0f8a249a | blueswir1 | break;
|
3136 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3137 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3138 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3139 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3140 | 3475187d | bellard | #endif
|
3141 | 0f8a249a | blueswir1 | break;
|
3142 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3143 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3144 | 725cb90b | bellard | goto jmp_insn;
|
3145 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
3146 | 0f8a249a | blueswir1 | break;
|
3147 | 9d926598 | blueswir1 | case 0x14: /* Softint set */ |
3148 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3149 | 9d926598 | blueswir1 | goto illegal_insn;
|
3150 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3151 | a7812ae4 | pbrook | gen_helper_set_softint(cpu_tmp64); |
3152 | 9d926598 | blueswir1 | break;
|
3153 | 9d926598 | blueswir1 | case 0x15: /* Softint clear */ |
3154 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3155 | 9d926598 | blueswir1 | goto illegal_insn;
|
3156 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3157 | a7812ae4 | pbrook | gen_helper_clear_softint(cpu_tmp64); |
3158 | 9d926598 | blueswir1 | break;
|
3159 | 9d926598 | blueswir1 | case 0x16: /* Softint write */ |
3160 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3161 | 9d926598 | blueswir1 | goto illegal_insn;
|
3162 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3163 | a7812ae4 | pbrook | gen_helper_write_softint(cpu_tmp64); |
3164 | 9d926598 | blueswir1 | break;
|
3165 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3166 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3167 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3168 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3169 | 83469015 | bellard | #endif
|
3170 | ccd4a219 | blueswir1 | { |
3171 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3172 | ccd4a219 | blueswir1 | |
3173 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
3174 | 6ae20372 | blueswir1 | cpu_src2); |
3175 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3176 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3177 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3178 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3179 | a7812ae4 | pbrook | cpu_tick_cmpr); |
3180 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3181 | ccd4a219 | blueswir1 | } |
3182 | 0f8a249a | blueswir1 | break;
|
3183 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3184 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3185 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3186 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3187 | 83469015 | bellard | #endif
|
3188 | ccd4a219 | blueswir1 | { |
3189 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3190 | ccd4a219 | blueswir1 | |
3191 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3192 | 6ae20372 | blueswir1 | cpu_src2); |
3193 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3194 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3195 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3196 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3197 | a7812ae4 | pbrook | cpu_dst); |
3198 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3199 | ccd4a219 | blueswir1 | } |
3200 | 0f8a249a | blueswir1 | break;
|
3201 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3202 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3203 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3204 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3205 | 3475187d | bellard | #endif
|
3206 | ccd4a219 | blueswir1 | { |
3207 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3208 | ccd4a219 | blueswir1 | |
3209 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
3210 | 6ae20372 | blueswir1 | cpu_src2); |
3211 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3212 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3213 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3214 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3215 | a7812ae4 | pbrook | cpu_stick_cmpr); |
3216 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3217 | ccd4a219 | blueswir1 | } |
3218 | 0f8a249a | blueswir1 | break;
|
3219 | 83469015 | bellard | |
3220 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3221 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3222 | 77f193da | blueswir1 | Counter */
|
3223 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3224 | 83469015 | bellard | #endif
|
3225 | 3475187d | bellard | default:
|
3226 | cf495bcf | bellard | goto illegal_insn;
|
3227 | cf495bcf | bellard | } |
3228 | cf495bcf | bellard | } |
3229 | cf495bcf | bellard | break;
|
3230 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3231 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3232 | e8af50a3 | bellard | { |
3233 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3234 | 0f8a249a | blueswir1 | goto priv_insn;
|
3235 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3236 | 0f8a249a | blueswir1 | switch (rd) {
|
3237 | 0f8a249a | blueswir1 | case 0: |
3238 | a7812ae4 | pbrook | gen_helper_saved(); |
3239 | 0f8a249a | blueswir1 | break;
|
3240 | 0f8a249a | blueswir1 | case 1: |
3241 | a7812ae4 | pbrook | gen_helper_restored(); |
3242 | 0f8a249a | blueswir1 | break;
|
3243 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3244 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3245 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3246 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3247 | e9ebed4d | blueswir1 | // XXX
|
3248 | 0f8a249a | blueswir1 | default:
|
3249 | 3475187d | bellard | goto illegal_insn;
|
3250 | 3475187d | bellard | } |
3251 | 3475187d | bellard | #else
|
3252 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3253 | a7812ae4 | pbrook | gen_helper_wrpsr(cpu_dst); |
3254 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3255 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3256 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3257 | 9e61bde5 | bellard | gen_op_next_insn(); |
3258 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3259 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3260 | 3475187d | bellard | #endif
|
3261 | e8af50a3 | bellard | } |
3262 | e8af50a3 | bellard | break;
|
3263 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3264 | e8af50a3 | bellard | { |
3265 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3266 | 0f8a249a | blueswir1 | goto priv_insn;
|
3267 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3268 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3269 | 0f8a249a | blueswir1 | switch (rd) {
|
3270 | 0f8a249a | blueswir1 | case 0: // tpc |
3271 | 375ee38b | blueswir1 | { |
3272 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3273 | 375ee38b | blueswir1 | |
3274 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3275 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3276 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3277 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3278 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3279 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3280 | 375ee38b | blueswir1 | } |
3281 | 0f8a249a | blueswir1 | break;
|
3282 | 0f8a249a | blueswir1 | case 1: // tnpc |
3283 | 375ee38b | blueswir1 | { |
3284 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3285 | 375ee38b | blueswir1 | |
3286 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3287 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3288 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3289 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3290 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3291 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3292 | 375ee38b | blueswir1 | } |
3293 | 0f8a249a | blueswir1 | break;
|
3294 | 0f8a249a | blueswir1 | case 2: // tstate |
3295 | 375ee38b | blueswir1 | { |
3296 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3297 | 375ee38b | blueswir1 | |
3298 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3299 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3300 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3301 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3302 | 77f193da | blueswir1 | offsetof(trap_state, |
3303 | 77f193da | blueswir1 | tstate)); |
3304 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3305 | 375ee38b | blueswir1 | } |
3306 | 0f8a249a | blueswir1 | break;
|
3307 | 0f8a249a | blueswir1 | case 3: // tt |
3308 | 375ee38b | blueswir1 | { |
3309 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3310 | 375ee38b | blueswir1 | |
3311 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3312 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3313 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3314 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3315 | 527067d8 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, r_tsptr, |
3316 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3317 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3318 | 375ee38b | blueswir1 | } |
3319 | 0f8a249a | blueswir1 | break;
|
3320 | 0f8a249a | blueswir1 | case 4: // tick |
3321 | ccd4a219 | blueswir1 | { |
3322 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3323 | ccd4a219 | blueswir1 | |
3324 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3325 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3326 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3327 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3328 | a7812ae4 | pbrook | cpu_tmp0); |
3329 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3330 | ccd4a219 | blueswir1 | } |
3331 | 0f8a249a | blueswir1 | break;
|
3332 | 0f8a249a | blueswir1 | case 5: // tba |
3333 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
3334 | 0f8a249a | blueswir1 | break;
|
3335 | 0f8a249a | blueswir1 | case 6: // pstate |
3336 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3337 | a7812ae4 | pbrook | gen_helper_wrpstate(cpu_tmp0); |
3338 | ded3ab80 | pbrook | gen_op_next_insn(); |
3339 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3340 | ded3ab80 | pbrook | dc->is_br = 1;
|
3341 | 0f8a249a | blueswir1 | break;
|
3342 | 0f8a249a | blueswir1 | case 7: // tl |
3343 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3344 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3345 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
3346 | 0f8a249a | blueswir1 | break;
|
3347 | 0f8a249a | blueswir1 | case 8: // pil |
3348 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3349 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3350 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3351 | 77f193da | blueswir1 | psrpil)); |
3352 | 0f8a249a | blueswir1 | break;
|
3353 | 0f8a249a | blueswir1 | case 9: // cwp |
3354 | a7812ae4 | pbrook | gen_helper_wrcwp(cpu_tmp0); |
3355 | 0f8a249a | blueswir1 | break;
|
3356 | 0f8a249a | blueswir1 | case 10: // cansave |
3357 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3358 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3359 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3360 | 77f193da | blueswir1 | cansave)); |
3361 | 0f8a249a | blueswir1 | break;
|
3362 | 0f8a249a | blueswir1 | case 11: // canrestore |
3363 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3364 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3365 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3366 | 77f193da | blueswir1 | canrestore)); |
3367 | 0f8a249a | blueswir1 | break;
|
3368 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3369 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3370 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3371 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3372 | 77f193da | blueswir1 | cleanwin)); |
3373 | 0f8a249a | blueswir1 | break;
|
3374 | 0f8a249a | blueswir1 | case 13: // otherwin |
3375 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3376 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3377 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3378 | 77f193da | blueswir1 | otherwin)); |
3379 | 0f8a249a | blueswir1 | break;
|
3380 | 0f8a249a | blueswir1 | case 14: // wstate |
3381 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3382 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3383 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3384 | 77f193da | blueswir1 | wstate)); |
3385 | 0f8a249a | blueswir1 | break;
|
3386 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3387 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3388 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3389 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3390 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
3391 | e9ebed4d | blueswir1 | break;
|
3392 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3393 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3394 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3395 | e9ebed4d | blueswir1 | goto priv_insn;
|
3396 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); |
3397 | e9ebed4d | blueswir1 | break;
|
3398 | 0f8a249a | blueswir1 | default:
|
3399 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3400 | 0f8a249a | blueswir1 | } |
3401 | 3475187d | bellard | #else
|
3402 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3403 | c93e7817 | blueswir1 | if (dc->def->nwindows != 32) |
3404 | c93e7817 | blueswir1 | tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, |
3405 | c93e7817 | blueswir1 | (1 << dc->def->nwindows) - 1); |
3406 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
3407 | 3475187d | bellard | #endif
|
3408 | e8af50a3 | bellard | } |
3409 | e8af50a3 | bellard | break;
|
3410 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3411 | e8af50a3 | bellard | { |
3412 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3413 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3414 | 0f8a249a | blueswir1 | goto priv_insn;
|
3415 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
3416 | e9ebed4d | blueswir1 | #else
|
3417 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3418 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3419 | e9ebed4d | blueswir1 | goto priv_insn;
|
3420 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3421 | e9ebed4d | blueswir1 | switch (rd) {
|
3422 | e9ebed4d | blueswir1 | case 0: // hpstate |
3423 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3424 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3425 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3426 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3427 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3428 | e9ebed4d | blueswir1 | break;
|
3429 | e9ebed4d | blueswir1 | case 1: // htstate |
3430 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3431 | e9ebed4d | blueswir1 | break;
|
3432 | e9ebed4d | blueswir1 | case 3: // hintp |
3433 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
3434 | e9ebed4d | blueswir1 | break;
|
3435 | e9ebed4d | blueswir1 | case 5: // htba |
3436 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
3437 | e9ebed4d | blueswir1 | break;
|
3438 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3439 | ccd4a219 | blueswir1 | { |
3440 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3441 | ccd4a219 | blueswir1 | |
3442 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
3443 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3444 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3445 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3446 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3447 | a7812ae4 | pbrook | cpu_hstick_cmpr); |
3448 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3449 | ccd4a219 | blueswir1 | } |
3450 | e9ebed4d | blueswir1 | break;
|
3451 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3452 | e9ebed4d | blueswir1 | default:
|
3453 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3454 | e9ebed4d | blueswir1 | } |
3455 | e9ebed4d | blueswir1 | #endif
|
3456 | e8af50a3 | bellard | } |
3457 | e8af50a3 | bellard | break;
|
3458 | e8af50a3 | bellard | #endif
|
3459 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3460 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3461 | 0f8a249a | blueswir1 | { |
3462 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3463 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3464 | 748b9d8e | blueswir1 | TCGv r_cond; |
3465 | 00f219bf | blueswir1 | int l1;
|
3466 | 00f219bf | blueswir1 | |
3467 | a7812ae4 | pbrook | r_cond = tcg_temp_new(); |
3468 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3469 | 0f8a249a | blueswir1 | if (cc == 0) |
3470 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
3471 | 0f8a249a | blueswir1 | else if (cc == 2) |
3472 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
3473 | 0f8a249a | blueswir1 | else
|
3474 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3475 | 0f8a249a | blueswir1 | } else {
|
3476 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3477 | 0f8a249a | blueswir1 | } |
3478 | 00f219bf | blueswir1 | |
3479 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3480 | 00f219bf | blueswir1 | |
3481 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
3482 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3483 | 2ea815ca | blueswir1 | TCGv r_const; |
3484 | 2ea815ca | blueswir1 | |
3485 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 10); |
3486 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3487 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3488 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3489 | 00f219bf | blueswir1 | } else {
|
3490 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3491 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3492 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3493 | 00f219bf | blueswir1 | } |
3494 | 00f219bf | blueswir1 | gen_set_label(l1); |
3495 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
3496 | 0f8a249a | blueswir1 | break;
|
3497 | 0f8a249a | blueswir1 | } |
3498 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3499 | 6ae20372 | blueswir1 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3500 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3501 | 0f8a249a | blueswir1 | break;
|
3502 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3503 | 0f8a249a | blueswir1 | { |
3504 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3505 | a7812ae4 | pbrook | gen_helper_popc(cpu_dst, cpu_src2); |
3506 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3507 | 0f8a249a | blueswir1 | } |
3508 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3509 | 0f8a249a | blueswir1 | { |
3510 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3511 | 00f219bf | blueswir1 | int l1;
|
3512 | 00f219bf | blueswir1 | |
3513 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3514 | 00f219bf | blueswir1 | |
3515 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3516 | 00f219bf | blueswir1 | |
3517 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3518 | cb63669a | pbrook | cpu_src1, 0, l1);
|
3519 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3520 | 2ea815ca | blueswir1 | TCGv r_const; |
3521 | 2ea815ca | blueswir1 | |
3522 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 9); |
3523 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3524 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3525 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3526 | 00f219bf | blueswir1 | } else {
|
3527 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3528 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3529 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3530 | 0f8a249a | blueswir1 | } |
3531 | 00f219bf | blueswir1 | gen_set_label(l1); |
3532 | 0f8a249a | blueswir1 | break;
|
3533 | 0f8a249a | blueswir1 | } |
3534 | 0f8a249a | blueswir1 | #endif
|
3535 | 0f8a249a | blueswir1 | default:
|
3536 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3537 | 0f8a249a | blueswir1 | } |
3538 | 0f8a249a | blueswir1 | } |
3539 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3540 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3541 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3542 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3543 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3544 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3545 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3546 | 3299908c | blueswir1 | |
3547 | 3299908c | blueswir1 | switch (opf) {
|
3548 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3549 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3550 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3551 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3552 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3553 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3554 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3555 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3556 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3557 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3558 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3559 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3560 | e9ebed4d | blueswir1 | // XXX
|
3561 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3562 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3563 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3564 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3565 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3566 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3567 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3568 | e9ebed4d | blueswir1 | break;
|
3569 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3570 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3571 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3572 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3573 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3574 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
3575 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3576 | e9ebed4d | blueswir1 | break;
|
3577 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3578 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3579 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3580 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3581 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3582 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
3583 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3584 | e9ebed4d | blueswir1 | break;
|
3585 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3586 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3587 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3588 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3589 | a7812ae4 | pbrook | gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); |
3590 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3591 | 3299908c | blueswir1 | break;
|
3592 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3593 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3594 | 3299908c | blueswir1 | // XXX
|
3595 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3596 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3597 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3598 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3599 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3600 | a7812ae4 | pbrook | gen_helper_fcmple16(); |
3601 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3602 | e9ebed4d | blueswir1 | break;
|
3603 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3604 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3605 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3606 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3607 | a7812ae4 | pbrook | gen_helper_fcmpne16(); |
3608 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3609 | 3299908c | blueswir1 | break;
|
3610 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3611 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3612 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3613 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3614 | a7812ae4 | pbrook | gen_helper_fcmple32(); |
3615 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3616 | e9ebed4d | blueswir1 | break;
|
3617 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3618 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3619 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3620 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3621 | a7812ae4 | pbrook | gen_helper_fcmpne32(); |
3622 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3623 | e9ebed4d | blueswir1 | break;
|
3624 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3625 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3626 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3627 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3628 | a7812ae4 | pbrook | gen_helper_fcmpgt16(); |
3629 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3630 | e9ebed4d | blueswir1 | break;
|
3631 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3632 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3633 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3634 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3635 | a7812ae4 | pbrook | gen_helper_fcmpeq16(); |
3636 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3637 | e9ebed4d | blueswir1 | break;
|
3638 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3639 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3640 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3641 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3642 | a7812ae4 | pbrook | gen_helper_fcmpgt32(); |
3643 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3644 | e9ebed4d | blueswir1 | break;
|
3645 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3646 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3647 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3648 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3649 | a7812ae4 | pbrook | gen_helper_fcmpeq32(); |
3650 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3651 | e9ebed4d | blueswir1 | break;
|
3652 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3653 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3654 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3655 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3656 | a7812ae4 | pbrook | gen_helper_fmul8x16(); |
3657 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3658 | e9ebed4d | blueswir1 | break;
|
3659 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3660 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3661 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3662 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3663 | a7812ae4 | pbrook | gen_helper_fmul8x16au(); |
3664 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3665 | e9ebed4d | blueswir1 | break;
|
3666 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3667 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3668 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3669 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3670 | a7812ae4 | pbrook | gen_helper_fmul8x16al(); |
3671 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3672 | e9ebed4d | blueswir1 | break;
|
3673 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3674 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3675 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3676 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3677 | a7812ae4 | pbrook | gen_helper_fmul8sux16(); |
3678 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3679 | e9ebed4d | blueswir1 | break;
|
3680 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3681 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3682 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3683 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3684 | a7812ae4 | pbrook | gen_helper_fmul8ulx16(); |
3685 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3686 | e9ebed4d | blueswir1 | break;
|
3687 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3688 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3689 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3690 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3691 | a7812ae4 | pbrook | gen_helper_fmuld8sux16(); |
3692 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3693 | e9ebed4d | blueswir1 | break;
|
3694 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3695 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3696 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3697 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3698 | a7812ae4 | pbrook | gen_helper_fmuld8ulx16(); |
3699 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3700 | e9ebed4d | blueswir1 | break;
|
3701 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3702 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3703 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3704 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3705 | e9ebed4d | blueswir1 | // XXX
|
3706 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3707 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3708 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3709 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3710 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3711 | a7812ae4 | pbrook | gen_helper_faligndata(); |
3712 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3713 | 3299908c | blueswir1 | break;
|
3714 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3715 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3716 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3717 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3718 | a7812ae4 | pbrook | gen_helper_fpmerge(); |
3719 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3720 | e9ebed4d | blueswir1 | break;
|
3721 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3722 | e9ebed4d | blueswir1 | // XXX
|
3723 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3724 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3725 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3726 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3727 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3728 | a7812ae4 | pbrook | gen_helper_fexpand(); |
3729 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3730 | e9ebed4d | blueswir1 | break;
|
3731 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3732 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3733 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3734 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3735 | a7812ae4 | pbrook | gen_helper_fpadd16(); |
3736 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3737 | e9ebed4d | blueswir1 | break;
|
3738 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3739 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3740 | a7812ae4 | pbrook | gen_helper_fpadd16s(cpu_fpr[rd], |
3741 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3742 | e9ebed4d | blueswir1 | break;
|
3743 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3744 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3745 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3746 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3747 | a7812ae4 | pbrook | gen_helper_fpadd32(); |
3748 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3749 | e9ebed4d | blueswir1 | break;
|
3750 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3751 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3752 | a7812ae4 | pbrook | gen_helper_fpadd32s(cpu_fpr[rd], |
3753 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3754 | e9ebed4d | blueswir1 | break;
|
3755 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3756 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3757 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3758 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3759 | a7812ae4 | pbrook | gen_helper_fpsub16(); |
3760 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3761 | e9ebed4d | blueswir1 | break;
|
3762 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3763 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3764 | a7812ae4 | pbrook | gen_helper_fpsub16s(cpu_fpr[rd], |
3765 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3766 | e9ebed4d | blueswir1 | break;
|
3767 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3768 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3769 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3770 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3771 | a7812ae4 | pbrook | gen_helper_fpsub32(); |
3772 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3773 | e9ebed4d | blueswir1 | break;
|
3774 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3775 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3776 | a7812ae4 | pbrook | gen_helper_fpsub32s(cpu_fpr[rd], |
3777 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3778 | e9ebed4d | blueswir1 | break;
|
3779 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3780 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3781 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
|
3782 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); |
3783 | 3299908c | blueswir1 | break;
|
3784 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3785 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3786 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], 0);
|
3787 | 3299908c | blueswir1 | break;
|
3788 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3789 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3790 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3791 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3792 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3793 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3794 | e9ebed4d | blueswir1 | break;
|
3795 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3796 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3797 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3798 | e9ebed4d | blueswir1 | break;
|
3799 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3800 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3801 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3802 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3803 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3804 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3805 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3806 | e9ebed4d | blueswir1 | break;
|
3807 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3808 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3809 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3810 | e9ebed4d | blueswir1 | break;
|
3811 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3812 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3813 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
3814 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3815 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3816 | e9ebed4d | blueswir1 | break;
|
3817 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3818 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3819 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
3820 | e9ebed4d | blueswir1 | break;
|
3821 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3822 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3823 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3824 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3825 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3826 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
3827 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3828 | e9ebed4d | blueswir1 | break;
|
3829 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3830 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3831 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
3832 | e9ebed4d | blueswir1 | break;
|
3833 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3834 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3835 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3836 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3837 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3838 | e9ebed4d | blueswir1 | break;
|
3839 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3840 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3841 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3842 | e9ebed4d | blueswir1 | break;
|
3843 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3844 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3845 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3846 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3847 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
|
3848 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3849 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3850 | e9ebed4d | blueswir1 | break;
|
3851 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3852 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3853 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3854 | e9ebed4d | blueswir1 | break;
|
3855 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
3856 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3857 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3858 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3859 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3860 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3861 | e9ebed4d | blueswir1 | break;
|
3862 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
3863 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3864 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3865 | e9ebed4d | blueswir1 | break;
|
3866 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
3867 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3868 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3869 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3870 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
|
3871 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3872 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3873 | e9ebed4d | blueswir1 | break;
|
3874 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
3875 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3876 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3877 | e9ebed4d | blueswir1 | break;
|
3878 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
3879 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3880 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
3881 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
3882 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3883 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
3884 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
3885 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3886 | e9ebed4d | blueswir1 | break;
|
3887 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
3888 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3889 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
3890 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
3891 | e9ebed4d | blueswir1 | break;
|
3892 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
3893 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3894 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3895 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
3896 | 1d01299d | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3897 | 3299908c | blueswir1 | break;
|
3898 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
3899 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3900 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3901 | 3299908c | blueswir1 | break;
|
3902 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
3903 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3904 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3905 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3906 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3907 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3908 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3909 | e9ebed4d | blueswir1 | break;
|
3910 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
3911 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3912 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3913 | e9ebed4d | blueswir1 | break;
|
3914 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
3915 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3916 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3917 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3918 | 3299908c | blueswir1 | break;
|
3919 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
3920 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3921 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
3922 | 3299908c | blueswir1 | break;
|
3923 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
3924 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3925 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3926 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3927 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3928 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
3929 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3930 | e9ebed4d | blueswir1 | break;
|
3931 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
3932 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3933 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
3934 | e9ebed4d | blueswir1 | break;
|
3935 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
3936 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3937 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3938 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3939 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
|
3940 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3941 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3942 | e9ebed4d | blueswir1 | break;
|
3943 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
3944 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3945 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3946 | e9ebed4d | blueswir1 | break;
|
3947 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
3948 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3949 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
|
3950 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); |
3951 | 3299908c | blueswir1 | break;
|
3952 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
3953 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3954 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], -1);
|
3955 | 3299908c | blueswir1 | break;
|
3956 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
3957 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
3958 | e9ebed4d | blueswir1 | // XXX
|
3959 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3960 | 3299908c | blueswir1 | default:
|
3961 | 3299908c | blueswir1 | goto illegal_insn;
|
3962 | 3299908c | blueswir1 | } |
3963 | 3299908c | blueswir1 | #else
|
3964 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3965 | 3299908c | blueswir1 | #endif
|
3966 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
3967 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
3968 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3969 | fcc72045 | blueswir1 | #else
|
3970 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3971 | fcc72045 | blueswir1 | #endif
|
3972 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3973 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
3974 | a7812ae4 | pbrook | TCGv_i32 r_const; |
3975 | 2ea815ca | blueswir1 | |
3976 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3977 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3978 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3979 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3980 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
3981 | 0f8a249a | blueswir1 | } else { /* register */ |
3982 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3983 | 0f8a249a | blueswir1 | if (rs2) {
|
3984 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3985 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
3986 | 6f551262 | blueswir1 | } else
|
3987 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
3988 | 3475187d | bellard | } |
3989 | a7812ae4 | pbrook | gen_helper_restore(); |
3990 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
3991 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
3992 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
3993 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
3994 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
3995 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3996 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3997 | 3475187d | bellard | #endif
|
3998 | 0f8a249a | blueswir1 | } else {
|
3999 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4000 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4001 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4002 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4003 | 0f8a249a | blueswir1 | } else { /* register */ |
4004 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4005 | 0f8a249a | blueswir1 | if (rs2) {
|
4006 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4007 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4008 | 6f551262 | blueswir1 | } else
|
4009 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4010 | cf495bcf | bellard | } |
4011 | 0f8a249a | blueswir1 | switch (xop) {
|
4012 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4013 | 0f8a249a | blueswir1 | { |
4014 | a7812ae4 | pbrook | TCGv r_pc; |
4015 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4016 | 2ea815ca | blueswir1 | |
4017 | a7812ae4 | pbrook | r_pc = tcg_const_tl(dc->pc); |
4018 | a7812ae4 | pbrook | gen_movl_TN_reg(rd, r_pc); |
4019 | a7812ae4 | pbrook | tcg_temp_free(r_pc); |
4020 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4021 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4022 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4023 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4024 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4025 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4026 | 0f8a249a | blueswir1 | } |
4027 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4028 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4029 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4030 | 0f8a249a | blueswir1 | { |
4031 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4032 | 2ea815ca | blueswir1 | |
4033 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4034 | 0f8a249a | blueswir1 | goto priv_insn;
|
4035 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4036 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4037 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4038 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4039 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4040 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4041 | a7812ae4 | pbrook | gen_helper_rett(); |
4042 | 0f8a249a | blueswir1 | } |
4043 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4044 | 0f8a249a | blueswir1 | #endif
|
4045 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4046 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
4047 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4048 | a7812ae4 | pbrook | gen_helper_flush(cpu_dst); |
4049 | 0f8a249a | blueswir1 | break;
|
4050 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4051 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4052 | a7812ae4 | pbrook | gen_helper_save(); |
4053 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4054 | 0f8a249a | blueswir1 | break;
|
4055 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4056 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4057 | a7812ae4 | pbrook | gen_helper_restore(); |
4058 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4059 | 0f8a249a | blueswir1 | break;
|
4060 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4061 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4062 | 0f8a249a | blueswir1 | { |
4063 | 0f8a249a | blueswir1 | switch (rd) {
|
4064 | 0f8a249a | blueswir1 | case 0: |
4065 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4066 | 0f8a249a | blueswir1 | goto priv_insn;
|
4067 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4068 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4069 | a7812ae4 | pbrook | gen_helper_done(); |
4070 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4071 | 0f8a249a | blueswir1 | case 1: |
4072 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4073 | 0f8a249a | blueswir1 | goto priv_insn;
|
4074 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4075 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4076 | a7812ae4 | pbrook | gen_helper_retry(); |
4077 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4078 | 0f8a249a | blueswir1 | default:
|
4079 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4080 | 0f8a249a | blueswir1 | } |
4081 | 0f8a249a | blueswir1 | } |
4082 | 0f8a249a | blueswir1 | break;
|
4083 | 0f8a249a | blueswir1 | #endif
|
4084 | 0f8a249a | blueswir1 | default:
|
4085 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4086 | 0f8a249a | blueswir1 | } |
4087 | cf495bcf | bellard | } |
4088 | 0f8a249a | blueswir1 | break;
|
4089 | 0f8a249a | blueswir1 | } |
4090 | 0f8a249a | blueswir1 | break;
|
4091 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4092 | 0f8a249a | blueswir1 | { |
4093 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4094 | 9322a4bf | blueswir1 | |
4095 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4096 | 71817e48 | blueswir1 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
4097 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4098 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4099 | 71817e48 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4100 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4101 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4102 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_addr, cpu_src1, simm); |
4103 | 0f8a249a | blueswir1 | } else { /* register */ |
4104 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4105 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4106 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4107 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
4108 | 6f551262 | blueswir1 | } else
|
4109 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4110 | 0f8a249a | blueswir1 | } |
4111 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4112 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4113 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4114 | 0f8a249a | blueswir1 | switch (xop) {
|
4115 | b89e94af | Blue Swirl | case 0x0: /* ld, V9 lduw, load unsigned word */ |
4116 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4117 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4118 | 0f8a249a | blueswir1 | break;
|
4119 | b89e94af | Blue Swirl | case 0x1: /* ldub, load unsigned byte */ |
4120 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4121 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4122 | 0f8a249a | blueswir1 | break;
|
4123 | b89e94af | Blue Swirl | case 0x2: /* lduh, load unsigned halfword */ |
4124 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4125 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4126 | 0f8a249a | blueswir1 | break;
|
4127 | b89e94af | Blue Swirl | case 0x3: /* ldd, load double word */ |
4128 | 0f8a249a | blueswir1 | if (rd & 1) |
4129 | d4218d99 | blueswir1 | goto illegal_insn;
|
4130 | 1a2fb1c0 | blueswir1 | else {
|
4131 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4132 | 2ea815ca | blueswir1 | |
4133 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4134 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4135 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4136 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4137 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4138 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4139 | 32b6c812 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4140 | 32b6c812 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
4141 | 32b6c812 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
4142 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4143 | 6ae20372 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4144 | 6ae20372 | blueswir1 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
|
4145 | 1a2fb1c0 | blueswir1 | } |
4146 | 0f8a249a | blueswir1 | break;
|
4147 | b89e94af | Blue Swirl | case 0x9: /* ldsb, load signed byte */ |
4148 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4149 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4150 | 0f8a249a | blueswir1 | break;
|
4151 | b89e94af | Blue Swirl | case 0xa: /* ldsh, load signed halfword */ |
4152 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4153 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4154 | 0f8a249a | blueswir1 | break;
|
4155 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4156 | 2ea815ca | blueswir1 | { |
4157 | 2ea815ca | blueswir1 | TCGv r_const; |
4158 | 2ea815ca | blueswir1 | |
4159 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4160 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4161 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4162 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4163 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4164 | 2ea815ca | blueswir1 | } |
4165 | 0f8a249a | blueswir1 | break;
|
4166 | b89e94af | Blue Swirl | case 0x0f: /* swap, swap register with memory. Also |
4167 | 77f193da | blueswir1 | atomically */
|
4168 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4169 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4170 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4171 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4172 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4173 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_val, cpu_tmp0); |
4174 | 0f8a249a | blueswir1 | break;
|
4175 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4176 | b89e94af | Blue Swirl | case 0x10: /* lda, V9 lduwa, load word alternate */ |
4177 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4178 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4179 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4180 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4181 | 0f8a249a | blueswir1 | goto priv_insn;
|
4182 | 6ea4a6c8 | blueswir1 | #endif
|
4183 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4184 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4185 | 0f8a249a | blueswir1 | break;
|
4186 | b89e94af | Blue Swirl | case 0x11: /* lduba, load unsigned byte alternate */ |
4187 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4188 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4189 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4190 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4191 | 0f8a249a | blueswir1 | goto priv_insn;
|
4192 | 0f8a249a | blueswir1 | #endif
|
4193 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4194 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4195 | 0f8a249a | blueswir1 | break;
|
4196 | b89e94af | Blue Swirl | case 0x12: /* lduha, load unsigned halfword alternate */ |
4197 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4198 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4199 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4200 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4201 | 0f8a249a | blueswir1 | goto priv_insn;
|
4202 | 6ea4a6c8 | blueswir1 | #endif
|
4203 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4204 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4205 | 0f8a249a | blueswir1 | break;
|
4206 | b89e94af | Blue Swirl | case 0x13: /* ldda, load double word alternate */ |
4207 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4208 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4209 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4210 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4211 | 0f8a249a | blueswir1 | goto priv_insn;
|
4212 | 3475187d | bellard | #endif
|
4213 | 0f8a249a | blueswir1 | if (rd & 1) |
4214 | d4218d99 | blueswir1 | goto illegal_insn;
|
4215 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4216 | db166940 | blueswir1 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4217 | db166940 | blueswir1 | goto skip_move;
|
4218 | b89e94af | Blue Swirl | case 0x19: /* ldsba, load signed byte alternate */ |
4219 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4220 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4221 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4222 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4223 | 0f8a249a | blueswir1 | goto priv_insn;
|
4224 | 0f8a249a | blueswir1 | #endif
|
4225 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4226 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4227 | 0f8a249a | blueswir1 | break;
|
4228 | b89e94af | Blue Swirl | case 0x1a: /* ldsha, load signed halfword alternate */ |
4229 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4230 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4231 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4232 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4233 | 0f8a249a | blueswir1 | goto priv_insn;
|
4234 | 6ea4a6c8 | blueswir1 | #endif
|
4235 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4236 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4237 | 0f8a249a | blueswir1 | break;
|
4238 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4239 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4240 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4241 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4242 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4243 | 0f8a249a | blueswir1 | goto priv_insn;
|
4244 | 0f8a249a | blueswir1 | #endif
|
4245 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4246 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4247 | 0f8a249a | blueswir1 | break;
|
4248 | b89e94af | Blue Swirl | case 0x1f: /* swapa, swap reg with alt. memory. Also |
4249 | 77f193da | blueswir1 | atomically */
|
4250 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4251 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4252 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4253 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4254 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4255 | 0f8a249a | blueswir1 | goto priv_insn;
|
4256 | 6ea4a6c8 | blueswir1 | #endif
|
4257 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4258 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4259 | 6ae20372 | blueswir1 | gen_swap_asi(cpu_val, cpu_addr, insn); |
4260 | 0f8a249a | blueswir1 | break;
|
4261 | 3475187d | bellard | |
4262 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4263 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4264 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4265 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4266 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4267 | 3475187d | bellard | #endif
|
4268 | 3475187d | bellard | #endif
|
4269 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4270 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4271 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4272 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4273 | 0f8a249a | blueswir1 | break;
|
4274 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4275 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4276 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4277 | 0f8a249a | blueswir1 | break;
|
4278 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4279 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4280 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4281 | 0f8a249a | blueswir1 | break;
|
4282 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4283 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4284 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4285 | 0f8a249a | blueswir1 | break;
|
4286 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4287 | 0f8a249a | blueswir1 | goto skip_move;
|
4288 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4289 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4290 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4291 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4292 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4293 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4294 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4295 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4296 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4297 | 0f8a249a | blueswir1 | goto skip_move;
|
4298 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4299 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4300 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4301 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4302 | 1f587329 | blueswir1 | goto skip_move;
|
4303 | 1f587329 | blueswir1 | #endif
|
4304 | 0f8a249a | blueswir1 | default:
|
4305 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4306 | 0f8a249a | blueswir1 | } |
4307 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4308 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4309 | 0f8a249a | blueswir1 | skip_move: ;
|
4310 | 3475187d | bellard | #endif
|
4311 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4312 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4313 | a80dde08 | bellard | goto jmp_insn;
|
4314 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4315 | 0f8a249a | blueswir1 | switch (xop) {
|
4316 | b89e94af | Blue Swirl | case 0x20: /* ldf, load fpreg */ |
4317 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4318 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4319 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); |
4320 | 0f8a249a | blueswir1 | break;
|
4321 | 3a3b925d | blueswir1 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4322 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4323 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4324 | 3a3b925d | blueswir1 | if (rd == 1) { |
4325 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4326 | a7812ae4 | pbrook | gen_helper_ldxfsr(cpu_tmp64); |
4327 | 3a3b925d | blueswir1 | } else
|
4328 | 3a3b925d | blueswir1 | #else
|
4329 | 3a3b925d | blueswir1 | { |
4330 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4331 | a7812ae4 | pbrook | gen_helper_ldfsr(cpu_tmp32); |
4332 | 3a3b925d | blueswir1 | } |
4333 | 3a3b925d | blueswir1 | #endif
|
4334 | 0f8a249a | blueswir1 | break;
|
4335 | b89e94af | Blue Swirl | case 0x22: /* ldqf, load quad fpreg */ |
4336 | 2ea815ca | blueswir1 | { |
4337 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4338 | 2ea815ca | blueswir1 | |
4339 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4340 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4341 | a7812ae4 | pbrook | gen_helper_ldqf(cpu_addr, r_const); |
4342 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4343 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4344 | 2ea815ca | blueswir1 | } |
4345 | 1f587329 | blueswir1 | break;
|
4346 | b89e94af | Blue Swirl | case 0x23: /* lddf, load double fpreg */ |
4347 | 2ea815ca | blueswir1 | { |
4348 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4349 | 2ea815ca | blueswir1 | |
4350 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4351 | a7812ae4 | pbrook | gen_helper_lddf(cpu_addr, r_const); |
4352 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4353 | 2ea815ca | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4354 | 2ea815ca | blueswir1 | } |
4355 | 0f8a249a | blueswir1 | break;
|
4356 | 0f8a249a | blueswir1 | default:
|
4357 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4358 | 0f8a249a | blueswir1 | } |
4359 | dc1a6971 | Blue Swirl | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || |
4360 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4361 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4362 | 0f8a249a | blueswir1 | switch (xop) {
|
4363 | b89e94af | Blue Swirl | case 0x4: /* st, store word */ |
4364 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4365 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4366 | 0f8a249a | blueswir1 | break;
|
4367 | b89e94af | Blue Swirl | case 0x5: /* stb, store byte */ |
4368 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4369 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4370 | 0f8a249a | blueswir1 | break;
|
4371 | b89e94af | Blue Swirl | case 0x6: /* sth, store halfword */ |
4372 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4373 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4374 | 0f8a249a | blueswir1 | break;
|
4375 | b89e94af | Blue Swirl | case 0x7: /* std, store double word */ |
4376 | 0f8a249a | blueswir1 | if (rd & 1) |
4377 | d4218d99 | blueswir1 | goto illegal_insn;
|
4378 | 1a2fb1c0 | blueswir1 | else {
|
4379 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4380 | 1a2fb1c0 | blueswir1 | |
4381 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4382 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4383 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4384 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4385 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4386 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
4387 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val); |
4388 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4389 | 7fa76c0b | blueswir1 | } |
4390 | 0f8a249a | blueswir1 | break;
|
4391 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4392 | b89e94af | Blue Swirl | case 0x14: /* sta, V9 stwa, store word alternate */ |
4393 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4394 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4395 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4396 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4397 | 0f8a249a | blueswir1 | goto priv_insn;
|
4398 | 3475187d | bellard | #endif
|
4399 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4400 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4401 | d39c0b99 | bellard | break;
|
4402 | b89e94af | Blue Swirl | case 0x15: /* stba, store byte alternate */ |
4403 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4404 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4405 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4406 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4407 | 0f8a249a | blueswir1 | goto priv_insn;
|
4408 | 3475187d | bellard | #endif
|
4409 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4410 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4411 | d39c0b99 | bellard | break;
|
4412 | b89e94af | Blue Swirl | case 0x16: /* stha, store halfword alternate */ |
4413 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4414 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4415 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4416 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4417 | 0f8a249a | blueswir1 | goto priv_insn;
|
4418 | 3475187d | bellard | #endif
|
4419 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4420 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4421 | d39c0b99 | bellard | break;
|
4422 | b89e94af | Blue Swirl | case 0x17: /* stda, store double word alternate */ |
4423 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4424 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4425 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4426 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4427 | 0f8a249a | blueswir1 | goto priv_insn;
|
4428 | 3475187d | bellard | #endif
|
4429 | 0f8a249a | blueswir1 | if (rd & 1) |
4430 | d4218d99 | blueswir1 | goto illegal_insn;
|
4431 | 1a2fb1c0 | blueswir1 | else {
|
4432 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4433 | 6ae20372 | blueswir1 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
4434 | 1a2fb1c0 | blueswir1 | } |
4435 | d39c0b99 | bellard | break;
|
4436 | e80cfcfc | bellard | #endif
|
4437 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4438 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4439 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4440 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
4441 | 0f8a249a | blueswir1 | break;
|
4442 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4443 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4444 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
4445 | 0f8a249a | blueswir1 | break;
|
4446 | 3475187d | bellard | #endif
|
4447 | 0f8a249a | blueswir1 | default:
|
4448 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4449 | 0f8a249a | blueswir1 | } |
4450 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4451 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4452 | a80dde08 | bellard | goto jmp_insn;
|
4453 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4454 | 0f8a249a | blueswir1 | switch (xop) {
|
4455 | b89e94af | Blue Swirl | case 0x24: /* stf, store fpreg */ |
4456 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4457 | 527067d8 | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); |
4458 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); |
4459 | 0f8a249a | blueswir1 | break;
|
4460 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4461 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4462 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4463 | 3a3b925d | blueswir1 | tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); |
4464 | 3a3b925d | blueswir1 | if (rd == 1) |
4465 | 3a3b925d | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4466 | 527067d8 | blueswir1 | else
|
4467 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx); |
4468 | 3a3b925d | blueswir1 | #else
|
4469 | 3a3b925d | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); |
4470 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4471 | 3a3b925d | blueswir1 | #endif
|
4472 | 0f8a249a | blueswir1 | break;
|
4473 | 1f587329 | blueswir1 | case 0x26: |
4474 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4475 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4476 | 2ea815ca | blueswir1 | { |
4477 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4478 | 2ea815ca | blueswir1 | |
4479 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4480 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4481 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4482 | a7812ae4 | pbrook | gen_helper_stqf(cpu_addr, r_const); |
4483 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4484 | 2ea815ca | blueswir1 | } |
4485 | 1f587329 | blueswir1 | break;
|
4486 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4487 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4488 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4489 | 1f587329 | blueswir1 | goto illegal_insn;
|
4490 | 1f587329 | blueswir1 | #else
|
4491 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4492 | 0f8a249a | blueswir1 | goto priv_insn;
|
4493 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4494 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4495 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4496 | 0f8a249a | blueswir1 | #endif
|
4497 | 1f587329 | blueswir1 | #endif
|
4498 | b89e94af | Blue Swirl | case 0x27: /* stdf, store double fpreg */ |
4499 | 2ea815ca | blueswir1 | { |
4500 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4501 | 2ea815ca | blueswir1 | |
4502 | 2ea815ca | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4503 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4504 | a7812ae4 | pbrook | gen_helper_stdf(cpu_addr, r_const); |
4505 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4506 | 2ea815ca | blueswir1 | } |
4507 | 0f8a249a | blueswir1 | break;
|
4508 | 0f8a249a | blueswir1 | default:
|
4509 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4510 | 0f8a249a | blueswir1 | } |
4511 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4512 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4513 | 0f8a249a | blueswir1 | switch (xop) {
|
4514 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4515 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4516 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
4517 | 0f8a249a | blueswir1 | break;
|
4518 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4519 | 2ea815ca | blueswir1 | { |
4520 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4521 | 2ea815ca | blueswir1 | |
4522 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4523 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4524 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); |
4525 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4526 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4527 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4528 | 2ea815ca | blueswir1 | } |
4529 | 1f587329 | blueswir1 | break;
|
4530 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4531 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4532 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4533 | 0f8a249a | blueswir1 | break;
|
4534 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4535 | 71817e48 | blueswir1 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4536 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4537 | 0f8a249a | blueswir1 | break;
|
4538 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4539 | 71817e48 | blueswir1 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4540 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4541 | 0f8a249a | blueswir1 | break;
|
4542 | a4d17f19 | blueswir1 | #else
|
4543 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4544 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4545 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4546 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4547 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4548 | 0f8a249a | blueswir1 | #endif
|
4549 | 0f8a249a | blueswir1 | default:
|
4550 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4551 | 0f8a249a | blueswir1 | } |
4552 | dc1a6971 | Blue Swirl | } else
|
4553 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4554 | 0f8a249a | blueswir1 | } |
4555 | 0f8a249a | blueswir1 | break;
|
4556 | cf495bcf | bellard | } |
4557 | cf495bcf | bellard | /* default case for non jump instructions */
|
4558 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4559 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4560 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4561 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4562 | 72cbca10 | bellard | /* we can do a static jump */
|
4563 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
4564 | 72cbca10 | bellard | dc->is_br = 1;
|
4565 | 72cbca10 | bellard | } else {
|
4566 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4567 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4568 | cf495bcf | bellard | } |
4569 | e80cfcfc | bellard | jmp_insn:
|
4570 | cf495bcf | bellard | return;
|
4571 | cf495bcf | bellard | illegal_insn:
|
4572 | 2ea815ca | blueswir1 | { |
4573 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4574 | 2ea815ca | blueswir1 | |
4575 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4576 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
4577 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4578 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4579 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4580 | 2ea815ca | blueswir1 | } |
4581 | e8af50a3 | bellard | return;
|
4582 | 64a88d5d | blueswir1 | unimp_flush:
|
4583 | 2ea815ca | blueswir1 | { |
4584 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4585 | 2ea815ca | blueswir1 | |
4586 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4587 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
4588 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4589 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4590 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4591 | 2ea815ca | blueswir1 | } |
4592 | 64a88d5d | blueswir1 | return;
|
4593 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4594 | e8af50a3 | bellard | priv_insn:
|
4595 | 2ea815ca | blueswir1 | { |
4596 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4597 | 2ea815ca | blueswir1 | |
4598 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4599 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
4600 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4601 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4602 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4603 | 2ea815ca | blueswir1 | } |
4604 | e80cfcfc | bellard | return;
|
4605 | 64a88d5d | blueswir1 | #endif
|
4606 | e80cfcfc | bellard | nfpu_insn:
|
4607 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4608 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4609 | e80cfcfc | bellard | dc->is_br = 1;
|
4610 | fcc72045 | blueswir1 | return;
|
4611 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4612 | 9143e598 | blueswir1 | nfq_insn:
|
4613 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4614 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4615 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4616 | 9143e598 | blueswir1 | return;
|
4617 | 9143e598 | blueswir1 | #endif
|
4618 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4619 | fcc72045 | blueswir1 | ncp_insn:
|
4620 | 2ea815ca | blueswir1 | { |
4621 | 2ea815ca | blueswir1 | TCGv r_const; |
4622 | 2ea815ca | blueswir1 | |
4623 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4624 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
4625 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4626 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4627 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4628 | 2ea815ca | blueswir1 | } |
4629 | fcc72045 | blueswir1 | return;
|
4630 | fcc72045 | blueswir1 | #endif
|
4631 | 7a3f1944 | bellard | } |
4632 | 7a3f1944 | bellard | |
4633 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4634 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
4635 | 7a3f1944 | bellard | { |
4636 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4637 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4638 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4639 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
4640 | e8af50a3 | bellard | int j, lj = -1; |
4641 | 2e70f6ef | pbrook | int num_insns;
|
4642 | 2e70f6ef | pbrook | int max_insns;
|
4643 | cf495bcf | bellard | |
4644 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4645 | cf495bcf | bellard | dc->tb = tb; |
4646 | 72cbca10 | bellard | pc_start = tb->pc; |
4647 | cf495bcf | bellard | dc->pc = pc_start; |
4648 | e80cfcfc | bellard | last_pc = dc->pc; |
4649 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4650 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_DYNAMIC; |
4651 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4652 | 5578ceab | blueswir1 | dc->def = env->def; |
4653 | 5578ceab | blueswir1 | if ((dc->def->features & CPU_FEATURE_FLOAT))
|
4654 | 64a88d5d | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4655 | 5578ceab | blueswir1 | else
|
4656 | 64a88d5d | blueswir1 | dc->fpu_enabled = 0;
|
4657 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
4658 | 2cade6a3 | blueswir1 | dc->address_mask_32bit = env->pstate & PS_AM; |
4659 | 2cade6a3 | blueswir1 | #endif
|
4660 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4661 | cf495bcf | bellard | |
4662 | a7812ae4 | pbrook | cpu_tmp0 = tcg_temp_new(); |
4663 | a7812ae4 | pbrook | cpu_tmp32 = tcg_temp_new_i32(); |
4664 | a7812ae4 | pbrook | cpu_tmp64 = tcg_temp_new_i64(); |
4665 | d987963a | blueswir1 | |
4666 | a7812ae4 | pbrook | cpu_dst = tcg_temp_local_new(); |
4667 | d987963a | blueswir1 | |
4668 | d987963a | blueswir1 | // loads and stores
|
4669 | a7812ae4 | pbrook | cpu_val = tcg_temp_local_new(); |
4670 | a7812ae4 | pbrook | cpu_addr = tcg_temp_local_new(); |
4671 | 1a2fb1c0 | blueswir1 | |
4672 | 2e70f6ef | pbrook | num_insns = 0;
|
4673 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
4674 | 2e70f6ef | pbrook | if (max_insns == 0) |
4675 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
4676 | 2e70f6ef | pbrook | gen_icount_start(); |
4677 | cf495bcf | bellard | do {
|
4678 | c0ce998e | aliguori | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
4679 | c0ce998e | aliguori | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
4680 | a1d1bb31 | aliguori | if (bp->pc == dc->pc) {
|
4681 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4682 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4683 | a7812ae4 | pbrook | gen_helper_debug(); |
4684 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4685 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4686 | e80cfcfc | bellard | goto exit_gen_loop;
|
4687 | e8af50a3 | bellard | } |
4688 | e8af50a3 | bellard | } |
4689 | e8af50a3 | bellard | } |
4690 | e8af50a3 | bellard | if (spc) {
|
4691 | 93fcfe39 | aliguori | qemu_log("Search PC...\n");
|
4692 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4693 | e8af50a3 | bellard | if (lj < j) {
|
4694 | e8af50a3 | bellard | lj++; |
4695 | e8af50a3 | bellard | while (lj < j)
|
4696 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4697 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4698 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4699 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4700 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
4701 | e8af50a3 | bellard | } |
4702 | e8af50a3 | bellard | } |
4703 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4704 | 2e70f6ef | pbrook | gen_io_start(); |
4705 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4706 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4707 | 2e70f6ef | pbrook | num_insns++; |
4708 | 0f8a249a | blueswir1 | |
4709 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4710 | 0f8a249a | blueswir1 | break;
|
4711 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4712 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4713 | 0f8a249a | blueswir1 | break;
|
4714 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4715 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4716 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4717 | d39c0b99 | bellard | break;
|
4718 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4719 | e80cfcfc | bellard | generate an exception */
|
4720 | 1b530a6d | aurel32 | if (env->singlestep_enabled || singlestep) {
|
4721 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4722 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4723 | e80cfcfc | bellard | break;
|
4724 | e80cfcfc | bellard | } |
4725 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4726 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
4727 | 2e70f6ef | pbrook | num_insns < max_insns); |
4728 | e80cfcfc | bellard | |
4729 | e80cfcfc | bellard | exit_gen_loop:
|
4730 | d987963a | blueswir1 | tcg_temp_free(cpu_addr); |
4731 | 3f0436fe | blueswir1 | tcg_temp_free(cpu_val); |
4732 | d987963a | blueswir1 | tcg_temp_free(cpu_dst); |
4733 | a7812ae4 | pbrook | tcg_temp_free_i64(cpu_tmp64); |
4734 | a7812ae4 | pbrook | tcg_temp_free_i32(cpu_tmp32); |
4735 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp0); |
4736 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
4737 | 2e70f6ef | pbrook | gen_io_end(); |
4738 | 72cbca10 | bellard | if (!dc->is_br) {
|
4739 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4740 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4741 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4742 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
4743 | 72cbca10 | bellard | } else {
|
4744 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4745 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4746 | 6ae20372 | blueswir1 | save_npc(dc, cpu_cond); |
4747 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4748 | 72cbca10 | bellard | } |
4749 | 72cbca10 | bellard | } |
4750 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
4751 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4752 | e8af50a3 | bellard | if (spc) {
|
4753 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4754 | e8af50a3 | bellard | lj++; |
4755 | e8af50a3 | bellard | while (lj <= j)
|
4756 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4757 | e8af50a3 | bellard | #if 0
|
4758 | 93fcfe39 | aliguori | log_page_dump();
|
4759 | e8af50a3 | bellard | #endif
|
4760 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4761 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4762 | e8af50a3 | bellard | } else {
|
4763 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4764 | 2e70f6ef | pbrook | tb->icount = num_insns; |
4765 | e8af50a3 | bellard | } |
4766 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4767 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
4768 | 93fcfe39 | aliguori | qemu_log("--------------\n");
|
4769 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
4770 | 93fcfe39 | aliguori | log_target_disas(pc_start, last_pc + 4 - pc_start, 0); |
4771 | 93fcfe39 | aliguori | qemu_log("\n");
|
4772 | cf495bcf | bellard | } |
4773 | 7a3f1944 | bellard | #endif
|
4774 | 7a3f1944 | bellard | } |
4775 | 7a3f1944 | bellard | |
4776 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4777 | 7a3f1944 | bellard | { |
4778 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
4779 | 7a3f1944 | bellard | } |
4780 | 7a3f1944 | bellard | |
4781 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4782 | 7a3f1944 | bellard | { |
4783 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
4784 | 7a3f1944 | bellard | } |
4785 | 7a3f1944 | bellard | |
4786 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
4787 | e80cfcfc | bellard | { |
4788 | f5069b26 | blueswir1 | unsigned int i; |
4789 | c48fcb47 | blueswir1 | static int inited; |
4790 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4791 | f5069b26 | blueswir1 | NULL, // g0 not used |
4792 | f5069b26 | blueswir1 | "g1",
|
4793 | f5069b26 | blueswir1 | "g2",
|
4794 | f5069b26 | blueswir1 | "g3",
|
4795 | f5069b26 | blueswir1 | "g4",
|
4796 | f5069b26 | blueswir1 | "g5",
|
4797 | f5069b26 | blueswir1 | "g6",
|
4798 | f5069b26 | blueswir1 | "g7",
|
4799 | f5069b26 | blueswir1 | }; |
4800 | 714547bb | blueswir1 | static const char * const fregnames[64] = { |
4801 | 714547bb | blueswir1 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
4802 | 714547bb | blueswir1 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
4803 | 714547bb | blueswir1 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
4804 | 714547bb | blueswir1 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
4805 | 714547bb | blueswir1 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
4806 | 714547bb | blueswir1 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
4807 | 714547bb | blueswir1 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
4808 | 714547bb | blueswir1 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
4809 | 714547bb | blueswir1 | }; |
4810 | aaed909a | bellard | |
4811 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4812 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4813 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4814 | 1a2fb1c0 | blueswir1 | |
4815 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
4816 | a7812ae4 | pbrook | cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0, |
4817 | a7812ae4 | pbrook | offsetof(CPUState, regwptr), |
4818 | a7812ae4 | pbrook | "regwptr");
|
4819 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4820 | a7812ae4 | pbrook | cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc), |
4821 | a7812ae4 | pbrook | "xcc");
|
4822 | a7812ae4 | pbrook | cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi), |
4823 | a7812ae4 | pbrook | "asi");
|
4824 | a7812ae4 | pbrook | cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs), |
4825 | a7812ae4 | pbrook | "fprs");
|
4826 | a7812ae4 | pbrook | cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr), |
4827 | 255e1fcb | blueswir1 | "gsr");
|
4828 | a7812ae4 | pbrook | cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4829 | 255e1fcb | blueswir1 | offsetof(CPUState, tick_cmpr), |
4830 | 255e1fcb | blueswir1 | "tick_cmpr");
|
4831 | a7812ae4 | pbrook | cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4832 | 255e1fcb | blueswir1 | offsetof(CPUState, stick_cmpr), |
4833 | 255e1fcb | blueswir1 | "stick_cmpr");
|
4834 | a7812ae4 | pbrook | cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4835 | 255e1fcb | blueswir1 | offsetof(CPUState, hstick_cmpr), |
4836 | 255e1fcb | blueswir1 | "hstick_cmpr");
|
4837 | a7812ae4 | pbrook | cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp), |
4838 | 255e1fcb | blueswir1 | "hintp");
|
4839 | a7812ae4 | pbrook | cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba), |
4840 | a7812ae4 | pbrook | "htba");
|
4841 | a7812ae4 | pbrook | cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver), |
4842 | a7812ae4 | pbrook | "hver");
|
4843 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new(TCG_AREG0, |
4844 | 255e1fcb | blueswir1 | offsetof(CPUState, ssr), "ssr");
|
4845 | a7812ae4 | pbrook | cpu_ver = tcg_global_mem_new(TCG_AREG0, |
4846 | 255e1fcb | blueswir1 | offsetof(CPUState, version), "ver");
|
4847 | a7812ae4 | pbrook | cpu_softint = tcg_global_mem_new_i32(TCG_AREG0, |
4848 | a7812ae4 | pbrook | offsetof(CPUState, softint), |
4849 | a7812ae4 | pbrook | "softint");
|
4850 | 255e1fcb | blueswir1 | #else
|
4851 | a7812ae4 | pbrook | cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim), |
4852 | 255e1fcb | blueswir1 | "wim");
|
4853 | 1a2fb1c0 | blueswir1 | #endif
|
4854 | a7812ae4 | pbrook | cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond), |
4855 | 77f193da | blueswir1 | "cond");
|
4856 | a7812ae4 | pbrook | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), |
4857 | dc99a3f2 | blueswir1 | "cc_src");
|
4858 | a7812ae4 | pbrook | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, |
4859 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
4860 | d9bdab86 | blueswir1 | "cc_src2");
|
4861 | a7812ae4 | pbrook | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), |
4862 | dc99a3f2 | blueswir1 | "cc_dst");
|
4863 | 8393617c | Blue Swirl | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op), |
4864 | 8393617c | Blue Swirl | "cc_op");
|
4865 | a7812ae4 | pbrook | cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr), |
4866 | a7812ae4 | pbrook | "psr");
|
4867 | a7812ae4 | pbrook | cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr), |
4868 | 87e92502 | blueswir1 | "fsr");
|
4869 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc), |
4870 | 48d5c82b | blueswir1 | "pc");
|
4871 | a7812ae4 | pbrook | cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc), |
4872 | a7812ae4 | pbrook | "npc");
|
4873 | a7812ae4 | pbrook | cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
|
4874 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
4875 | a7812ae4 | pbrook | cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr), |
4876 | 255e1fcb | blueswir1 | "tbr");
|
4877 | 255e1fcb | blueswir1 | #endif
|
4878 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
4879 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0, |
4880 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
4881 | f5069b26 | blueswir1 | gregnames[i]); |
4882 | 714547bb | blueswir1 | for (i = 0; i < TARGET_FPREGS; i++) |
4883 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, |
4884 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), |
4885 | a7812ae4 | pbrook | fregnames[i]); |
4886 | 714547bb | blueswir1 | |
4887 | c9e03d8f | blueswir1 | /* register helpers */
|
4888 | c9e03d8f | blueswir1 | |
4889 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
4890 | c9e03d8f | blueswir1 | #include "helper.h" |
4891 | 1a2fb1c0 | blueswir1 | } |
4892 | 658138bc | bellard | } |
4893 | d2856f1a | aurel32 | |
4894 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
4895 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
4896 | d2856f1a | aurel32 | { |
4897 | d2856f1a | aurel32 | target_ulong npc; |
4898 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
4899 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
4900 | d2856f1a | aurel32 | if (npc == 1) { |
4901 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
|
4902 | d2856f1a | aurel32 | } else if (npc == 2) { |
4903 | d2856f1a | aurel32 | target_ulong t2 = (target_ulong)(unsigned long)puc; |
4904 | d2856f1a | aurel32 | /* jump PC: use T2 and the jump targets of the translation */
|
4905 | d2856f1a | aurel32 | if (t2)
|
4906 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
|
4907 | d2856f1a | aurel32 | else
|
4908 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
|
4909 | d2856f1a | aurel32 | } else {
|
4910 | d2856f1a | aurel32 | env->npc = npc; |
4911 | d2856f1a | aurel32 | } |
4912 | d2856f1a | aurel32 | } |