root / hw / a9mpcore.c @ 2558e0a6
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1 | f7c70325 | Paul Brook | /*
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2 | f7c70325 | Paul Brook | * Cortex-A9MPCore internal peripheral emulation.
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3 | f7c70325 | Paul Brook | *
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4 | f7c70325 | Paul Brook | * Copyright (c) 2009 CodeSourcery.
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5 | b12080cd | Peter Maydell | * Copyright (c) 2011 Linaro Limited.
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6 | b12080cd | Peter Maydell | * Written by Paul Brook, Peter Maydell.
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7 | f7c70325 | Paul Brook | *
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8 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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9 | f7c70325 | Paul Brook | */
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10 | f7c70325 | Paul Brook | |
11 | b12080cd | Peter Maydell | #include "sysbus.h" |
12 | b12080cd | Peter Maydell | |
13 | b12080cd | Peter Maydell | /* Configuration for arm_gic.c:
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14 | a32134aa | Mark Langsdorf | * max number of CPUs, how to ID current CPU
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15 | b12080cd | Peter Maydell | */
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16 | b12080cd | Peter Maydell | #define NCPU 4 |
17 | b12080cd | Peter Maydell | |
18 | b12080cd | Peter Maydell | static inline int |
19 | b12080cd | Peter Maydell | gic_get_current_cpu(void)
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20 | b12080cd | Peter Maydell | { |
21 | b12080cd | Peter Maydell | return cpu_single_env->cpu_index;
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22 | b12080cd | Peter Maydell | } |
23 | b12080cd | Peter Maydell | |
24 | b12080cd | Peter Maydell | #include "arm_gic.c" |
25 | b12080cd | Peter Maydell | |
26 | b12080cd | Peter Maydell | /* A9MP private memory region. */
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27 | b12080cd | Peter Maydell | |
28 | b12080cd | Peter Maydell | typedef struct a9mp_priv_state { |
29 | b12080cd | Peter Maydell | gic_state gic; |
30 | b12080cd | Peter Maydell | uint32_t scu_control; |
31 | 78aca8a7 | Rob Herring | uint32_t scu_status; |
32 | b12080cd | Peter Maydell | uint32_t old_timer_status[8];
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33 | b12080cd | Peter Maydell | uint32_t num_cpu; |
34 | b12080cd | Peter Maydell | qemu_irq *timer_irq; |
35 | b12080cd | Peter Maydell | MemoryRegion scu_iomem; |
36 | b12080cd | Peter Maydell | MemoryRegion ptimer_iomem; |
37 | b12080cd | Peter Maydell | MemoryRegion container; |
38 | b12080cd | Peter Maydell | DeviceState *mptimer; |
39 | a32134aa | Mark Langsdorf | uint32_t num_irq; |
40 | b12080cd | Peter Maydell | } a9mp_priv_state; |
41 | b12080cd | Peter Maydell | |
42 | b12080cd | Peter Maydell | static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset, |
43 | b12080cd | Peter Maydell | unsigned size)
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44 | b12080cd | Peter Maydell | { |
45 | b12080cd | Peter Maydell | a9mp_priv_state *s = (a9mp_priv_state *)opaque; |
46 | b12080cd | Peter Maydell | switch (offset) {
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47 | b12080cd | Peter Maydell | case 0x00: /* Control */ |
48 | b12080cd | Peter Maydell | return s->scu_control;
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49 | b12080cd | Peter Maydell | case 0x04: /* Configuration */ |
50 | b12080cd | Peter Maydell | return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); |
51 | b12080cd | Peter Maydell | case 0x08: /* CPU Power Status */ |
52 | 78aca8a7 | Rob Herring | return s->scu_status;
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53 | 78aca8a7 | Rob Herring | case 0x09: /* CPU status. */ |
54 | 78aca8a7 | Rob Herring | return s->scu_status >> 8; |
55 | 78aca8a7 | Rob Herring | case 0x0a: /* CPU status. */ |
56 | 78aca8a7 | Rob Herring | return s->scu_status >> 16; |
57 | 78aca8a7 | Rob Herring | case 0x0b: /* CPU status. */ |
58 | 78aca8a7 | Rob Herring | return s->scu_status >> 24; |
59 | b12080cd | Peter Maydell | case 0x0c: /* Invalidate All Registers In Secure State */ |
60 | b12080cd | Peter Maydell | return 0; |
61 | b12080cd | Peter Maydell | case 0x40: /* Filtering Start Address Register */ |
62 | b12080cd | Peter Maydell | case 0x44: /* Filtering End Address Register */ |
63 | b12080cd | Peter Maydell | /* RAZ/WI, like an implementation with only one AXI master */
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64 | b12080cd | Peter Maydell | return 0; |
65 | b12080cd | Peter Maydell | case 0x50: /* SCU Access Control Register */ |
66 | b12080cd | Peter Maydell | case 0x54: /* SCU Non-secure Access Control Register */ |
67 | b12080cd | Peter Maydell | /* unimplemented, fall through */
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68 | b12080cd | Peter Maydell | default:
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69 | b12080cd | Peter Maydell | return 0; |
70 | b12080cd | Peter Maydell | } |
71 | b12080cd | Peter Maydell | } |
72 | b12080cd | Peter Maydell | |
73 | b12080cd | Peter Maydell | static void a9_scu_write(void *opaque, target_phys_addr_t offset, |
74 | b12080cd | Peter Maydell | uint64_t value, unsigned size)
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75 | b12080cd | Peter Maydell | { |
76 | b12080cd | Peter Maydell | a9mp_priv_state *s = (a9mp_priv_state *)opaque; |
77 | 78aca8a7 | Rob Herring | uint32_t mask; |
78 | 78aca8a7 | Rob Herring | uint32_t shift; |
79 | 78aca8a7 | Rob Herring | switch (size) {
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80 | 78aca8a7 | Rob Herring | case 1: |
81 | 78aca8a7 | Rob Herring | mask = 0xff;
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82 | 78aca8a7 | Rob Herring | break;
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83 | 78aca8a7 | Rob Herring | case 2: |
84 | 78aca8a7 | Rob Herring | mask = 0xffff;
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85 | 78aca8a7 | Rob Herring | break;
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86 | 78aca8a7 | Rob Herring | case 4: |
87 | 78aca8a7 | Rob Herring | mask = 0xffffffff;
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88 | 78aca8a7 | Rob Herring | break;
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89 | 78aca8a7 | Rob Herring | default:
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90 | 78aca8a7 | Rob Herring | fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
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91 | 78aca8a7 | Rob Herring | size, offset); |
92 | 78aca8a7 | Rob Herring | return;
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93 | 78aca8a7 | Rob Herring | } |
94 | 78aca8a7 | Rob Herring | |
95 | b12080cd | Peter Maydell | switch (offset) {
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96 | b12080cd | Peter Maydell | case 0x00: /* Control */ |
97 | b12080cd | Peter Maydell | s->scu_control = value & 1;
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98 | b12080cd | Peter Maydell | break;
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99 | b12080cd | Peter Maydell | case 0x4: /* Configuration: RO */ |
100 | b12080cd | Peter Maydell | break;
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101 | 78aca8a7 | Rob Herring | case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ |
102 | 78aca8a7 | Rob Herring | shift = (offset - 0x8) * 8; |
103 | 78aca8a7 | Rob Herring | s->scu_status &= ~(mask << shift); |
104 | 78aca8a7 | Rob Herring | s->scu_status |= ((value & mask) << shift); |
105 | 78aca8a7 | Rob Herring | break;
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106 | b12080cd | Peter Maydell | case 0x0c: /* Invalidate All Registers In Secure State */ |
107 | b12080cd | Peter Maydell | /* no-op as we do not implement caches */
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108 | b12080cd | Peter Maydell | break;
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109 | b12080cd | Peter Maydell | case 0x40: /* Filtering Start Address Register */ |
110 | b12080cd | Peter Maydell | case 0x44: /* Filtering End Address Register */ |
111 | b12080cd | Peter Maydell | /* RAZ/WI, like an implementation with only one AXI master */
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112 | b12080cd | Peter Maydell | break;
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113 | b12080cd | Peter Maydell | case 0x50: /* SCU Access Control Register */ |
114 | b12080cd | Peter Maydell | case 0x54: /* SCU Non-secure Access Control Register */ |
115 | b12080cd | Peter Maydell | /* unimplemented, fall through */
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116 | b12080cd | Peter Maydell | default:
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117 | b12080cd | Peter Maydell | break;
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118 | b12080cd | Peter Maydell | } |
119 | b12080cd | Peter Maydell | } |
120 | b12080cd | Peter Maydell | |
121 | b12080cd | Peter Maydell | static const MemoryRegionOps a9_scu_ops = { |
122 | b12080cd | Peter Maydell | .read = a9_scu_read, |
123 | b12080cd | Peter Maydell | .write = a9_scu_write, |
124 | b12080cd | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
125 | b12080cd | Peter Maydell | }; |
126 | b12080cd | Peter Maydell | |
127 | b12080cd | Peter Maydell | static void a9mpcore_timer_irq_handler(void *opaque, int irq, int level) |
128 | b12080cd | Peter Maydell | { |
129 | b12080cd | Peter Maydell | a9mp_priv_state *s = (a9mp_priv_state *)opaque; |
130 | b12080cd | Peter Maydell | if (level && !s->old_timer_status[irq]) {
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131 | b12080cd | Peter Maydell | gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1)); |
132 | b12080cd | Peter Maydell | } |
133 | b12080cd | Peter Maydell | s->old_timer_status[irq] = level; |
134 | b12080cd | Peter Maydell | } |
135 | b12080cd | Peter Maydell | |
136 | b12080cd | Peter Maydell | static void a9mp_priv_reset(DeviceState *dev) |
137 | b12080cd | Peter Maydell | { |
138 | b12080cd | Peter Maydell | a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, sysbus_from_qdev(dev)); |
139 | b12080cd | Peter Maydell | int i;
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140 | b12080cd | Peter Maydell | s->scu_control = 0;
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141 | b12080cd | Peter Maydell | for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) { |
142 | b12080cd | Peter Maydell | s->old_timer_status[i] = 0;
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143 | b12080cd | Peter Maydell | } |
144 | b12080cd | Peter Maydell | } |
145 | b12080cd | Peter Maydell | |
146 | b12080cd | Peter Maydell | static int a9mp_priv_init(SysBusDevice *dev) |
147 | b12080cd | Peter Maydell | { |
148 | b12080cd | Peter Maydell | a9mp_priv_state *s = FROM_SYSBUSGIC(a9mp_priv_state, dev); |
149 | b12080cd | Peter Maydell | SysBusDevice *busdev; |
150 | b12080cd | Peter Maydell | int i;
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151 | b12080cd | Peter Maydell | |
152 | b12080cd | Peter Maydell | if (s->num_cpu > NCPU) {
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153 | b12080cd | Peter Maydell | hw_error("a9mp_priv_init: num-cpu may not be more than %d\n", NCPU);
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154 | b12080cd | Peter Maydell | } |
155 | b12080cd | Peter Maydell | |
156 | a32134aa | Mark Langsdorf | gic_init(&s->gic, s->num_cpu, s->num_irq); |
157 | b12080cd | Peter Maydell | |
158 | b12080cd | Peter Maydell | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
159 | b12080cd | Peter Maydell | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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160 | b12080cd | Peter Maydell | qdev_init_nofail(s->mptimer); |
161 | b12080cd | Peter Maydell | busdev = sysbus_from_qdev(s->mptimer); |
162 | b12080cd | Peter Maydell | |
163 | b12080cd | Peter Maydell | /* Memory map (addresses are offsets from PERIPHBASE):
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164 | b12080cd | Peter Maydell | * 0x0000-0x00ff -- Snoop Control Unit
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165 | b12080cd | Peter Maydell | * 0x0100-0x01ff -- GIC CPU interface
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166 | b12080cd | Peter Maydell | * 0x0200-0x02ff -- Global Timer
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167 | b12080cd | Peter Maydell | * 0x0300-0x05ff -- nothing
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168 | b12080cd | Peter Maydell | * 0x0600-0x06ff -- private timers and watchdogs
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169 | b12080cd | Peter Maydell | * 0x0700-0x0fff -- nothing
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170 | b12080cd | Peter Maydell | * 0x1000-0x1fff -- GIC Distributor
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171 | b12080cd | Peter Maydell | *
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172 | b12080cd | Peter Maydell | * We should implement the global timer but don't currently do so.
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173 | b12080cd | Peter Maydell | */
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174 | b12080cd | Peter Maydell | memory_region_init(&s->container, "a9mp-priv-container", 0x2000); |
175 | b12080cd | Peter Maydell | memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100); |
176 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
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177 | b12080cd | Peter Maydell | /* GIC CPU interface */
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178 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0x100, &s->gic.cpuiomem[0]); |
179 | b12080cd | Peter Maydell | /* Note that the A9 exposes only the "timer/watchdog for this core"
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180 | b12080cd | Peter Maydell | * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
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181 | b12080cd | Peter Maydell | */
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182 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0x600,
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183 | b12080cd | Peter Maydell | sysbus_mmio_get_region(busdev, 0));
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184 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0x620,
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185 | b12080cd | Peter Maydell | sysbus_mmio_get_region(busdev, 1));
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186 | b12080cd | Peter Maydell | memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
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187 | b12080cd | Peter Maydell | |
188 | b12080cd | Peter Maydell | sysbus_init_mmio(dev, &s->container); |
189 | b12080cd | Peter Maydell | |
190 | b12080cd | Peter Maydell | /* Wire up the interrupt from each watchdog and timer. */
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191 | b12080cd | Peter Maydell | s->timer_irq = qemu_allocate_irqs(a9mpcore_timer_irq_handler, |
192 | b12080cd | Peter Maydell | s, (s->num_cpu + 1) * 2); |
193 | b12080cd | Peter Maydell | for (i = 0; i < s->num_cpu * 2; i++) { |
194 | b12080cd | Peter Maydell | sysbus_connect_irq(busdev, i, s->timer_irq[i]); |
195 | b12080cd | Peter Maydell | } |
196 | b12080cd | Peter Maydell | return 0; |
197 | b12080cd | Peter Maydell | } |
198 | b12080cd | Peter Maydell | |
199 | b12080cd | Peter Maydell | static const VMStateDescription vmstate_a9mp_priv = { |
200 | b12080cd | Peter Maydell | .name = "a9mpcore_priv",
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201 | 78aca8a7 | Rob Herring | .version_id = 2,
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202 | b12080cd | Peter Maydell | .minimum_version_id = 1,
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203 | b12080cd | Peter Maydell | .fields = (VMStateField[]) { |
204 | b12080cd | Peter Maydell | VMSTATE_UINT32(scu_control, a9mp_priv_state), |
205 | b12080cd | Peter Maydell | VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
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206 | 78aca8a7 | Rob Herring | VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
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207 | b12080cd | Peter Maydell | VMSTATE_END_OF_LIST() |
208 | b12080cd | Peter Maydell | } |
209 | b12080cd | Peter Maydell | }; |
210 | f7c70325 | Paul Brook | |
211 | 39bffca2 | Anthony Liguori | static Property a9mp_priv_properties[] = {
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212 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1), |
213 | 39bffca2 | Anthony Liguori | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
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214 | 39bffca2 | Anthony Liguori | * IRQ lines (with another 32 internal). We default to 64+32, which
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215 | 39bffca2 | Anthony Liguori | * is the number provided by the Cortex-A9MP test chip in the
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216 | 39bffca2 | Anthony Liguori | * Realview PBX-A9 and Versatile Express A9 development boards.
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217 | 39bffca2 | Anthony Liguori | * Other boards may differ and should set this property appropriately.
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218 | 39bffca2 | Anthony Liguori | */
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219 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96), |
220 | 39bffca2 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
221 | 39bffca2 | Anthony Liguori | }; |
222 | 39bffca2 | Anthony Liguori | |
223 | 999e12bb | Anthony Liguori | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
224 | 999e12bb | Anthony Liguori | { |
225 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
226 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
227 | 999e12bb | Anthony Liguori | |
228 | 999e12bb | Anthony Liguori | k->init = a9mp_priv_init; |
229 | 39bffca2 | Anthony Liguori | dc->props = a9mp_priv_properties; |
230 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_a9mp_priv; |
231 | 39bffca2 | Anthony Liguori | dc->reset = a9mp_priv_reset; |
232 | 999e12bb | Anthony Liguori | } |
233 | 999e12bb | Anthony Liguori | |
234 | 39bffca2 | Anthony Liguori | static TypeInfo a9mp_priv_info = {
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235 | 39bffca2 | Anthony Liguori | .name = "a9mpcore_priv",
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236 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
237 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(a9mp_priv_state),
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238 | 39bffca2 | Anthony Liguori | .class_init = a9mp_priv_class_init, |
239 | f7c70325 | Paul Brook | }; |
240 | f7c70325 | Paul Brook | |
241 | 83f7d43a | Andreas Färber | static void a9mp_register_types(void) |
242 | f7c70325 | Paul Brook | { |
243 | 39bffca2 | Anthony Liguori | type_register_static(&a9mp_priv_info); |
244 | f7c70325 | Paul Brook | } |
245 | f7c70325 | Paul Brook | |
246 | 83f7d43a | Andreas Färber | type_init(a9mp_register_types) |