Revision 255e1fcb target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 41 | 41 |
static TCGv cpu_env, cpu_regwptr; |
| 42 | 42 |
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; |
| 43 | 43 |
static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
| 44 |
static TCGv cpu_y; |
|
| 45 |
#ifndef CONFIG_USER_ONLY |
|
| 46 |
static TCGv cpu_tbr; |
|
| 47 |
#endif |
|
| 44 | 48 |
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; |
| 45 | 49 |
#ifdef TARGET_SPARC64 |
| 46 |
static TCGv cpu_xcc; |
|
| 50 |
static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr; |
|
| 51 |
static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; |
|
| 52 |
static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; |
|
| 53 |
#else |
|
| 54 |
static TCGv cpu_wim; |
|
| 47 | 55 |
#endif |
| 48 | 56 |
/* local register indexes (only used inside old micro ops) */ |
| 49 | 57 |
static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64; |
| ... | ... | |
| 724 | 732 |
T1 = 0; |
| 725 | 733 |
*/ |
| 726 | 734 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 727 |
tcg_gen_ld_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 728 |
tcg_gen_andi_tl(r_temp, r_temp, 0x1); |
|
| 735 |
tcg_gen_andi_tl(r_temp, cpu_y, 0x1); |
|
| 729 | 736 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 730 | 737 |
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); |
| 731 | 738 |
tcg_gen_movi_tl(cpu_cc_src2, 0); |
| ... | ... | |
| 735 | 742 |
// env->y = (b2 << 31) | (env->y >> 1); |
| 736 | 743 |
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); |
| 737 | 744 |
tcg_gen_shli_tl(r_temp, r_temp, 31); |
| 738 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 739 |
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 1); |
|
| 740 |
tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
|
| 741 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 745 |
tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1); |
|
| 746 |
tcg_gen_or_tl(cpu_y, cpu_tmp0, r_temp); |
|
| 742 | 747 |
|
| 743 | 748 |
// b1 = N ^ V; |
| 744 | 749 |
gen_mov_reg_N(cpu_tmp0, cpu_psr); |
| ... | ... | |
| 776 | 781 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 777 | 782 |
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
| 778 | 783 |
tcg_temp_free(r_temp); |
| 779 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); |
|
| 780 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 784 |
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); |
|
| 781 | 785 |
#ifdef TARGET_SPARC64 |
| 782 | 786 |
tcg_gen_mov_i64(dst, r_temp2); |
| 783 | 787 |
#else |
| ... | ... | |
| 800 | 804 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 801 | 805 |
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
| 802 | 806 |
tcg_temp_free(r_temp); |
| 803 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); |
|
| 804 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 807 |
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); |
|
| 805 | 808 |
#ifdef TARGET_SPARC64 |
| 806 | 809 |
tcg_gen_mov_i64(dst, r_temp2); |
| 807 | 810 |
#else |
| ... | ... | |
| 1645 | 1648 |
|
| 1646 | 1649 |
if (IS_IMM) {
|
| 1647 | 1650 |
r_asi = tcg_temp_new(TCG_TYPE_I32); |
| 1648 |
tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
|
|
| 1651 |
tcg_gen_mov_i32(r_asi, cpu_asi);
|
|
| 1649 | 1652 |
} else {
|
| 1650 | 1653 |
asi = GET_FIELD(insn, 19, 26); |
| 1651 | 1654 |
r_asi = tcg_const_i32(asi); |
| ... | ... | |
| 2080 | 2083 |
SPARCv8 manual, rdy on the |
| 2081 | 2084 |
microSPARC II */ |
| 2082 | 2085 |
#endif |
| 2083 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
|
| 2084 |
offsetof(CPUSPARCState, y)); |
|
| 2085 |
gen_movl_TN_reg(rd, cpu_tmp0); |
|
| 2086 |
gen_movl_TN_reg(rd, cpu_y); |
|
| 2086 | 2087 |
break; |
| 2087 | 2088 |
#ifdef TARGET_SPARC64 |
| 2088 | 2089 |
case 0x2: /* V9 rdccr */ |
| ... | ... | |
| 2090 | 2091 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2091 | 2092 |
break; |
| 2092 | 2093 |
case 0x3: /* V9 rdasi */ |
| 2093 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
|
| 2094 |
offsetof(CPUSPARCState, asi)); |
|
| 2095 |
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
|
| 2094 |
tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
|
| 2096 | 2095 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2097 | 2096 |
break; |
| 2098 | 2097 |
case 0x4: /* V9 rdtick */ |
| ... | ... | |
| 2118 | 2117 |
} |
| 2119 | 2118 |
break; |
| 2120 | 2119 |
case 0x6: /* V9 rdfprs */ |
| 2121 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
|
| 2122 |
offsetof(CPUSPARCState, fprs)); |
|
| 2123 |
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
|
| 2120 |
tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
|
| 2124 | 2121 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2125 | 2122 |
break; |
| 2126 | 2123 |
case 0xf: /* V9 membar */ |
| ... | ... | |
| 2128 | 2125 |
case 0x13: /* Graphics Status */ |
| 2129 | 2126 |
if (gen_trap_ifnofpu(dc, cpu_cond)) |
| 2130 | 2127 |
goto jmp_insn; |
| 2131 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
|
| 2132 |
offsetof(CPUSPARCState, gsr)); |
|
| 2133 |
gen_movl_TN_reg(rd, cpu_tmp0); |
|
| 2128 |
gen_movl_TN_reg(rd, cpu_gsr); |
|
| 2134 | 2129 |
break; |
| 2135 | 2130 |
case 0x17: /* Tick compare */ |
| 2136 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
|
| 2137 |
offsetof(CPUSPARCState, tick_cmpr)); |
|
| 2138 |
gen_movl_TN_reg(rd, cpu_tmp0); |
|
| 2131 |
gen_movl_TN_reg(rd, cpu_tick_cmpr); |
|
| 2139 | 2132 |
break; |
| 2140 | 2133 |
case 0x18: /* System tick */ |
| 2141 | 2134 |
{
|
| ... | ... | |
| 2151 | 2144 |
} |
| 2152 | 2145 |
break; |
| 2153 | 2146 |
case 0x19: /* System tick compare */ |
| 2154 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
|
| 2155 |
offsetof(CPUSPARCState, stick_cmpr)); |
|
| 2156 |
gen_movl_TN_reg(rd, cpu_tmp0); |
|
| 2147 |
gen_movl_TN_reg(rd, cpu_stick_cmpr); |
|
| 2157 | 2148 |
break; |
| 2158 | 2149 |
case 0x10: /* Performance Control */ |
| 2159 | 2150 |
case 0x11: /* Performance Instrumentation Counter */ |
| ... | ... | |
| 2184 | 2175 |
// gen_op_rdhtstate(); |
| 2185 | 2176 |
break; |
| 2186 | 2177 |
case 3: // hintp |
| 2187 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
|
| 2188 |
offsetof(CPUSPARCState, hintp)); |
|
| 2189 |
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
|
| 2178 |
tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
|
| 2190 | 2179 |
break; |
| 2191 | 2180 |
case 5: // htba |
| 2192 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
|
| 2193 |
offsetof(CPUSPARCState, htba)); |
|
| 2194 |
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
|
| 2181 |
tcg_gen_mov_tl(cpu_dst, cpu_htba); |
|
| 2195 | 2182 |
break; |
| 2196 | 2183 |
case 6: // hver |
| 2197 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
|
| 2198 |
offsetof(CPUSPARCState, hver)); |
|
| 2199 |
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32); |
|
| 2184 |
tcg_gen_mov_tl(cpu_dst, cpu_hver); |
|
| 2200 | 2185 |
break; |
| 2201 | 2186 |
case 31: // hstick_cmpr |
| 2202 |
tcg_gen_ld_tl(cpu_dst, cpu_env, |
|
| 2203 |
offsetof(CPUSPARCState, hstick_cmpr)); |
|
| 2187 |
tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
|
| 2204 | 2188 |
break; |
| 2205 | 2189 |
default: |
| 2206 | 2190 |
goto illegal_insn; |
| ... | ... | |
| 2276 | 2260 |
} |
| 2277 | 2261 |
break; |
| 2278 | 2262 |
case 5: // tba |
| 2279 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
|
| 2280 |
offsetof(CPUSPARCState, tbr)); |
|
| 2263 |
tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
|
| 2281 | 2264 |
break; |
| 2282 | 2265 |
case 6: // pstate |
| 2283 | 2266 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
| ... | ... | |
| 2332 | 2315 |
CHECK_IU_FEATURE(dc, HYPV); |
| 2333 | 2316 |
if (!hypervisor(dc)) |
| 2334 | 2317 |
goto priv_insn; |
| 2335 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
|
| 2336 |
offsetof(CPUSPARCState, ssr)); |
|
| 2337 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
|
| 2318 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_ssr); |
|
| 2338 | 2319 |
break; |
| 2339 | 2320 |
case 31: // ver |
| 2340 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, |
|
| 2341 |
offsetof(CPUSPARCState, version)); |
|
| 2321 |
tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
|
| 2342 | 2322 |
break; |
| 2343 | 2323 |
case 15: // fq |
| 2344 | 2324 |
default: |
| 2345 | 2325 |
goto illegal_insn; |
| 2346 | 2326 |
} |
| 2347 | 2327 |
#else |
| 2348 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
|
| 2349 |
offsetof(CPUSPARCState, wim)); |
|
| 2350 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
|
| 2328 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
|
| 2351 | 2329 |
#endif |
| 2352 | 2330 |
gen_movl_TN_reg(rd, cpu_tmp0); |
| 2353 | 2331 |
break; |
| ... | ... | |
| 2358 | 2336 |
#else |
| 2359 | 2337 |
if (!supervisor(dc)) |
| 2360 | 2338 |
goto priv_insn; |
| 2361 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr)); |
|
| 2362 |
gen_movl_TN_reg(rd, cpu_tmp0); |
|
| 2339 |
gen_movl_TN_reg(rd, cpu_tbr); |
|
| 2363 | 2340 |
#endif |
| 2364 | 2341 |
break; |
| 2365 | 2342 |
#endif |
| ... | ... | |
| 3152 | 3129 |
{
|
| 3153 | 3130 |
switch(rd) {
|
| 3154 | 3131 |
case 0: /* wry */ |
| 3155 |
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
|
| 3156 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, |
|
| 3157 |
offsetof(CPUSPARCState, y)); |
|
| 3132 |
tcg_gen_xor_tl(cpu_y, cpu_src1, cpu_src2); |
|
| 3158 | 3133 |
break; |
| 3159 | 3134 |
#ifndef TARGET_SPARC64 |
| 3160 | 3135 |
case 0x01 ... 0x0f: /* undefined in the |
| ... | ... | |
| 3173 | 3148 |
break; |
| 3174 | 3149 |
case 0x3: /* V9 wrasi */ |
| 3175 | 3150 |
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
| 3176 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
|
| 3177 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, |
|
| 3178 |
offsetof(CPUSPARCState, asi)); |
|
| 3151 |
tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
|
| 3179 | 3152 |
break; |
| 3180 | 3153 |
case 0x6: /* V9 wrfprs */ |
| 3181 | 3154 |
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
| 3182 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
|
| 3183 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, |
|
| 3184 |
offsetof(CPUSPARCState, fprs)); |
|
| 3155 |
tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
|
| 3185 | 3156 |
save_state(dc, cpu_cond); |
| 3186 | 3157 |
gen_op_next_insn(); |
| 3187 | 3158 |
tcg_gen_exit_tb(0); |
| ... | ... | |
| 3196 | 3167 |
case 0x13: /* Graphics Status */ |
| 3197 | 3168 |
if (gen_trap_ifnofpu(dc, cpu_cond)) |
| 3198 | 3169 |
goto jmp_insn; |
| 3199 |
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
|
| 3200 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, |
|
| 3201 |
offsetof(CPUSPARCState, gsr)); |
|
| 3170 |
tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
|
| 3202 | 3171 |
break; |
| 3203 | 3172 |
case 0x17: /* Tick compare */ |
| 3204 | 3173 |
#if !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 3208 | 3177 |
{
|
| 3209 | 3178 |
TCGv r_tickptr; |
| 3210 | 3179 |
|
| 3211 |
tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
|
|
| 3180 |
tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
|
|
| 3212 | 3181 |
cpu_src2); |
| 3213 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, |
|
| 3214 |
offsetof(CPUSPARCState, |
|
| 3215 |
tick_cmpr)); |
|
| 3216 | 3182 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
| 3217 | 3183 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
| 3218 | 3184 |
offsetof(CPUState, tick)); |
| 3219 | 3185 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
| 3220 |
r_tickptr, cpu_tmp0);
|
|
| 3186 |
r_tickptr, cpu_tick_cmpr);
|
|
| 3221 | 3187 |
tcg_temp_free(r_tickptr); |
| 3222 | 3188 |
} |
| 3223 | 3189 |
break; |
| ... | ... | |
| 3247 | 3213 |
{
|
| 3248 | 3214 |
TCGv r_tickptr; |
| 3249 | 3215 |
|
| 3250 |
tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
|
|
| 3216 |
tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
|
|
| 3251 | 3217 |
cpu_src2); |
| 3252 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, |
|
| 3253 |
offsetof(CPUSPARCState, |
|
| 3254 |
stick_cmpr)); |
|
| 3255 | 3218 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
| 3256 | 3219 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
| 3257 | 3220 |
offsetof(CPUState, stick)); |
| 3258 | 3221 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
| 3259 |
r_tickptr, cpu_tmp0);
|
|
| 3222 |
r_tickptr, cpu_stick_cmpr);
|
|
| 3260 | 3223 |
tcg_temp_free(r_tickptr); |
| 3261 | 3224 |
} |
| 3262 | 3225 |
break; |
| ... | ... | |
| 3374 | 3337 |
} |
| 3375 | 3338 |
break; |
| 3376 | 3339 |
case 5: // tba |
| 3377 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, |
|
| 3378 |
offsetof(CPUSPARCState, tbr)); |
|
| 3340 |
tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
|
| 3379 | 3341 |
break; |
| 3380 | 3342 |
case 6: // pstate |
| 3381 | 3343 |
save_state(dc, cpu_cond); |
| ... | ... | |
| 3438 | 3400 |
CHECK_IU_FEATURE(dc, HYPV); |
| 3439 | 3401 |
if (!hypervisor(dc)) |
| 3440 | 3402 |
goto priv_insn; |
| 3441 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
|
| 3442 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, |
|
| 3443 |
offsetof(CPUSPARCState, ssr)); |
|
| 3403 |
tcg_gen_trunc_tl_i32(cpu_ssr, cpu_tmp0); |
|
| 3444 | 3404 |
break; |
| 3445 | 3405 |
default: |
| 3446 | 3406 |
goto illegal_insn; |
| ... | ... | |
| 3450 | 3410 |
if (dc->def->nwindows != 32) |
| 3451 | 3411 |
tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, |
| 3452 | 3412 |
(1 << dc->def->nwindows) - 1); |
| 3453 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, |
|
| 3454 |
offsetof(CPUSPARCState, wim)); |
|
| 3413 |
tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
|
| 3455 | 3414 |
#endif |
| 3456 | 3415 |
} |
| 3457 | 3416 |
break; |
| ... | ... | |
| 3460 | 3419 |
#ifndef TARGET_SPARC64 |
| 3461 | 3420 |
if (!supervisor(dc)) |
| 3462 | 3421 |
goto priv_insn; |
| 3463 |
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
|
| 3464 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, |
|
| 3465 |
offsetof(CPUSPARCState, tbr)); |
|
| 3422 |
tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
|
| 3466 | 3423 |
#else |
| 3467 | 3424 |
CHECK_IU_FEATURE(dc, HYPV); |
| 3468 | 3425 |
if (!hypervisor(dc)) |
| ... | ... | |
| 3480 | 3437 |
// XXX gen_op_wrhtstate(); |
| 3481 | 3438 |
break; |
| 3482 | 3439 |
case 3: // hintp |
| 3483 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
|
| 3484 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, |
|
| 3485 |
offsetof(CPUSPARCState, hintp)); |
|
| 3440 |
tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
|
| 3486 | 3441 |
break; |
| 3487 | 3442 |
case 5: // htba |
| 3488 |
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
|
| 3489 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, |
|
| 3490 |
offsetof(CPUSPARCState, htba)); |
|
| 3443 |
tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
|
| 3491 | 3444 |
break; |
| 3492 | 3445 |
case 31: // hstick_cmpr |
| 3493 | 3446 |
{
|
| 3494 | 3447 |
TCGv r_tickptr; |
| 3495 | 3448 |
|
| 3496 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, |
|
| 3497 |
offsetof(CPUSPARCState, |
|
| 3498 |
hstick_cmpr)); |
|
| 3449 |
tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
|
| 3499 | 3450 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
| 3500 | 3451 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
| 3501 | 3452 |
offsetof(CPUState, hstick)); |
| 3502 | 3453 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
| 3503 |
r_tickptr, cpu_tmp0);
|
|
| 3454 |
r_tickptr, cpu_hstick_cmpr);
|
|
| 3504 | 3455 |
tcg_temp_free(r_tickptr); |
| 3505 | 3456 |
} |
| 3506 | 3457 |
break; |
| ... | ... | |
| 4905 | 4856 |
cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
| 4906 | 4857 |
TCG_AREG0, offsetof(CPUState, xcc), |
| 4907 | 4858 |
"xcc"); |
| 4859 |
cpu_asi = tcg_global_mem_new(TCG_TYPE_I32, |
|
| 4860 |
TCG_AREG0, offsetof(CPUState, asi), |
|
| 4861 |
"asi"); |
|
| 4862 |
cpu_fprs = tcg_global_mem_new(TCG_TYPE_I32, |
|
| 4863 |
TCG_AREG0, offsetof(CPUState, fprs), |
|
| 4864 |
"fprs"); |
|
| 4865 |
cpu_gsr = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4866 |
TCG_AREG0, offsetof(CPUState, gsr), |
|
| 4867 |
"gsr"); |
|
| 4868 |
cpu_tick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4869 |
TCG_AREG0, |
|
| 4870 |
offsetof(CPUState, tick_cmpr), |
|
| 4871 |
"tick_cmpr"); |
|
| 4872 |
cpu_stick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4873 |
TCG_AREG0, |
|
| 4874 |
offsetof(CPUState, stick_cmpr), |
|
| 4875 |
"stick_cmpr"); |
|
| 4876 |
cpu_hstick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4877 |
TCG_AREG0, |
|
| 4878 |
offsetof(CPUState, hstick_cmpr), |
|
| 4879 |
"hstick_cmpr"); |
|
| 4880 |
cpu_hintp = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
|
| 4881 |
offsetof(CPUState, hintp), |
|
| 4882 |
"hintp"); |
|
| 4883 |
cpu_htba = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
|
| 4884 |
offsetof(CPUState, htba), |
|
| 4885 |
"htba"); |
|
| 4886 |
cpu_hver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
|
| 4887 |
offsetof(CPUState, hver), |
|
| 4888 |
"hver"); |
|
| 4889 |
cpu_ssr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
|
| 4890 |
offsetof(CPUState, ssr), "ssr"); |
|
| 4891 |
cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
|
| 4892 |
offsetof(CPUState, version), "ver"); |
|
| 4893 |
#else |
|
| 4894 |
cpu_wim = tcg_global_mem_new(TCG_TYPE_I32, |
|
| 4895 |
TCG_AREG0, offsetof(CPUState, wim), |
|
| 4896 |
"wim"); |
|
| 4908 | 4897 |
#endif |
| 4909 | 4898 |
cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, |
| 4910 | 4899 |
TCG_AREG0, offsetof(CPUState, cond), |
| ... | ... | |
| 4930 | 4919 |
cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, |
| 4931 | 4920 |
TCG_AREG0, offsetof(CPUState, npc), |
| 4932 | 4921 |
"npc"); |
| 4922 |
cpu_y = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4923 |
TCG_AREG0, offsetof(CPUState, y), "y"); |
|
| 4924 |
#ifndef CONFIG_USER_ONLY |
|
| 4925 |
cpu_tbr = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4926 |
TCG_AREG0, offsetof(CPUState, tbr), |
|
| 4927 |
"tbr"); |
|
| 4928 |
#endif |
|
| 4933 | 4929 |
for (i = 1; i < 8; i++) |
| 4934 | 4930 |
cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
| 4935 | 4931 |
offsetof(CPUState, gregs[i]), |
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