Archipelago » qemu

#define MSR_AP   23 /* Access privilege state on 602                  hflags */

#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */

#define MSR_KEY  19 /* key bit on 603e                                       */

#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */

#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */

#define MSR_ILE  16 /* Interrupt little-endian mode                          */

#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */

#define MSR_FE1  8  /* Floating point exception mode 1                hflags */

#define MSR_AL   7  /* AL bit on POWER                                       */

#define MSR_IR   5  /* Instruction relocate                                  */

#define MSR_DR   4  /* Data relocate                                         */

#define MSR_PX   2  /* Protection exclusive on 403                  x        */

#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */

#define MSR_RI   1  /* Recoverable interrupt                        1        */

#define msr_sa   env->msr[MSR_SA]

#define msr_key  env->msr[MSR_KEY]

#define msr_pow  env->msr[MSR_POW]

#define msr_tgpr env->msr[MSR_TGPR]

#define msr_ce   env->msr[MSR_CE]

#define msr_ile  env->msr[MSR_ILE]

#define msr_de   env->msr[MSR_DE]

#define msr_fe1  env->msr[MSR_FE1]

#define msr_al   env->msr[MSR_AL]

#define msr_ir   env->msr[MSR_IR]

#define msr_dr   env->msr[MSR_DR]

#define msr_pe   env->msr[MSR_PE]

#define msr_le   env->msr[MSR_LE]

enum {

    POWERPC_FLAG_NONE = 0x00000000,

    /* Flag for MSR bit 25 signification (VRE/SPE)                           */

    POWERPC_FLAG_SPE  = 0x00000001,

    POWERPC_FLAG_VRE  = 0x00000002,

    /* Flag for MSR bit 17 signification (TGPR/CE)                           */

    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */

    /* Flag for MSR bit 9 signification (BE/DE)                              */

    /* Flag for MSR but 2 signification (PX/PMM)                             */

};

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