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/*
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* defines common to all virtual CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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#include "qemu-common.h" |
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#include "qemu-tls.h" |
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#include "cpu-common.h" |
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#include "memory_mapping.h" |
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#include "dump.h" |
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/* some important defines:
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*
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* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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* memory accesses.
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*
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* HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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* otherwise little endian.
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*
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* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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*
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* TARGET_WORDS_BIGENDIAN : same for target cpu
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*/
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#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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#define BSWAP_NEEDED
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#endif
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#ifdef BSWAP_NEEDED
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static inline uint16_t tswap16(uint16_t s) |
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{ |
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return bswap16(s);
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} |
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static inline uint32_t tswap32(uint32_t s) |
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{ |
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return bswap32(s);
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} |
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static inline uint64_t tswap64(uint64_t s) |
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{ |
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return bswap64(s);
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} |
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static inline void tswap16s(uint16_t *s) |
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{ |
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*s = bswap16(*s); |
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} |
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static inline void tswap32s(uint32_t *s) |
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{ |
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*s = bswap32(*s); |
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} |
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static inline void tswap64s(uint64_t *s) |
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{ |
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*s = bswap64(*s); |
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} |
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#else
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static inline uint16_t tswap16(uint16_t s) |
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{ |
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return s;
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} |
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static inline uint32_t tswap32(uint32_t s) |
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{ |
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return s;
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} |
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static inline uint64_t tswap64(uint64_t s) |
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{ |
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return s;
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} |
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static inline void tswap16s(uint16_t *s) |
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{ |
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} |
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static inline void tswap32s(uint32_t *s) |
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{ |
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} |
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static inline void tswap64s(uint64_t *s) |
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{ |
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} |
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#endif
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#if TARGET_LONG_SIZE == 4 |
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#define tswapl(s) tswap32(s)
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#define tswapls(s) tswap32s((uint32_t *)(s))
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#define bswaptls(s) bswap32s(s)
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#else
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#define tswapl(s) tswap64(s)
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#define tswapls(s) tswap64s((uint64_t *)(s))
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#define bswaptls(s) bswap64s(s)
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#endif
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/* CPU memory access without any memory or io remapping */
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/*
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* the generic syntax for the memory accesses is:
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*
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* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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*
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* store: st{type}{size}{endian}_{access_type}(ptr, val)
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*
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* type is:
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* (empty): integer access
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* f : float access
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*
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* sign is:
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* (empty): for floats or 32 bit size
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* endian is:
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* (empty): target cpu endianness or 8 bit access
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* r : reversed target cpu endianness (not implemented yet)
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* be : big endian (not implemented yet)
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* le : little endian (not implemented yet)
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*
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* access_type is:
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* raw : host memory access
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* user : user mode access using soft MMU
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* kernel : kernel mode access using soft MMU
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*/
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/* target-endianness CPU memory access functions */
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#if defined(TARGET_WORDS_BIGENDIAN)
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#define lduw_p(p) lduw_be_p(p)
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#define ldsw_p(p) ldsw_be_p(p)
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#define ldl_p(p) ldl_be_p(p)
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#define ldq_p(p) ldq_be_p(p)
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#define ldfl_p(p) ldfl_be_p(p)
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#define ldfq_p(p) ldfq_be_p(p)
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#define stw_p(p, v) stw_be_p(p, v)
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#define stl_p(p, v) stl_be_p(p, v)
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#define stq_p(p, v) stq_be_p(p, v)
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#define stfl_p(p, v) stfl_be_p(p, v)
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#define stfq_p(p, v) stfq_be_p(p, v)
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#else
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#define lduw_p(p) lduw_le_p(p)
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#define ldsw_p(p) ldsw_le_p(p)
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#define ldl_p(p) ldl_le_p(p)
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#define ldq_p(p) ldq_le_p(p)
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#define ldfl_p(p) ldfl_le_p(p)
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#define ldfq_p(p) ldfq_le_p(p)
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#define stw_p(p, v) stw_le_p(p, v)
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#define stl_p(p, v) stl_le_p(p, v)
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#define stq_p(p, v) stq_le_p(p, v)
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#define stfl_p(p, v) stfl_le_p(p, v)
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#define stfq_p(p, v) stfq_le_p(p, v)
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#endif
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/* MMU memory access macros */
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#if defined(CONFIG_USER_ONLY)
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#include <assert.h> |
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#include "qemu-types.h" |
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/* On some host systems the guest address space is reserved on the host.
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* This allows the guest address space to be offset to a convenient location.
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*/
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#if defined(CONFIG_USE_GUEST_BASE)
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extern unsigned long guest_base; |
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extern int have_guest_base; |
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extern unsigned long reserved_va; |
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#define GUEST_BASE guest_base
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#define RESERVED_VA reserved_va
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#else
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#define GUEST_BASE 0ul |
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#define RESERVED_VA 0ul |
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#endif
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/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
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#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE)) |
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#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
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#define h2g_valid(x) 1 |
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#else
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#define h2g_valid(x) ({ \
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unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ |
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(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
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(!RESERVED_VA || (__guest < RESERVED_VA)); \ |
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}) |
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#endif
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#define h2g(x) ({ \
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unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ |
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/* Check if given address fits target address space */ \
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assert(h2g_valid(x)); \ |
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(abi_ulong)__ret; \ |
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}) |
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#define saddr(x) g2h(x)
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#define laddr(x) g2h(x)
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#else /* !CONFIG_USER_ONLY */ |
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/* NOTE: we use double casts if pointers and target_ulong have
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different sizes */
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#define saddr(x) (uint8_t *)(intptr_t)(x)
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#define laddr(x) (uint8_t *)(intptr_t)(x)
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#endif
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#define ldub_raw(p) ldub_p(laddr((p)))
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#define ldsb_raw(p) ldsb_p(laddr((p)))
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#define lduw_raw(p) lduw_p(laddr((p)))
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#define ldsw_raw(p) ldsw_p(laddr((p)))
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#define ldl_raw(p) ldl_p(laddr((p)))
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#define ldq_raw(p) ldq_p(laddr((p)))
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#define ldfl_raw(p) ldfl_p(laddr((p)))
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#define ldfq_raw(p) ldfq_p(laddr((p)))
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#define stb_raw(p, v) stb_p(saddr((p)), v)
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#define stw_raw(p, v) stw_p(saddr((p)), v)
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#define stl_raw(p, v) stl_p(saddr((p)), v)
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#define stq_raw(p, v) stq_p(saddr((p)), v)
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#define stfl_raw(p, v) stfl_p(saddr((p)), v)
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#define stfq_raw(p, v) stfq_p(saddr((p)), v)
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#if defined(CONFIG_USER_ONLY)
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/* if user mode, no other memory access functions */
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#define ldub(p) ldub_raw(p)
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#define ldsb(p) ldsb_raw(p)
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#define lduw(p) lduw_raw(p)
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#define ldsw(p) ldsw_raw(p)
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#define ldl(p) ldl_raw(p)
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#define ldq(p) ldq_raw(p)
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#define ldfl(p) ldfl_raw(p)
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#define ldfq(p) ldfq_raw(p)
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#define stb(p, v) stb_raw(p, v)
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#define stw(p, v) stw_raw(p, v)
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#define stl(p, v) stl_raw(p, v)
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#define stq(p, v) stq_raw(p, v)
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#define stfl(p, v) stfl_raw(p, v)
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#define stfq(p, v) stfq_raw(p, v)
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#ifndef CONFIG_TCG_PASS_AREG0
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#define ldub_code(p) ldub_raw(p)
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#define ldsb_code(p) ldsb_raw(p)
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#define lduw_code(p) lduw_raw(p)
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#define ldsw_code(p) ldsw_raw(p)
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#define ldl_code(p) ldl_raw(p)
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#define ldq_code(p) ldq_raw(p)
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#else
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#define cpu_ldub_code(env1, p) ldub_raw(p)
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#define cpu_ldsb_code(env1, p) ldsb_raw(p)
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#define cpu_lduw_code(env1, p) lduw_raw(p)
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#define cpu_ldsw_code(env1, p) ldsw_raw(p)
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#define cpu_ldl_code(env1, p) ldl_raw(p)
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#define cpu_ldq_code(env1, p) ldq_raw(p)
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#endif
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#define ldub_kernel(p) ldub_raw(p)
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#define ldsb_kernel(p) ldsb_raw(p)
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#define lduw_kernel(p) lduw_raw(p)
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#define ldsw_kernel(p) ldsw_raw(p)
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#define ldl_kernel(p) ldl_raw(p)
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#define ldq_kernel(p) ldq_raw(p)
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#define ldfl_kernel(p) ldfl_raw(p)
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#define ldfq_kernel(p) ldfq_raw(p)
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#define stb_kernel(p, v) stb_raw(p, v)
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#define stw_kernel(p, v) stw_raw(p, v)
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#define stl_kernel(p, v) stl_raw(p, v)
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#define stq_kernel(p, v) stq_raw(p, v)
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#define stfl_kernel(p, v) stfl_raw(p, v)
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#define stfq_kernel(p, vt) stfq_raw(p, v)
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#endif /* defined(CONFIG_USER_ONLY) */ |
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/* page related stuff */
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#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
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#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
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#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
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/* ??? These should be the larger of uintptr_t and target_ulong. */
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extern uintptr_t qemu_real_host_page_size;
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extern uintptr_t qemu_host_page_size;
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extern uintptr_t qemu_host_page_mask;
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#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
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/* same as PROT_xxx */
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#define PAGE_READ 0x0001 |
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#define PAGE_WRITE 0x0002 |
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#define PAGE_EXEC 0x0004 |
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#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
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#define PAGE_VALID 0x0008 |
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/* original state of the write flag (used when tracking self-modifying
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code */
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#define PAGE_WRITE_ORG 0x0010 |
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#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
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/* FIXME: Code that sets/uses this is broken and needs to go away. */
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#define PAGE_RESERVED 0x0020 |
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#endif
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#if defined(CONFIG_USER_ONLY)
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void page_dump(FILE *f);
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typedef int (*walk_memory_regions_fn)(void *, abi_ulong, |
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abi_ulong, unsigned long); |
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int walk_memory_regions(void *, walk_memory_regions_fn); |
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int page_get_flags(target_ulong address);
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void page_set_flags(target_ulong start, target_ulong end, int flags); |
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int page_check_range(target_ulong start, target_ulong len, int flags); |
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#endif
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CPUArchState *cpu_copy(CPUArchState *env); |
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CPUArchState *qemu_get_cpu(int cpu);
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#define CPU_DUMP_CODE 0x00010000 |
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void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) |
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GCC_FMT_ATTR(2, 3); |
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extern CPUArchState *first_cpu;
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DECLARE_TLS(CPUArchState *,cpu_single_env); |
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#define cpu_single_env tls_var(cpu_single_env)
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/* Flags for use in ENV->INTERRUPT_PENDING.
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The numbers assigned here are non-sequential in order to preserve
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binary compatibility with the vmstate dump. Bit 0 (0x0001) was
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previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
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the vmstate dump. */
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/* External hardware interrupt pending. This is typically used for
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interrupts from devices. */
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#define CPU_INTERRUPT_HARD 0x0002 |
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/* Exit the current TB. This is typically used when some system-level device
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makes some change to the memory mapping. E.g. the a20 line change. */
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#define CPU_INTERRUPT_EXITTB 0x0004 |
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/* Halt the CPU. */
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#define CPU_INTERRUPT_HALT 0x0020 |
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/* Debug event pending. */
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#define CPU_INTERRUPT_DEBUG 0x0080 |
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/* Several target-specific external hardware interrupts. Each target/cpu.h
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should define proper names based on these defines. */
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#define CPU_INTERRUPT_TGT_EXT_0 0x0008 |
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#define CPU_INTERRUPT_TGT_EXT_1 0x0010 |
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#define CPU_INTERRUPT_TGT_EXT_2 0x0040 |
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#define CPU_INTERRUPT_TGT_EXT_3 0x0200 |
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#define CPU_INTERRUPT_TGT_EXT_4 0x1000 |
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/* Several target-specific internal interrupts. These differ from the
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preceding target-specific interrupts in that they are intended to
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originate from within the cpu itself, typically in response to some
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instruction being executed. These, therefore, are not masked while
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single-stepping within the debugger. */
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#define CPU_INTERRUPT_TGT_INT_0 0x0100 |
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#define CPU_INTERRUPT_TGT_INT_1 0x0400 |
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#define CPU_INTERRUPT_TGT_INT_2 0x0800 |
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#define CPU_INTERRUPT_TGT_INT_3 0x2000 |
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/* First unused bit: 0x4000. */
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/* The set of all bits that should be masked when single-stepping. */
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#define CPU_INTERRUPT_SSTEP_MASK \
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(CPU_INTERRUPT_HARD \ |
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| CPU_INTERRUPT_TGT_EXT_0 \ |
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| CPU_INTERRUPT_TGT_EXT_1 \ |
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| CPU_INTERRUPT_TGT_EXT_2 \ |
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| CPU_INTERRUPT_TGT_EXT_3 \ |
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| CPU_INTERRUPT_TGT_EXT_4) |
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#ifndef CONFIG_USER_ONLY
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typedef void (*CPUInterruptHandler)(CPUArchState *, int); |
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extern CPUInterruptHandler cpu_interrupt_handler;
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static inline void cpu_interrupt(CPUArchState *s, int mask) |
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{ |
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cpu_interrupt_handler(s, mask); |
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} |
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#else /* USER_ONLY */ |
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void cpu_interrupt(CPUArchState *env, int mask); |
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#endif /* USER_ONLY */ |
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void cpu_reset_interrupt(CPUArchState *env, int mask); |
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void cpu_exit(CPUArchState *s);
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bool qemu_cpu_has_work(CPUArchState *env);
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/* Breakpoint/watchpoint flags */
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#define BP_MEM_READ 0x01 |
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#define BP_MEM_WRITE 0x02 |
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#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
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#define BP_STOP_BEFORE_ACCESS 0x04 |
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#define BP_WATCHPOINT_HIT 0x08 |
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#define BP_GDB 0x10 |
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#define BP_CPU 0x20 |
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int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, |
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CPUBreakpoint **breakpoint); |
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int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); |
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void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
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void cpu_breakpoint_remove_all(CPUArchState *env, int mask); |
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int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
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int flags, CPUWatchpoint **watchpoint);
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int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
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target_ulong len, int flags);
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void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
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void cpu_watchpoint_remove_all(CPUArchState *env, int mask); |
442 |
|
443 |
#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
444 |
#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ |
445 |
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ |
446 |
|
447 |
void cpu_single_step(CPUArchState *env, int enabled); |
448 |
int cpu_is_stopped(CPUArchState *env);
|
449 |
void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data); |
450 |
|
451 |
#define CPU_LOG_TB_OUT_ASM (1 << 0) |
452 |
#define CPU_LOG_TB_IN_ASM (1 << 1) |
453 |
#define CPU_LOG_TB_OP (1 << 2) |
454 |
#define CPU_LOG_TB_OP_OPT (1 << 3) |
455 |
#define CPU_LOG_INT (1 << 4) |
456 |
#define CPU_LOG_EXEC (1 << 5) |
457 |
#define CPU_LOG_PCALL (1 << 6) |
458 |
#define CPU_LOG_IOPORT (1 << 7) |
459 |
#define CPU_LOG_TB_CPU (1 << 8) |
460 |
#define CPU_LOG_RESET (1 << 9) |
461 |
|
462 |
/* define log items */
|
463 |
typedef struct CPULogItem { |
464 |
int mask;
|
465 |
const char *name; |
466 |
const char *help; |
467 |
} CPULogItem; |
468 |
|
469 |
extern const CPULogItem cpu_log_items[]; |
470 |
|
471 |
void cpu_set_log(int log_flags); |
472 |
void cpu_set_log_filename(const char *filename); |
473 |
int cpu_str_to_log_mask(const char *str); |
474 |
|
475 |
#if !defined(CONFIG_USER_ONLY)
|
476 |
|
477 |
/* Return the physical page corresponding to a virtual one. Use it
|
478 |
only for debugging because no protection checks are done. Return -1
|
479 |
if no page found. */
|
480 |
target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr); |
481 |
|
482 |
/* memory API */
|
483 |
|
484 |
extern int phys_ram_fd; |
485 |
extern ram_addr_t ram_size;
|
486 |
|
487 |
/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
|
488 |
#define RAM_PREALLOC_MASK (1 << 0) |
489 |
|
490 |
typedef struct RAMBlock { |
491 |
struct MemoryRegion *mr;
|
492 |
uint8_t *host; |
493 |
ram_addr_t offset; |
494 |
ram_addr_t length; |
495 |
uint32_t flags; |
496 |
char idstr[256]; |
497 |
QLIST_ENTRY(RAMBlock) next; |
498 |
#if defined(__linux__) && !defined(TARGET_S390X)
|
499 |
int fd;
|
500 |
#endif
|
501 |
} RAMBlock; |
502 |
|
503 |
typedef struct RAMList { |
504 |
uint8_t *phys_dirty; |
505 |
QLIST_HEAD(, RAMBlock) blocks; |
506 |
} RAMList; |
507 |
extern RAMList ram_list;
|
508 |
|
509 |
extern const char *mem_path; |
510 |
extern int mem_prealloc; |
511 |
|
512 |
/* Flags stored in the low bits of the TLB virtual address. These are
|
513 |
defined so that fast path ram access is all zeros. */
|
514 |
/* Zero if TLB entry is valid. */
|
515 |
#define TLB_INVALID_MASK (1 << 3) |
516 |
/* Set if TLB entry references a clean RAM page. The iotlb entry will
|
517 |
contain the page physical address. */
|
518 |
#define TLB_NOTDIRTY (1 << 4) |
519 |
/* Set if TLB entry is an IO callback. */
|
520 |
#define TLB_MMIO (1 << 5) |
521 |
|
522 |
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
|
523 |
#endif /* !CONFIG_USER_ONLY */ |
524 |
|
525 |
int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
|
526 |
uint8_t *buf, int len, int is_write); |
527 |
|
528 |
#if defined(CONFIG_HAVE_GET_MEMORY_MAPPING)
|
529 |
int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env);
|
530 |
bool cpu_paging_enabled(CPUArchState *env);
|
531 |
#else
|
532 |
static inline int cpu_get_memory_mapping(MemoryMappingList *list, |
533 |
CPUArchState *env) |
534 |
{ |
535 |
return -1; |
536 |
} |
537 |
|
538 |
static inline bool cpu_paging_enabled(CPUArchState *env) |
539 |
{ |
540 |
return true; |
541 |
} |
542 |
#endif
|
543 |
|
544 |
typedef int (*write_core_dump_function)(void *buf, size_t size, void *opaque); |
545 |
#if defined(CONFIG_HAVE_CORE_DUMP)
|
546 |
int cpu_write_elf64_note(write_core_dump_function f, CPUArchState *env,
|
547 |
int cpuid, void *opaque); |
548 |
int cpu_write_elf32_note(write_core_dump_function f, CPUArchState *env,
|
549 |
int cpuid, void *opaque); |
550 |
int cpu_write_elf64_qemunote(write_core_dump_function f, CPUArchState *env,
|
551 |
void *opaque);
|
552 |
int cpu_write_elf32_qemunote(write_core_dump_function f, CPUArchState *env,
|
553 |
void *opaque);
|
554 |
int cpu_get_dump_info(ArchDumpInfo *info);
|
555 |
size_t cpu_get_note_size(int class, int machine, int nr_cpus); |
556 |
#else
|
557 |
static inline int cpu_write_elf64_note(write_core_dump_function f, |
558 |
CPUArchState *env, int cpuid,
|
559 |
void *opaque)
|
560 |
{ |
561 |
return -1; |
562 |
} |
563 |
|
564 |
static inline int cpu_write_elf32_note(write_core_dump_function f, |
565 |
CPUArchState *env, int cpuid,
|
566 |
void *opaque)
|
567 |
{ |
568 |
return -1; |
569 |
} |
570 |
|
571 |
static inline int cpu_write_elf64_qemunote(write_core_dump_function f, |
572 |
CPUArchState *env, |
573 |
void *opaque)
|
574 |
{ |
575 |
return -1; |
576 |
} |
577 |
|
578 |
static inline int cpu_write_elf32_qemunote(write_core_dump_function f, |
579 |
CPUArchState *env, |
580 |
void *opaque)
|
581 |
{ |
582 |
return -1; |
583 |
} |
584 |
|
585 |
static inline int cpu_get_dump_info(ArchDumpInfo *info) |
586 |
{ |
587 |
return -1; |
588 |
} |
589 |
|
590 |
static inline int cpu_get_note_size(int class, int machine, int nr_cpus) |
591 |
{ |
592 |
return -1; |
593 |
} |
594 |
#endif
|
595 |
|
596 |
#endif /* CPU_ALL_H */ |