Revision 25eb4484
| b/exec-i386.c | ||
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/* thread support */ |
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#ifdef __powerpc__ |
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static inline int testandset (int *p) |
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{
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int ret; |
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__asm__ __volatile__ ( |
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"0: lwarx %0,0,%1 ;" |
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" xor. %0,%3,%0;" |
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" bne 1f;" |
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" stwcx. %2,0,%1;" |
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" bne- 0b;" |
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"1: " |
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: "=&r" (ret) |
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: "r" (p), "r" (1), "r" (0) |
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: "cr0", "memory"); |
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return ret; |
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} |
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#endif |
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#ifdef __i386__ |
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static inline int testandset (int *p) |
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{
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char ret; |
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long int readval; |
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__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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: "=q" (ret), "=m" (*p), "=a" (readval) |
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: "r" (1), "m" (*p), "a" (0) |
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: "memory"); |
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return ret; |
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} |
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#endif |
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#ifdef __s390__ |
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static inline int testandset (int *p) |
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{
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int ret; |
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__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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" jl 0b" |
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: "=&d" (ret) |
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: "r" (1), "a" (p), "0" (*p) |
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: "cc", "memory" ); |
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return ret; |
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} |
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#endif |
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#ifdef __alpha__ |
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int testandset (int *p) |
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{
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int ret; |
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unsigned long one; |
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__asm__ __volatile__ ("0: mov 1,%2\n"
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" ldl_l %0,%1\n" |
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" stl_c %2,%1\n" |
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" beq %2,1f\n" |
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".subsection 2\n" |
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"1: br 0b\n" |
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".previous" |
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: "=r" (ret), "=m" (*p), "=r" (one) |
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: "m" (*p)); |
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return ret; |
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} |
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#endif |
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#ifdef __sparc__ |
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static inline int testandset (int *p) |
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{
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int ret; |
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (ret) |
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: "r" (p) |
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: "memory"); |
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return (ret ? 1 : 0); |
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} |
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#endif |
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int global_cpu_lock = 0; |
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
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void cpu_lock(void) |
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{
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while (testandset(&global_cpu_lock));
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spin_lock(&global_cpu_lock);
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} |
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void cpu_unlock(void) |
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{
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global_cpu_lock = 0;
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spin_unlock(&global_cpu_lock);
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} |
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/* exception support */ |
| ... | ... | |
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flags); |
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if (!tb) {
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/* if no translated code available, then translate it now */ |
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/* XXX: very inefficient: we lock all the cpus when
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generating code */ |
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cpu_lock();
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/* very inefficient but safe: we lock all the cpus
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when generating code */
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spin_lock(&tb_lock);
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tc_ptr = code_gen_ptr; |
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ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE, |
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&code_gen_size, pc, cs_base, flags, |
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&code_size); |
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/* if invalid instruction, signal it */ |
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if (ret != 0) {
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cpu_unlock();
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spin_unlock(&tb_lock);
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raise_exception(EXCP06_ILLOP); |
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} |
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tb = tb_alloc((unsigned long)pc, code_size); |
| ... | ... | |
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tb->tc_ptr = tc_ptr; |
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tb->hash_next = NULL; |
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
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cpu_unlock();
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spin_unlock(&tb_lock);
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} |
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#ifdef DEBUG_EXEC |
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if (loglevel) {
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| ... | ... | |
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set); |
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#endif |
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/* XXX: locking issue */ |
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if (is_write && page_unprotect(address)) {
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sigprocmask(SIG_SETMASK, old_set, NULL); |
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return 1; |
| ... | ... | |
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uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? |
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(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
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pold_set); |
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#elif defined(__powerpc) |
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struct ucontext *uc = puc; |
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struct pt_regs *regs = uc->uc_mcontext.regs; |
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unsigned long pc; |
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sigset_t *pold_set; |
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int is_write; |
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pc = regs->nip; |
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pold_set = &uc->uc_sigmask; |
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is_write = 0; |
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#if 0 |
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/* ppc 4xx case */ |
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if (regs->dsisr & 0x00800000) |
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is_write = 1; |
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#else |
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if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) |
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is_write = 1; |
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#endif |
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return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
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is_write, pold_set); |
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#else |
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#warning No CPU specific signal handler: cannot handle target SIGSEGV events
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#error CPU specific signal handler needed
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return 0; |
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#endif |
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} |
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