Revision 2623c1ec target-mips/cpu.h
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int error_code; |
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uint32_t hflags; /* CPU State */ |
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/* TMASK defines different execution modes */ |
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#define MIPS_HFLAG_TMASK 0x01FF
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#define MIPS_HFLAG_TMASK 0x03FF
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#define MIPS_HFLAG_MODE 0x0007 /* execution modes */ |
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/* The KSU flags must be the lowest bits in hflags. The flag order |
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must be the same as defined for CP0 Status. This allows to use |
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and RSQRT.D. */ |
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#define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ |
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#define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ |
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#define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ |
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/* If translation is interrupted between the branch instruction and |
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* the delay slot, record what type of branch it is so that we can |
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* resume translation properly. It might be possible to reduce |
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* this from three bits to two. */ |
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#define MIPS_HFLAG_BMASK 0x0e00
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#define MIPS_HFLAG_B 0x0200 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x0400 /* Conditional branch */
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#define MIPS_HFLAG_BL 0x0600 /* Likely branch */
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#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
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#define MIPS_HFLAG_BMASK 0x1C00
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#define MIPS_HFLAG_B 0x0400 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x0800 /* Conditional branch */
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#define MIPS_HFLAG_BL 0x0C00 /* Likely branch */
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#define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */
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target_ulong btarget; /* Jump / branch target */ |
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int bcond; /* Branch condition (if needed) */ |
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