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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 micro operations
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | f68dd770 | bellard | |
21 | f68dd770 | bellard | #define ASM_SOFTMMU
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22 | 2c0262af | bellard | #include "exec.h" |
23 | 2c0262af | bellard | |
24 | 2c0262af | bellard | /* n must be a constant to be efficient */
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25 | 14ce26e7 | bellard | static inline target_long lshift(target_long x, int n) |
26 | 2c0262af | bellard | { |
27 | 2c0262af | bellard | if (n >= 0) |
28 | 2c0262af | bellard | return x << n;
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29 | 2c0262af | bellard | else
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30 | 2c0262af | bellard | return x >> (-n);
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31 | 2c0262af | bellard | } |
32 | 2c0262af | bellard | |
33 | 2c0262af | bellard | /* we define the various pieces of code used by the JIT */
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34 | 2c0262af | bellard | |
35 | 2c0262af | bellard | #define REG EAX
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36 | 2c0262af | bellard | #define REGNAME _EAX
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37 | 2c0262af | bellard | #include "opreg_template.h" |
38 | 2c0262af | bellard | #undef REG
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39 | 2c0262af | bellard | #undef REGNAME
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40 | 2c0262af | bellard | |
41 | 2c0262af | bellard | #define REG ECX
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42 | 2c0262af | bellard | #define REGNAME _ECX
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43 | 2c0262af | bellard | #include "opreg_template.h" |
44 | 2c0262af | bellard | #undef REG
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45 | 2c0262af | bellard | #undef REGNAME
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46 | 2c0262af | bellard | |
47 | 2c0262af | bellard | #define REG EDX
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48 | 2c0262af | bellard | #define REGNAME _EDX
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49 | 2c0262af | bellard | #include "opreg_template.h" |
50 | 2c0262af | bellard | #undef REG
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51 | 2c0262af | bellard | #undef REGNAME
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52 | 2c0262af | bellard | |
53 | 2c0262af | bellard | #define REG EBX
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54 | 2c0262af | bellard | #define REGNAME _EBX
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55 | 2c0262af | bellard | #include "opreg_template.h" |
56 | 2c0262af | bellard | #undef REG
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57 | 2c0262af | bellard | #undef REGNAME
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58 | 2c0262af | bellard | |
59 | 2c0262af | bellard | #define REG ESP
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60 | 2c0262af | bellard | #define REGNAME _ESP
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61 | 2c0262af | bellard | #include "opreg_template.h" |
62 | 2c0262af | bellard | #undef REG
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63 | 2c0262af | bellard | #undef REGNAME
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64 | 2c0262af | bellard | |
65 | 2c0262af | bellard | #define REG EBP
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66 | 2c0262af | bellard | #define REGNAME _EBP
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67 | 2c0262af | bellard | #include "opreg_template.h" |
68 | 2c0262af | bellard | #undef REG
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69 | 2c0262af | bellard | #undef REGNAME
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70 | 2c0262af | bellard | |
71 | 2c0262af | bellard | #define REG ESI
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72 | 2c0262af | bellard | #define REGNAME _ESI
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73 | 2c0262af | bellard | #include "opreg_template.h" |
74 | 2c0262af | bellard | #undef REG
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75 | 2c0262af | bellard | #undef REGNAME
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76 | 2c0262af | bellard | |
77 | 2c0262af | bellard | #define REG EDI
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78 | 2c0262af | bellard | #define REGNAME _EDI
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79 | 2c0262af | bellard | #include "opreg_template.h" |
80 | 2c0262af | bellard | #undef REG
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81 | 2c0262af | bellard | #undef REGNAME
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82 | 2c0262af | bellard | |
83 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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84 | 14ce26e7 | bellard | |
85 | 14ce26e7 | bellard | #define REG (env->regs[8]) |
86 | 14ce26e7 | bellard | #define REGNAME _R8
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87 | 14ce26e7 | bellard | #include "opreg_template.h" |
88 | 14ce26e7 | bellard | #undef REG
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89 | 14ce26e7 | bellard | #undef REGNAME
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90 | 14ce26e7 | bellard | |
91 | 14ce26e7 | bellard | #define REG (env->regs[9]) |
92 | 14ce26e7 | bellard | #define REGNAME _R9
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93 | 14ce26e7 | bellard | #include "opreg_template.h" |
94 | 14ce26e7 | bellard | #undef REG
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95 | 14ce26e7 | bellard | #undef REGNAME
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96 | 14ce26e7 | bellard | |
97 | 14ce26e7 | bellard | #define REG (env->regs[10]) |
98 | 14ce26e7 | bellard | #define REGNAME _R10
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99 | 14ce26e7 | bellard | #include "opreg_template.h" |
100 | 14ce26e7 | bellard | #undef REG
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101 | 14ce26e7 | bellard | #undef REGNAME
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102 | 14ce26e7 | bellard | |
103 | 14ce26e7 | bellard | #define REG (env->regs[11]) |
104 | 14ce26e7 | bellard | #define REGNAME _R11
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105 | 14ce26e7 | bellard | #include "opreg_template.h" |
106 | 14ce26e7 | bellard | #undef REG
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107 | 14ce26e7 | bellard | #undef REGNAME
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108 | 14ce26e7 | bellard | |
109 | 14ce26e7 | bellard | #define REG (env->regs[12]) |
110 | 14ce26e7 | bellard | #define REGNAME _R12
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111 | 14ce26e7 | bellard | #include "opreg_template.h" |
112 | 14ce26e7 | bellard | #undef REG
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113 | 14ce26e7 | bellard | #undef REGNAME
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114 | 14ce26e7 | bellard | |
115 | 14ce26e7 | bellard | #define REG (env->regs[13]) |
116 | 14ce26e7 | bellard | #define REGNAME _R13
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117 | 14ce26e7 | bellard | #include "opreg_template.h" |
118 | 14ce26e7 | bellard | #undef REG
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119 | 14ce26e7 | bellard | #undef REGNAME
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120 | 14ce26e7 | bellard | |
121 | 14ce26e7 | bellard | #define REG (env->regs[14]) |
122 | 14ce26e7 | bellard | #define REGNAME _R14
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123 | 14ce26e7 | bellard | #include "opreg_template.h" |
124 | 14ce26e7 | bellard | #undef REG
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125 | 14ce26e7 | bellard | #undef REGNAME
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126 | 14ce26e7 | bellard | |
127 | 14ce26e7 | bellard | #define REG (env->regs[15]) |
128 | 14ce26e7 | bellard | #define REGNAME _R15
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129 | 14ce26e7 | bellard | #include "opreg_template.h" |
130 | 14ce26e7 | bellard | #undef REG
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131 | 14ce26e7 | bellard | #undef REGNAME
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132 | 14ce26e7 | bellard | |
133 | 14ce26e7 | bellard | #endif
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134 | 14ce26e7 | bellard | |
135 | 2c0262af | bellard | /* operations with flags */
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136 | 2c0262af | bellard | |
137 | 2c0262af | bellard | /* update flags with T0 and T1 (add/sub case) */
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138 | 2c0262af | bellard | void OPPROTO op_update2_cc(void) |
139 | 2c0262af | bellard | { |
140 | 2c0262af | bellard | CC_SRC = T1; |
141 | 2c0262af | bellard | CC_DST = T0; |
142 | 2c0262af | bellard | } |
143 | 2c0262af | bellard | |
144 | 2c0262af | bellard | /* update flags with T0 (logic operation case) */
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145 | 2c0262af | bellard | void OPPROTO op_update1_cc(void) |
146 | 2c0262af | bellard | { |
147 | 2c0262af | bellard | CC_DST = T0; |
148 | 2c0262af | bellard | } |
149 | 2c0262af | bellard | |
150 | 2c0262af | bellard | void OPPROTO op_update_neg_cc(void) |
151 | 2c0262af | bellard | { |
152 | 2c0262af | bellard | CC_SRC = -T0; |
153 | 2c0262af | bellard | CC_DST = T0; |
154 | 2c0262af | bellard | } |
155 | 2c0262af | bellard | |
156 | 2c0262af | bellard | void OPPROTO op_cmpl_T0_T1_cc(void) |
157 | 2c0262af | bellard | { |
158 | 2c0262af | bellard | CC_SRC = T1; |
159 | 2c0262af | bellard | CC_DST = T0 - T1; |
160 | 2c0262af | bellard | } |
161 | 2c0262af | bellard | |
162 | 2c0262af | bellard | void OPPROTO op_update_inc_cc(void) |
163 | 2c0262af | bellard | { |
164 | 2c0262af | bellard | CC_SRC = cc_table[CC_OP].compute_c(); |
165 | 2c0262af | bellard | CC_DST = T0; |
166 | 2c0262af | bellard | } |
167 | 2c0262af | bellard | |
168 | 2c0262af | bellard | void OPPROTO op_testl_T0_T1_cc(void) |
169 | 2c0262af | bellard | { |
170 | 2c0262af | bellard | CC_DST = T0 & T1; |
171 | 2c0262af | bellard | } |
172 | 2c0262af | bellard | |
173 | 2c0262af | bellard | /* operations without flags */
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174 | 2c0262af | bellard | |
175 | 2c0262af | bellard | void OPPROTO op_addl_T0_T1(void) |
176 | 2c0262af | bellard | { |
177 | 2c0262af | bellard | T0 += T1; |
178 | 2c0262af | bellard | } |
179 | 2c0262af | bellard | |
180 | 2c0262af | bellard | void OPPROTO op_orl_T0_T1(void) |
181 | 2c0262af | bellard | { |
182 | 2c0262af | bellard | T0 |= T1; |
183 | 2c0262af | bellard | } |
184 | 2c0262af | bellard | |
185 | 2c0262af | bellard | void OPPROTO op_andl_T0_T1(void) |
186 | 2c0262af | bellard | { |
187 | 2c0262af | bellard | T0 &= T1; |
188 | 2c0262af | bellard | } |
189 | 2c0262af | bellard | |
190 | 2c0262af | bellard | void OPPROTO op_subl_T0_T1(void) |
191 | 2c0262af | bellard | { |
192 | 2c0262af | bellard | T0 -= T1; |
193 | 2c0262af | bellard | } |
194 | 2c0262af | bellard | |
195 | 2c0262af | bellard | void OPPROTO op_xorl_T0_T1(void) |
196 | 2c0262af | bellard | { |
197 | 2c0262af | bellard | T0 ^= T1; |
198 | 2c0262af | bellard | } |
199 | 2c0262af | bellard | |
200 | 2c0262af | bellard | void OPPROTO op_negl_T0(void) |
201 | 2c0262af | bellard | { |
202 | 2c0262af | bellard | T0 = -T0; |
203 | 2c0262af | bellard | } |
204 | 2c0262af | bellard | |
205 | 2c0262af | bellard | void OPPROTO op_incl_T0(void) |
206 | 2c0262af | bellard | { |
207 | 2c0262af | bellard | T0++; |
208 | 2c0262af | bellard | } |
209 | 2c0262af | bellard | |
210 | 2c0262af | bellard | void OPPROTO op_decl_T0(void) |
211 | 2c0262af | bellard | { |
212 | 2c0262af | bellard | T0--; |
213 | 2c0262af | bellard | } |
214 | 2c0262af | bellard | |
215 | 2c0262af | bellard | void OPPROTO op_notl_T0(void) |
216 | 2c0262af | bellard | { |
217 | 2c0262af | bellard | T0 = ~T0; |
218 | 2c0262af | bellard | } |
219 | 2c0262af | bellard | |
220 | 2c0262af | bellard | void OPPROTO op_bswapl_T0(void) |
221 | 2c0262af | bellard | { |
222 | 2c0262af | bellard | T0 = bswap32(T0); |
223 | 2c0262af | bellard | } |
224 | 2c0262af | bellard | |
225 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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226 | 14ce26e7 | bellard | void OPPROTO op_bswapq_T0(void) |
227 | 14ce26e7 | bellard | { |
228 | 68cae3d8 | bellard | helper_bswapq_T0(); |
229 | 14ce26e7 | bellard | } |
230 | 14ce26e7 | bellard | #endif
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231 | 14ce26e7 | bellard | |
232 | 2c0262af | bellard | /* multiply/divide */
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233 | d36cd60e | bellard | |
234 | d36cd60e | bellard | /* XXX: add eflags optimizations */
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235 | d36cd60e | bellard | /* XXX: add non P4 style flags */
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236 | d36cd60e | bellard | |
237 | 2c0262af | bellard | void OPPROTO op_mulb_AL_T0(void) |
238 | 2c0262af | bellard | { |
239 | 2c0262af | bellard | unsigned int res; |
240 | 2c0262af | bellard | res = (uint8_t)EAX * (uint8_t)T0; |
241 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | res;
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242 | d36cd60e | bellard | CC_DST = res; |
243 | 2c0262af | bellard | CC_SRC = (res & 0xff00);
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244 | 2c0262af | bellard | } |
245 | 2c0262af | bellard | |
246 | 2c0262af | bellard | void OPPROTO op_imulb_AL_T0(void) |
247 | 2c0262af | bellard | { |
248 | 2c0262af | bellard | int res;
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249 | 2c0262af | bellard | res = (int8_t)EAX * (int8_t)T0; |
250 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
251 | d36cd60e | bellard | CC_DST = res; |
252 | 2c0262af | bellard | CC_SRC = (res != (int8_t)res); |
253 | 2c0262af | bellard | } |
254 | 2c0262af | bellard | |
255 | 2c0262af | bellard | void OPPROTO op_mulw_AX_T0(void) |
256 | 2c0262af | bellard | { |
257 | 2c0262af | bellard | unsigned int res; |
258 | 2c0262af | bellard | res = (uint16_t)EAX * (uint16_t)T0; |
259 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
260 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff); |
261 | d36cd60e | bellard | CC_DST = res; |
262 | 2c0262af | bellard | CC_SRC = res >> 16;
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263 | 2c0262af | bellard | } |
264 | 2c0262af | bellard | |
265 | 2c0262af | bellard | void OPPROTO op_imulw_AX_T0(void) |
266 | 2c0262af | bellard | { |
267 | 2c0262af | bellard | int res;
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268 | 2c0262af | bellard | res = (int16_t)EAX * (int16_t)T0; |
269 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
270 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff); |
271 | d36cd60e | bellard | CC_DST = res; |
272 | 2c0262af | bellard | CC_SRC = (res != (int16_t)res); |
273 | 2c0262af | bellard | } |
274 | 2c0262af | bellard | |
275 | 2c0262af | bellard | void OPPROTO op_mull_EAX_T0(void) |
276 | 2c0262af | bellard | { |
277 | 2c0262af | bellard | uint64_t res; |
278 | 2c0262af | bellard | res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0); |
279 | 14ce26e7 | bellard | EAX = (uint32_t)res; |
280 | 14ce26e7 | bellard | EDX = (uint32_t)(res >> 32);
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281 | 14ce26e7 | bellard | CC_DST = (uint32_t)res; |
282 | 14ce26e7 | bellard | CC_SRC = (uint32_t)(res >> 32);
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283 | 2c0262af | bellard | } |
284 | 2c0262af | bellard | |
285 | 2c0262af | bellard | void OPPROTO op_imull_EAX_T0(void) |
286 | 2c0262af | bellard | { |
287 | 2c0262af | bellard | int64_t res; |
288 | 2c0262af | bellard | res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0); |
289 | 31313213 | bellard | EAX = (uint32_t)(res); |
290 | 31313213 | bellard | EDX = (uint32_t)(res >> 32);
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291 | d36cd60e | bellard | CC_DST = res; |
292 | 2c0262af | bellard | CC_SRC = (res != (int32_t)res); |
293 | 2c0262af | bellard | } |
294 | 2c0262af | bellard | |
295 | 2c0262af | bellard | void OPPROTO op_imulw_T0_T1(void) |
296 | 2c0262af | bellard | { |
297 | 2c0262af | bellard | int res;
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298 | 2c0262af | bellard | res = (int16_t)T0 * (int16_t)T1; |
299 | 2c0262af | bellard | T0 = res; |
300 | d36cd60e | bellard | CC_DST = res; |
301 | 2c0262af | bellard | CC_SRC = (res != (int16_t)res); |
302 | 2c0262af | bellard | } |
303 | 2c0262af | bellard | |
304 | 2c0262af | bellard | void OPPROTO op_imull_T0_T1(void) |
305 | 2c0262af | bellard | { |
306 | 2c0262af | bellard | int64_t res; |
307 | 2c0262af | bellard | res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
308 | 2c0262af | bellard | T0 = res; |
309 | d36cd60e | bellard | CC_DST = res; |
310 | 2c0262af | bellard | CC_SRC = (res != (int32_t)res); |
311 | 2c0262af | bellard | } |
312 | 2c0262af | bellard | |
313 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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314 | 14ce26e7 | bellard | void OPPROTO op_mulq_EAX_T0(void) |
315 | 14ce26e7 | bellard | { |
316 | 14ce26e7 | bellard | helper_mulq_EAX_T0(); |
317 | 14ce26e7 | bellard | } |
318 | 14ce26e7 | bellard | |
319 | 14ce26e7 | bellard | void OPPROTO op_imulq_EAX_T0(void) |
320 | 14ce26e7 | bellard | { |
321 | 14ce26e7 | bellard | helper_imulq_EAX_T0(); |
322 | 14ce26e7 | bellard | } |
323 | 14ce26e7 | bellard | |
324 | 14ce26e7 | bellard | void OPPROTO op_imulq_T0_T1(void) |
325 | 14ce26e7 | bellard | { |
326 | 14ce26e7 | bellard | helper_imulq_T0_T1(); |
327 | 14ce26e7 | bellard | } |
328 | 14ce26e7 | bellard | #endif
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329 | 14ce26e7 | bellard | |
330 | 2c0262af | bellard | /* division, flags are undefined */
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331 | 2c0262af | bellard | |
332 | 2c0262af | bellard | void OPPROTO op_divb_AL_T0(void) |
333 | 2c0262af | bellard | { |
334 | 2c0262af | bellard | unsigned int num, den, q, r; |
335 | 2c0262af | bellard | |
336 | 2c0262af | bellard | num = (EAX & 0xffff);
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337 | 2c0262af | bellard | den = (T0 & 0xff);
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338 | 2c0262af | bellard | if (den == 0) { |
339 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
340 | 2c0262af | bellard | } |
341 | 45bbbb46 | bellard | q = (num / den); |
342 | 45bbbb46 | bellard | if (q > 0xff) |
343 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
344 | 45bbbb46 | bellard | q &= 0xff;
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345 | 2c0262af | bellard | r = (num % den) & 0xff;
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346 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (r << 8) | q; |
347 | 2c0262af | bellard | } |
348 | 2c0262af | bellard | |
349 | 2c0262af | bellard | void OPPROTO op_idivb_AL_T0(void) |
350 | 2c0262af | bellard | { |
351 | 2c0262af | bellard | int num, den, q, r;
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352 | 2c0262af | bellard | |
353 | 2c0262af | bellard | num = (int16_t)EAX; |
354 | 2c0262af | bellard | den = (int8_t)T0; |
355 | 2c0262af | bellard | if (den == 0) { |
356 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
357 | 2c0262af | bellard | } |
358 | 45bbbb46 | bellard | q = (num / den); |
359 | 45bbbb46 | bellard | if (q != (int8_t)q)
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360 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
361 | 45bbbb46 | bellard | q &= 0xff;
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362 | 2c0262af | bellard | r = (num % den) & 0xff;
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363 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (r << 8) | q; |
364 | 2c0262af | bellard | } |
365 | 2c0262af | bellard | |
366 | 2c0262af | bellard | void OPPROTO op_divw_AX_T0(void) |
367 | 2c0262af | bellard | { |
368 | 2c0262af | bellard | unsigned int num, den, q, r; |
369 | 2c0262af | bellard | |
370 | 2c0262af | bellard | num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); |
371 | 2c0262af | bellard | den = (T0 & 0xffff);
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372 | 2c0262af | bellard | if (den == 0) { |
373 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
374 | 2c0262af | bellard | } |
375 | 45bbbb46 | bellard | q = (num / den); |
376 | 45bbbb46 | bellard | if (q > 0xffff) |
377 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
378 | 45bbbb46 | bellard | q &= 0xffff;
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379 | 2c0262af | bellard | r = (num % den) & 0xffff;
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380 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | q;
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381 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | r;
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382 | 2c0262af | bellard | } |
383 | 2c0262af | bellard | |
384 | 2c0262af | bellard | void OPPROTO op_idivw_AX_T0(void) |
385 | 2c0262af | bellard | { |
386 | 2c0262af | bellard | int num, den, q, r;
|
387 | 2c0262af | bellard | |
388 | 2c0262af | bellard | num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); |
389 | 2c0262af | bellard | den = (int16_t)T0; |
390 | 2c0262af | bellard | if (den == 0) { |
391 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
392 | 2c0262af | bellard | } |
393 | 45bbbb46 | bellard | q = (num / den); |
394 | 45bbbb46 | bellard | if (q != (int16_t)q)
|
395 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
396 | 45bbbb46 | bellard | q &= 0xffff;
|
397 | 2c0262af | bellard | r = (num % den) & 0xffff;
|
398 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | q;
|
399 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | r;
|
400 | 2c0262af | bellard | } |
401 | 2c0262af | bellard | |
402 | 2c0262af | bellard | void OPPROTO op_divl_EAX_T0(void) |
403 | 2c0262af | bellard | { |
404 | 14ce26e7 | bellard | helper_divl_EAX_T0(); |
405 | 2c0262af | bellard | } |
406 | 2c0262af | bellard | |
407 | 2c0262af | bellard | void OPPROTO op_idivl_EAX_T0(void) |
408 | 2c0262af | bellard | { |
409 | 14ce26e7 | bellard | helper_idivl_EAX_T0(); |
410 | 2c0262af | bellard | } |
411 | 2c0262af | bellard | |
412 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
413 | 14ce26e7 | bellard | void OPPROTO op_divq_EAX_T0(void) |
414 | 14ce26e7 | bellard | { |
415 | 14ce26e7 | bellard | helper_divq_EAX_T0(); |
416 | 14ce26e7 | bellard | } |
417 | 14ce26e7 | bellard | |
418 | 14ce26e7 | bellard | void OPPROTO op_idivq_EAX_T0(void) |
419 | 14ce26e7 | bellard | { |
420 | 14ce26e7 | bellard | helper_idivq_EAX_T0(); |
421 | 14ce26e7 | bellard | } |
422 | 14ce26e7 | bellard | #endif
|
423 | 14ce26e7 | bellard | |
424 | 2c0262af | bellard | /* constant load & misc op */
|
425 | 2c0262af | bellard | |
426 | 14ce26e7 | bellard | /* XXX: consistent names */
|
427 | 14ce26e7 | bellard | void OPPROTO op_movl_T0_imu(void) |
428 | 14ce26e7 | bellard | { |
429 | 14ce26e7 | bellard | T0 = (uint32_t)PARAM1; |
430 | 14ce26e7 | bellard | } |
431 | 14ce26e7 | bellard | |
432 | 2c0262af | bellard | void OPPROTO op_movl_T0_im(void) |
433 | 2c0262af | bellard | { |
434 | 14ce26e7 | bellard | T0 = (int32_t)PARAM1; |
435 | 2c0262af | bellard | } |
436 | 2c0262af | bellard | |
437 | 2c0262af | bellard | void OPPROTO op_addl_T0_im(void) |
438 | 2c0262af | bellard | { |
439 | 2c0262af | bellard | T0 += PARAM1; |
440 | 2c0262af | bellard | } |
441 | 2c0262af | bellard | |
442 | 2c0262af | bellard | void OPPROTO op_andl_T0_ffff(void) |
443 | 2c0262af | bellard | { |
444 | 2c0262af | bellard | T0 = T0 & 0xffff;
|
445 | 2c0262af | bellard | } |
446 | 2c0262af | bellard | |
447 | 2c0262af | bellard | void OPPROTO op_andl_T0_im(void) |
448 | 2c0262af | bellard | { |
449 | 2c0262af | bellard | T0 = T0 & PARAM1; |
450 | 2c0262af | bellard | } |
451 | 2c0262af | bellard | |
452 | 2c0262af | bellard | void OPPROTO op_movl_T0_T1(void) |
453 | 2c0262af | bellard | { |
454 | 2c0262af | bellard | T0 = T1; |
455 | 2c0262af | bellard | } |
456 | 2c0262af | bellard | |
457 | 14ce26e7 | bellard | void OPPROTO op_movl_T1_imu(void) |
458 | 14ce26e7 | bellard | { |
459 | 14ce26e7 | bellard | T1 = (uint32_t)PARAM1; |
460 | 14ce26e7 | bellard | } |
461 | 14ce26e7 | bellard | |
462 | 2c0262af | bellard | void OPPROTO op_movl_T1_im(void) |
463 | 2c0262af | bellard | { |
464 | 14ce26e7 | bellard | T1 = (int32_t)PARAM1; |
465 | 2c0262af | bellard | } |
466 | 2c0262af | bellard | |
467 | 2c0262af | bellard | void OPPROTO op_addl_T1_im(void) |
468 | 2c0262af | bellard | { |
469 | 2c0262af | bellard | T1 += PARAM1; |
470 | 2c0262af | bellard | } |
471 | 2c0262af | bellard | |
472 | 2c0262af | bellard | void OPPROTO op_movl_T1_A0(void) |
473 | 2c0262af | bellard | { |
474 | 2c0262af | bellard | T1 = A0; |
475 | 2c0262af | bellard | } |
476 | 2c0262af | bellard | |
477 | 2c0262af | bellard | void OPPROTO op_movl_A0_im(void) |
478 | 2c0262af | bellard | { |
479 | 14ce26e7 | bellard | A0 = (uint32_t)PARAM1; |
480 | 2c0262af | bellard | } |
481 | 2c0262af | bellard | |
482 | 2c0262af | bellard | void OPPROTO op_addl_A0_im(void) |
483 | 2c0262af | bellard | { |
484 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + PARAM1); |
485 | 14ce26e7 | bellard | } |
486 | 14ce26e7 | bellard | |
487 | 14ce26e7 | bellard | void OPPROTO op_movl_A0_seg(void) |
488 | 14ce26e7 | bellard | { |
489 | 14ce26e7 | bellard | A0 = (uint32_t)*(target_ulong *)((char *)env + PARAM1);
|
490 | 14ce26e7 | bellard | } |
491 | 14ce26e7 | bellard | |
492 | 14ce26e7 | bellard | void OPPROTO op_addl_A0_seg(void) |
493 | 14ce26e7 | bellard | { |
494 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + *(target_ulong *)((char *)env + PARAM1));
|
495 | 2c0262af | bellard | } |
496 | 2c0262af | bellard | |
497 | 2c0262af | bellard | void OPPROTO op_addl_A0_AL(void) |
498 | 2c0262af | bellard | { |
499 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + (EAX & 0xff));
|
500 | 14ce26e7 | bellard | } |
501 | 14ce26e7 | bellard | |
502 | 14ce26e7 | bellard | #ifdef WORDS_BIGENDIAN
|
503 | 14ce26e7 | bellard | typedef union UREG64 { |
504 | 14ce26e7 | bellard | struct { uint16_t v3, v2, v1, v0; } w;
|
505 | 14ce26e7 | bellard | struct { uint32_t v1, v0; } l;
|
506 | 14ce26e7 | bellard | uint64_t q; |
507 | 14ce26e7 | bellard | } UREG64; |
508 | 14ce26e7 | bellard | #else
|
509 | 14ce26e7 | bellard | typedef union UREG64 { |
510 | 14ce26e7 | bellard | struct { uint16_t v0, v1, v2, v3; } w;
|
511 | 14ce26e7 | bellard | struct { uint32_t v0, v1; } l;
|
512 | 14ce26e7 | bellard | uint64_t q; |
513 | 14ce26e7 | bellard | } UREG64; |
514 | 14ce26e7 | bellard | #endif
|
515 | 14ce26e7 | bellard | |
516 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
517 | 14ce26e7 | bellard | |
518 | 14ce26e7 | bellard | #define PARAMQ1 \
|
519 | 14ce26e7 | bellard | ({\ |
520 | 14ce26e7 | bellard | UREG64 __p;\ |
521 | 14ce26e7 | bellard | __p.l.v1 = PARAM1;\ |
522 | 14ce26e7 | bellard | __p.l.v0 = PARAM2;\ |
523 | 14ce26e7 | bellard | __p.q;\ |
524 | 14ce26e7 | bellard | }) |
525 | 14ce26e7 | bellard | |
526 | 14ce26e7 | bellard | void OPPROTO op_movq_T0_im64(void) |
527 | 14ce26e7 | bellard | { |
528 | 14ce26e7 | bellard | T0 = PARAMQ1; |
529 | 2c0262af | bellard | } |
530 | 2c0262af | bellard | |
531 | 1ef38687 | bellard | void OPPROTO op_movq_T1_im64(void) |
532 | 1ef38687 | bellard | { |
533 | 1ef38687 | bellard | T1 = PARAMQ1; |
534 | 1ef38687 | bellard | } |
535 | 1ef38687 | bellard | |
536 | 14ce26e7 | bellard | void OPPROTO op_movq_A0_im(void) |
537 | 14ce26e7 | bellard | { |
538 | 14ce26e7 | bellard | A0 = (int32_t)PARAM1; |
539 | 14ce26e7 | bellard | } |
540 | 14ce26e7 | bellard | |
541 | 14ce26e7 | bellard | void OPPROTO op_movq_A0_im64(void) |
542 | 14ce26e7 | bellard | { |
543 | 14ce26e7 | bellard | A0 = PARAMQ1; |
544 | 14ce26e7 | bellard | } |
545 | 14ce26e7 | bellard | |
546 | 14ce26e7 | bellard | void OPPROTO op_addq_A0_im(void) |
547 | 14ce26e7 | bellard | { |
548 | 14ce26e7 | bellard | A0 = (A0 + (int32_t)PARAM1); |
549 | 14ce26e7 | bellard | } |
550 | 14ce26e7 | bellard | |
551 | 14ce26e7 | bellard | void OPPROTO op_addq_A0_im64(void) |
552 | 14ce26e7 | bellard | { |
553 | 14ce26e7 | bellard | A0 = (A0 + PARAMQ1); |
554 | 14ce26e7 | bellard | } |
555 | 14ce26e7 | bellard | |
556 | 14ce26e7 | bellard | void OPPROTO op_movq_A0_seg(void) |
557 | 14ce26e7 | bellard | { |
558 | 14ce26e7 | bellard | A0 = *(target_ulong *)((char *)env + PARAM1);
|
559 | 14ce26e7 | bellard | } |
560 | 14ce26e7 | bellard | |
561 | 14ce26e7 | bellard | void OPPROTO op_addq_A0_seg(void) |
562 | 14ce26e7 | bellard | { |
563 | 14ce26e7 | bellard | A0 += *(target_ulong *)((char *)env + PARAM1);
|
564 | 14ce26e7 | bellard | } |
565 | 14ce26e7 | bellard | |
566 | 14ce26e7 | bellard | void OPPROTO op_addq_A0_AL(void) |
567 | 14ce26e7 | bellard | { |
568 | 14ce26e7 | bellard | A0 = (A0 + (EAX & 0xff));
|
569 | 14ce26e7 | bellard | } |
570 | 14ce26e7 | bellard | |
571 | 14ce26e7 | bellard | #endif
|
572 | 14ce26e7 | bellard | |
573 | 2c0262af | bellard | void OPPROTO op_andl_A0_ffff(void) |
574 | 2c0262af | bellard | { |
575 | 2c0262af | bellard | A0 = A0 & 0xffff;
|
576 | 2c0262af | bellard | } |
577 | 2c0262af | bellard | |
578 | 2c0262af | bellard | /* memory access */
|
579 | 2c0262af | bellard | |
580 | 61382a50 | bellard | #define MEMSUFFIX _raw
|
581 | 2c0262af | bellard | #include "ops_mem.h" |
582 | 2c0262af | bellard | |
583 | 61382a50 | bellard | #if !defined(CONFIG_USER_ONLY)
|
584 | f68dd770 | bellard | #define MEMSUFFIX _kernel
|
585 | 2c0262af | bellard | #include "ops_mem.h" |
586 | 2c0262af | bellard | |
587 | f68dd770 | bellard | #define MEMSUFFIX _user
|
588 | 2c0262af | bellard | #include "ops_mem.h" |
589 | 61382a50 | bellard | #endif
|
590 | 2c0262af | bellard | |
591 | 14ce26e7 | bellard | /* indirect jump */
|
592 | 2c0262af | bellard | |
593 | 14ce26e7 | bellard | void OPPROTO op_jmp_T0(void) |
594 | 2c0262af | bellard | { |
595 | 14ce26e7 | bellard | EIP = T0; |
596 | 2c0262af | bellard | } |
597 | 2c0262af | bellard | |
598 | 14ce26e7 | bellard | void OPPROTO op_movl_eip_im(void) |
599 | 2c0262af | bellard | { |
600 | 14ce26e7 | bellard | EIP = (uint32_t)PARAM1; |
601 | 2c0262af | bellard | } |
602 | 2c0262af | bellard | |
603 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
604 | 14ce26e7 | bellard | void OPPROTO op_movq_eip_im(void) |
605 | 2c0262af | bellard | { |
606 | 14ce26e7 | bellard | EIP = (int32_t)PARAM1; |
607 | 2c0262af | bellard | } |
608 | 2c0262af | bellard | |
609 | 14ce26e7 | bellard | void OPPROTO op_movq_eip_im64(void) |
610 | 2c0262af | bellard | { |
611 | 14ce26e7 | bellard | EIP = PARAMQ1; |
612 | 2c0262af | bellard | } |
613 | 14ce26e7 | bellard | #endif
|
614 | 2c0262af | bellard | |
615 | 2c0262af | bellard | void OPPROTO op_hlt(void) |
616 | 2c0262af | bellard | { |
617 | 3d7374c5 | bellard | helper_hlt(); |
618 | 3d7374c5 | bellard | } |
619 | 3d7374c5 | bellard | |
620 | 3d7374c5 | bellard | void OPPROTO op_monitor(void) |
621 | 3d7374c5 | bellard | { |
622 | 3d7374c5 | bellard | helper_monitor(); |
623 | 3d7374c5 | bellard | } |
624 | 3d7374c5 | bellard | |
625 | 3d7374c5 | bellard | void OPPROTO op_mwait(void) |
626 | 3d7374c5 | bellard | { |
627 | 3d7374c5 | bellard | helper_mwait(); |
628 | 2c0262af | bellard | } |
629 | 2c0262af | bellard | |
630 | 2c0262af | bellard | void OPPROTO op_debug(void) |
631 | 2c0262af | bellard | { |
632 | 2c0262af | bellard | env->exception_index = EXCP_DEBUG; |
633 | 2c0262af | bellard | cpu_loop_exit(); |
634 | 2c0262af | bellard | } |
635 | 2c0262af | bellard | |
636 | 2c0262af | bellard | void OPPROTO op_raise_interrupt(void) |
637 | 2c0262af | bellard | { |
638 | a8ede8ba | bellard | int intno, next_eip_addend;
|
639 | 2c0262af | bellard | intno = PARAM1; |
640 | a8ede8ba | bellard | next_eip_addend = PARAM2; |
641 | a8ede8ba | bellard | raise_interrupt(intno, 1, 0, next_eip_addend); |
642 | 2c0262af | bellard | } |
643 | 2c0262af | bellard | |
644 | 2c0262af | bellard | void OPPROTO op_raise_exception(void) |
645 | 2c0262af | bellard | { |
646 | 2c0262af | bellard | int exception_index;
|
647 | 2c0262af | bellard | exception_index = PARAM1; |
648 | 2c0262af | bellard | raise_exception(exception_index); |
649 | 2c0262af | bellard | } |
650 | 2c0262af | bellard | |
651 | 2c0262af | bellard | void OPPROTO op_into(void) |
652 | 2c0262af | bellard | { |
653 | 2c0262af | bellard | int eflags;
|
654 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
655 | 2c0262af | bellard | if (eflags & CC_O) {
|
656 | 2c0262af | bellard | raise_interrupt(EXCP04_INTO, 1, 0, PARAM1); |
657 | 2c0262af | bellard | } |
658 | 2c0262af | bellard | FORCE_RET(); |
659 | 2c0262af | bellard | } |
660 | 2c0262af | bellard | |
661 | 2c0262af | bellard | void OPPROTO op_cli(void) |
662 | 2c0262af | bellard | { |
663 | 2c0262af | bellard | env->eflags &= ~IF_MASK; |
664 | 2c0262af | bellard | } |
665 | 2c0262af | bellard | |
666 | 2c0262af | bellard | void OPPROTO op_sti(void) |
667 | 2c0262af | bellard | { |
668 | 2c0262af | bellard | env->eflags |= IF_MASK; |
669 | 2c0262af | bellard | } |
670 | 2c0262af | bellard | |
671 | 2c0262af | bellard | void OPPROTO op_set_inhibit_irq(void) |
672 | 2c0262af | bellard | { |
673 | 2c0262af | bellard | env->hflags |= HF_INHIBIT_IRQ_MASK; |
674 | 2c0262af | bellard | } |
675 | 2c0262af | bellard | |
676 | 2c0262af | bellard | void OPPROTO op_reset_inhibit_irq(void) |
677 | 2c0262af | bellard | { |
678 | 2c0262af | bellard | env->hflags &= ~HF_INHIBIT_IRQ_MASK; |
679 | 2c0262af | bellard | } |
680 | 2c0262af | bellard | |
681 | 3b21e03e | bellard | void OPPROTO op_rsm(void) |
682 | 3b21e03e | bellard | { |
683 | 3b21e03e | bellard | helper_rsm(); |
684 | 3b21e03e | bellard | } |
685 | 3b21e03e | bellard | |
686 | 2c0262af | bellard | #if 0
|
687 | 2c0262af | bellard | /* vm86plus instructions */
|
688 | 2c0262af | bellard | void OPPROTO op_cli_vm(void)
|
689 | 2c0262af | bellard | {
|
690 | 2c0262af | bellard | env->eflags &= ~VIF_MASK;
|
691 | 2c0262af | bellard | }
|
692 | 2c0262af | bellard | |
693 | 2c0262af | bellard | void OPPROTO op_sti_vm(void)
|
694 | 2c0262af | bellard | {
|
695 | 2c0262af | bellard | env->eflags |= VIF_MASK;
|
696 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
|
697 | 2c0262af | bellard | EIP = PARAM1;
|
698 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
|
699 | 2c0262af | bellard | }
|
700 | 2c0262af | bellard | FORCE_RET();
|
701 | 2c0262af | bellard | }
|
702 | 2c0262af | bellard | #endif
|
703 | 2c0262af | bellard | |
704 | 2c0262af | bellard | void OPPROTO op_boundw(void) |
705 | 2c0262af | bellard | { |
706 | 2c0262af | bellard | int low, high, v;
|
707 | 14ce26e7 | bellard | low = ldsw(A0); |
708 | 14ce26e7 | bellard | high = ldsw(A0 + 2);
|
709 | 2c0262af | bellard | v = (int16_t)T0; |
710 | 2c0262af | bellard | if (v < low || v > high) {
|
711 | 2c0262af | bellard | raise_exception(EXCP05_BOUND); |
712 | 2c0262af | bellard | } |
713 | 2c0262af | bellard | FORCE_RET(); |
714 | 2c0262af | bellard | } |
715 | 2c0262af | bellard | |
716 | 2c0262af | bellard | void OPPROTO op_boundl(void) |
717 | 2c0262af | bellard | { |
718 | 2c0262af | bellard | int low, high, v;
|
719 | 14ce26e7 | bellard | low = ldl(A0); |
720 | 14ce26e7 | bellard | high = ldl(A0 + 4);
|
721 | 2c0262af | bellard | v = T0; |
722 | 2c0262af | bellard | if (v < low || v > high) {
|
723 | 2c0262af | bellard | raise_exception(EXCP05_BOUND); |
724 | 2c0262af | bellard | } |
725 | 2c0262af | bellard | FORCE_RET(); |
726 | 2c0262af | bellard | } |
727 | 2c0262af | bellard | |
728 | 2c0262af | bellard | void OPPROTO op_cmpxchg8b(void) |
729 | 2c0262af | bellard | { |
730 | 2c0262af | bellard | helper_cmpxchg8b(); |
731 | 2c0262af | bellard | } |
732 | 2c0262af | bellard | |
733 | 2c0262af | bellard | void OPPROTO op_movl_T0_0(void) |
734 | 2c0262af | bellard | { |
735 | 2c0262af | bellard | T0 = 0;
|
736 | 2c0262af | bellard | } |
737 | 2c0262af | bellard | |
738 | 2c0262af | bellard | void OPPROTO op_exit_tb(void) |
739 | 2c0262af | bellard | { |
740 | 2c0262af | bellard | EXIT_TB(); |
741 | 2c0262af | bellard | } |
742 | 2c0262af | bellard | |
743 | 2c0262af | bellard | /* multiple size ops */
|
744 | 2c0262af | bellard | |
745 | 2c0262af | bellard | #define ldul ldl
|
746 | 2c0262af | bellard | |
747 | 2c0262af | bellard | #define SHIFT 0 |
748 | 2c0262af | bellard | #include "ops_template.h" |
749 | 2c0262af | bellard | #undef SHIFT
|
750 | 2c0262af | bellard | |
751 | 2c0262af | bellard | #define SHIFT 1 |
752 | 2c0262af | bellard | #include "ops_template.h" |
753 | 2c0262af | bellard | #undef SHIFT
|
754 | 2c0262af | bellard | |
755 | 2c0262af | bellard | #define SHIFT 2 |
756 | 2c0262af | bellard | #include "ops_template.h" |
757 | 2c0262af | bellard | #undef SHIFT
|
758 | 2c0262af | bellard | |
759 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
760 | 14ce26e7 | bellard | |
761 | 14ce26e7 | bellard | #define SHIFT 3 |
762 | 14ce26e7 | bellard | #include "ops_template.h" |
763 | 14ce26e7 | bellard | #undef SHIFT
|
764 | 14ce26e7 | bellard | |
765 | 14ce26e7 | bellard | #endif
|
766 | 14ce26e7 | bellard | |
767 | 2c0262af | bellard | /* sign extend */
|
768 | 2c0262af | bellard | |
769 | 2c0262af | bellard | void OPPROTO op_movsbl_T0_T0(void) |
770 | 2c0262af | bellard | { |
771 | 2c0262af | bellard | T0 = (int8_t)T0; |
772 | 2c0262af | bellard | } |
773 | 2c0262af | bellard | |
774 | 2c0262af | bellard | void OPPROTO op_movzbl_T0_T0(void) |
775 | 2c0262af | bellard | { |
776 | 2c0262af | bellard | T0 = (uint8_t)T0; |
777 | 2c0262af | bellard | } |
778 | 2c0262af | bellard | |
779 | 2c0262af | bellard | void OPPROTO op_movswl_T0_T0(void) |
780 | 2c0262af | bellard | { |
781 | 2c0262af | bellard | T0 = (int16_t)T0; |
782 | 2c0262af | bellard | } |
783 | 2c0262af | bellard | |
784 | 2c0262af | bellard | void OPPROTO op_movzwl_T0_T0(void) |
785 | 2c0262af | bellard | { |
786 | 2c0262af | bellard | T0 = (uint16_t)T0; |
787 | 2c0262af | bellard | } |
788 | 2c0262af | bellard | |
789 | 2c0262af | bellard | void OPPROTO op_movswl_EAX_AX(void) |
790 | 2c0262af | bellard | { |
791 | 0499e4a0 | bellard | EAX = (uint32_t)((int16_t)EAX); |
792 | 2c0262af | bellard | } |
793 | 2c0262af | bellard | |
794 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
795 | 664e0f19 | bellard | void OPPROTO op_movslq_T0_T0(void) |
796 | 664e0f19 | bellard | { |
797 | 664e0f19 | bellard | T0 = (int32_t)T0; |
798 | 664e0f19 | bellard | } |
799 | 664e0f19 | bellard | |
800 | 14ce26e7 | bellard | void OPPROTO op_movslq_RAX_EAX(void) |
801 | 14ce26e7 | bellard | { |
802 | 14ce26e7 | bellard | EAX = (int32_t)EAX; |
803 | 14ce26e7 | bellard | } |
804 | 14ce26e7 | bellard | #endif
|
805 | 14ce26e7 | bellard | |
806 | 2c0262af | bellard | void OPPROTO op_movsbw_AX_AL(void) |
807 | 2c0262af | bellard | { |
808 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | ((int8_t)EAX & 0xffff); |
809 | 2c0262af | bellard | } |
810 | 2c0262af | bellard | |
811 | 2c0262af | bellard | void OPPROTO op_movslq_EDX_EAX(void) |
812 | 2c0262af | bellard | { |
813 | 0499e4a0 | bellard | EDX = (uint32_t)((int32_t)EAX >> 31);
|
814 | 2c0262af | bellard | } |
815 | 2c0262af | bellard | |
816 | 2c0262af | bellard | void OPPROTO op_movswl_DX_AX(void) |
817 | 2c0262af | bellard | { |
818 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | (((int16_t)EAX >> 15) & 0xffff); |
819 | 14ce26e7 | bellard | } |
820 | 14ce26e7 | bellard | |
821 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
822 | 14ce26e7 | bellard | void OPPROTO op_movsqo_RDX_RAX(void) |
823 | 14ce26e7 | bellard | { |
824 | 14ce26e7 | bellard | EDX = (int64_t)EAX >> 63;
|
825 | 2c0262af | bellard | } |
826 | 14ce26e7 | bellard | #endif
|
827 | 2c0262af | bellard | |
828 | 2c0262af | bellard | /* string ops helpers */
|
829 | 2c0262af | bellard | |
830 | 2c0262af | bellard | void OPPROTO op_addl_ESI_T0(void) |
831 | 2c0262af | bellard | { |
832 | 14ce26e7 | bellard | ESI = (uint32_t)(ESI + T0); |
833 | 2c0262af | bellard | } |
834 | 2c0262af | bellard | |
835 | 2c0262af | bellard | void OPPROTO op_addw_ESI_T0(void) |
836 | 2c0262af | bellard | { |
837 | 2c0262af | bellard | ESI = (ESI & ~0xffff) | ((ESI + T0) & 0xffff); |
838 | 2c0262af | bellard | } |
839 | 2c0262af | bellard | |
840 | 2c0262af | bellard | void OPPROTO op_addl_EDI_T0(void) |
841 | 2c0262af | bellard | { |
842 | 14ce26e7 | bellard | EDI = (uint32_t)(EDI + T0); |
843 | 2c0262af | bellard | } |
844 | 2c0262af | bellard | |
845 | 2c0262af | bellard | void OPPROTO op_addw_EDI_T0(void) |
846 | 2c0262af | bellard | { |
847 | 2c0262af | bellard | EDI = (EDI & ~0xffff) | ((EDI + T0) & 0xffff); |
848 | 2c0262af | bellard | } |
849 | 2c0262af | bellard | |
850 | 2c0262af | bellard | void OPPROTO op_decl_ECX(void) |
851 | 2c0262af | bellard | { |
852 | 14ce26e7 | bellard | ECX = (uint32_t)(ECX - 1);
|
853 | 2c0262af | bellard | } |
854 | 2c0262af | bellard | |
855 | 2c0262af | bellard | void OPPROTO op_decw_ECX(void) |
856 | 2c0262af | bellard | { |
857 | 2c0262af | bellard | ECX = (ECX & ~0xffff) | ((ECX - 1) & 0xffff); |
858 | 2c0262af | bellard | } |
859 | 2c0262af | bellard | |
860 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
861 | 14ce26e7 | bellard | void OPPROTO op_addq_ESI_T0(void) |
862 | 14ce26e7 | bellard | { |
863 | 14ce26e7 | bellard | ESI = (ESI + T0); |
864 | 14ce26e7 | bellard | } |
865 | 14ce26e7 | bellard | |
866 | 14ce26e7 | bellard | void OPPROTO op_addq_EDI_T0(void) |
867 | 14ce26e7 | bellard | { |
868 | 14ce26e7 | bellard | EDI = (EDI + T0); |
869 | 14ce26e7 | bellard | } |
870 | 14ce26e7 | bellard | |
871 | 14ce26e7 | bellard | void OPPROTO op_decq_ECX(void) |
872 | 14ce26e7 | bellard | { |
873 | 14ce26e7 | bellard | ECX--; |
874 | 14ce26e7 | bellard | } |
875 | 14ce26e7 | bellard | #endif
|
876 | 14ce26e7 | bellard | |
877 | f68dd770 | bellard | /* push/pop utils */
|
878 | 2c0262af | bellard | |
879 | f68dd770 | bellard | void op_addl_A0_SS(void) |
880 | 2c0262af | bellard | { |
881 | bc3fc8da | bellard | A0 = (uint32_t)(A0 + env->segs[R_SS].base); |
882 | 2c0262af | bellard | } |
883 | 2c0262af | bellard | |
884 | f68dd770 | bellard | void op_subl_A0_2(void) |
885 | 2c0262af | bellard | { |
886 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 - 2);
|
887 | 2c0262af | bellard | } |
888 | 2c0262af | bellard | |
889 | f68dd770 | bellard | void op_subl_A0_4(void) |
890 | 2c0262af | bellard | { |
891 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 - 4);
|
892 | 2c0262af | bellard | } |
893 | 2c0262af | bellard | |
894 | 2c0262af | bellard | void op_addl_ESP_4(void) |
895 | 2c0262af | bellard | { |
896 | 14ce26e7 | bellard | ESP = (uint32_t)(ESP + 4);
|
897 | 2c0262af | bellard | } |
898 | 2c0262af | bellard | |
899 | 2c0262af | bellard | void op_addl_ESP_2(void) |
900 | 2c0262af | bellard | { |
901 | 14ce26e7 | bellard | ESP = (uint32_t)(ESP + 2);
|
902 | 2c0262af | bellard | } |
903 | 2c0262af | bellard | |
904 | 2c0262af | bellard | void op_addw_ESP_4(void) |
905 | 2c0262af | bellard | { |
906 | 2c0262af | bellard | ESP = (ESP & ~0xffff) | ((ESP + 4) & 0xffff); |
907 | 2c0262af | bellard | } |
908 | 2c0262af | bellard | |
909 | 2c0262af | bellard | void op_addw_ESP_2(void) |
910 | 2c0262af | bellard | { |
911 | 2c0262af | bellard | ESP = (ESP & ~0xffff) | ((ESP + 2) & 0xffff); |
912 | 2c0262af | bellard | } |
913 | 2c0262af | bellard | |
914 | 2c0262af | bellard | void op_addl_ESP_im(void) |
915 | 2c0262af | bellard | { |
916 | 14ce26e7 | bellard | ESP = (uint32_t)(ESP + PARAM1); |
917 | 2c0262af | bellard | } |
918 | 2c0262af | bellard | |
919 | 2c0262af | bellard | void op_addw_ESP_im(void) |
920 | 2c0262af | bellard | { |
921 | 2c0262af | bellard | ESP = (ESP & ~0xffff) | ((ESP + PARAM1) & 0xffff); |
922 | 2c0262af | bellard | } |
923 | 2c0262af | bellard | |
924 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
925 | 8f091a59 | bellard | void op_subq_A0_2(void) |
926 | 8f091a59 | bellard | { |
927 | 8f091a59 | bellard | A0 -= 2;
|
928 | 8f091a59 | bellard | } |
929 | 8f091a59 | bellard | |
930 | 14ce26e7 | bellard | void op_subq_A0_8(void) |
931 | 14ce26e7 | bellard | { |
932 | 14ce26e7 | bellard | A0 -= 8;
|
933 | 14ce26e7 | bellard | } |
934 | 14ce26e7 | bellard | |
935 | 14ce26e7 | bellard | void op_addq_ESP_8(void) |
936 | 14ce26e7 | bellard | { |
937 | 14ce26e7 | bellard | ESP += 8;
|
938 | 14ce26e7 | bellard | } |
939 | 14ce26e7 | bellard | |
940 | 14ce26e7 | bellard | void op_addq_ESP_im(void) |
941 | 14ce26e7 | bellard | { |
942 | 14ce26e7 | bellard | ESP += PARAM1; |
943 | 14ce26e7 | bellard | } |
944 | 14ce26e7 | bellard | #endif
|
945 | 14ce26e7 | bellard | |
946 | 2c0262af | bellard | void OPPROTO op_rdtsc(void) |
947 | 2c0262af | bellard | { |
948 | 2c0262af | bellard | helper_rdtsc(); |
949 | 2c0262af | bellard | } |
950 | 2c0262af | bellard | |
951 | 2c0262af | bellard | void OPPROTO op_cpuid(void) |
952 | 2c0262af | bellard | { |
953 | 2c0262af | bellard | helper_cpuid(); |
954 | 2c0262af | bellard | } |
955 | 2c0262af | bellard | |
956 | 61a8c4ec | bellard | void OPPROTO op_enter_level(void) |
957 | 61a8c4ec | bellard | { |
958 | 61a8c4ec | bellard | helper_enter_level(PARAM1, PARAM2); |
959 | 61a8c4ec | bellard | } |
960 | 61a8c4ec | bellard | |
961 | 8f091a59 | bellard | #ifdef TARGET_X86_64
|
962 | 8f091a59 | bellard | void OPPROTO op_enter64_level(void) |
963 | 8f091a59 | bellard | { |
964 | 8f091a59 | bellard | helper_enter64_level(PARAM1, PARAM2); |
965 | 8f091a59 | bellard | } |
966 | 8f091a59 | bellard | #endif
|
967 | 8f091a59 | bellard | |
968 | 023fe10d | bellard | void OPPROTO op_sysenter(void) |
969 | 023fe10d | bellard | { |
970 | 023fe10d | bellard | helper_sysenter(); |
971 | 023fe10d | bellard | } |
972 | 023fe10d | bellard | |
973 | 023fe10d | bellard | void OPPROTO op_sysexit(void) |
974 | 023fe10d | bellard | { |
975 | 023fe10d | bellard | helper_sysexit(); |
976 | 023fe10d | bellard | } |
977 | 023fe10d | bellard | |
978 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
979 | 14ce26e7 | bellard | void OPPROTO op_syscall(void) |
980 | 14ce26e7 | bellard | { |
981 | 06c2f506 | bellard | helper_syscall(PARAM1); |
982 | 14ce26e7 | bellard | } |
983 | 14ce26e7 | bellard | |
984 | 14ce26e7 | bellard | void OPPROTO op_sysret(void) |
985 | 14ce26e7 | bellard | { |
986 | 14ce26e7 | bellard | helper_sysret(PARAM1); |
987 | 14ce26e7 | bellard | } |
988 | 14ce26e7 | bellard | #endif
|
989 | 14ce26e7 | bellard | |
990 | 2c0262af | bellard | void OPPROTO op_rdmsr(void) |
991 | 2c0262af | bellard | { |
992 | 2c0262af | bellard | helper_rdmsr(); |
993 | 2c0262af | bellard | } |
994 | 2c0262af | bellard | |
995 | 2c0262af | bellard | void OPPROTO op_wrmsr(void) |
996 | 2c0262af | bellard | { |
997 | 2c0262af | bellard | helper_wrmsr(); |
998 | 2c0262af | bellard | } |
999 | 2c0262af | bellard | |
1000 | 2c0262af | bellard | /* bcd */
|
1001 | 2c0262af | bellard | |
1002 | 2c0262af | bellard | /* XXX: exception */
|
1003 | 2c0262af | bellard | void OPPROTO op_aam(void) |
1004 | 2c0262af | bellard | { |
1005 | 2c0262af | bellard | int base = PARAM1;
|
1006 | 2c0262af | bellard | int al, ah;
|
1007 | 2c0262af | bellard | al = EAX & 0xff;
|
1008 | 2c0262af | bellard | ah = al / base; |
1009 | 2c0262af | bellard | al = al % base; |
1010 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al | (ah << 8); |
1011 | 2c0262af | bellard | CC_DST = al; |
1012 | 2c0262af | bellard | } |
1013 | 2c0262af | bellard | |
1014 | 2c0262af | bellard | void OPPROTO op_aad(void) |
1015 | 2c0262af | bellard | { |
1016 | 2c0262af | bellard | int base = PARAM1;
|
1017 | 2c0262af | bellard | int al, ah;
|
1018 | 2c0262af | bellard | al = EAX & 0xff;
|
1019 | 2c0262af | bellard | ah = (EAX >> 8) & 0xff; |
1020 | 2c0262af | bellard | al = ((ah * base) + al) & 0xff;
|
1021 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al;
|
1022 | 2c0262af | bellard | CC_DST = al; |
1023 | 2c0262af | bellard | } |
1024 | 2c0262af | bellard | |
1025 | 2c0262af | bellard | void OPPROTO op_aaa(void) |
1026 | 2c0262af | bellard | { |
1027 | 2c0262af | bellard | int icarry;
|
1028 | 2c0262af | bellard | int al, ah, af;
|
1029 | 2c0262af | bellard | int eflags;
|
1030 | 2c0262af | bellard | |
1031 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1032 | 2c0262af | bellard | af = eflags & CC_A; |
1033 | 2c0262af | bellard | al = EAX & 0xff;
|
1034 | 2c0262af | bellard | ah = (EAX >> 8) & 0xff; |
1035 | 2c0262af | bellard | |
1036 | 2c0262af | bellard | icarry = (al > 0xf9);
|
1037 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
1038 | 2c0262af | bellard | al = (al + 6) & 0x0f; |
1039 | 2c0262af | bellard | ah = (ah + 1 + icarry) & 0xff; |
1040 | 2c0262af | bellard | eflags |= CC_C | CC_A; |
1041 | 2c0262af | bellard | } else {
|
1042 | 2c0262af | bellard | eflags &= ~(CC_C | CC_A); |
1043 | 2c0262af | bellard | al &= 0x0f;
|
1044 | 2c0262af | bellard | } |
1045 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al | (ah << 8); |
1046 | 2c0262af | bellard | CC_SRC = eflags; |
1047 | 647c5930 | pbrook | FORCE_RET(); |
1048 | 2c0262af | bellard | } |
1049 | 2c0262af | bellard | |
1050 | 2c0262af | bellard | void OPPROTO op_aas(void) |
1051 | 2c0262af | bellard | { |
1052 | 2c0262af | bellard | int icarry;
|
1053 | 2c0262af | bellard | int al, ah, af;
|
1054 | 2c0262af | bellard | int eflags;
|
1055 | 2c0262af | bellard | |
1056 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1057 | 2c0262af | bellard | af = eflags & CC_A; |
1058 | 2c0262af | bellard | al = EAX & 0xff;
|
1059 | 2c0262af | bellard | ah = (EAX >> 8) & 0xff; |
1060 | 2c0262af | bellard | |
1061 | 2c0262af | bellard | icarry = (al < 6);
|
1062 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
1063 | 2c0262af | bellard | al = (al - 6) & 0x0f; |
1064 | 2c0262af | bellard | ah = (ah - 1 - icarry) & 0xff; |
1065 | 2c0262af | bellard | eflags |= CC_C | CC_A; |
1066 | 2c0262af | bellard | } else {
|
1067 | 2c0262af | bellard | eflags &= ~(CC_C | CC_A); |
1068 | 2c0262af | bellard | al &= 0x0f;
|
1069 | 2c0262af | bellard | } |
1070 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al | (ah << 8); |
1071 | 2c0262af | bellard | CC_SRC = eflags; |
1072 | 647c5930 | pbrook | FORCE_RET(); |
1073 | 2c0262af | bellard | } |
1074 | 2c0262af | bellard | |
1075 | 2c0262af | bellard | void OPPROTO op_daa(void) |
1076 | 2c0262af | bellard | { |
1077 | 2c0262af | bellard | int al, af, cf;
|
1078 | 2c0262af | bellard | int eflags;
|
1079 | 2c0262af | bellard | |
1080 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1081 | 2c0262af | bellard | cf = eflags & CC_C; |
1082 | 2c0262af | bellard | af = eflags & CC_A; |
1083 | 2c0262af | bellard | al = EAX & 0xff;
|
1084 | 2c0262af | bellard | |
1085 | 2c0262af | bellard | eflags = 0;
|
1086 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
1087 | 2c0262af | bellard | al = (al + 6) & 0xff; |
1088 | 2c0262af | bellard | eflags |= CC_A; |
1089 | 2c0262af | bellard | } |
1090 | 2c0262af | bellard | if ((al > 0x9f) || cf) { |
1091 | 2c0262af | bellard | al = (al + 0x60) & 0xff; |
1092 | 2c0262af | bellard | eflags |= CC_C; |
1093 | 2c0262af | bellard | } |
1094 | 2c0262af | bellard | EAX = (EAX & ~0xff) | al;
|
1095 | 2c0262af | bellard | /* well, speed is not an issue here, so we compute the flags by hand */
|
1096 | 2c0262af | bellard | eflags |= (al == 0) << 6; /* zf */ |
1097 | 2c0262af | bellard | eflags |= parity_table[al]; /* pf */
|
1098 | 2c0262af | bellard | eflags |= (al & 0x80); /* sf */ |
1099 | 2c0262af | bellard | CC_SRC = eflags; |
1100 | 647c5930 | pbrook | FORCE_RET(); |
1101 | 2c0262af | bellard | } |
1102 | 2c0262af | bellard | |
1103 | 2c0262af | bellard | void OPPROTO op_das(void) |
1104 | 2c0262af | bellard | { |
1105 | 2c0262af | bellard | int al, al1, af, cf;
|
1106 | 2c0262af | bellard | int eflags;
|
1107 | 2c0262af | bellard | |
1108 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1109 | 2c0262af | bellard | cf = eflags & CC_C; |
1110 | 2c0262af | bellard | af = eflags & CC_A; |
1111 | 2c0262af | bellard | al = EAX & 0xff;
|
1112 | 2c0262af | bellard | |
1113 | 2c0262af | bellard | eflags = 0;
|
1114 | 2c0262af | bellard | al1 = al; |
1115 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
1116 | 2c0262af | bellard | eflags |= CC_A; |
1117 | 2c0262af | bellard | if (al < 6 || cf) |
1118 | 2c0262af | bellard | eflags |= CC_C; |
1119 | 2c0262af | bellard | al = (al - 6) & 0xff; |
1120 | 2c0262af | bellard | } |
1121 | 2c0262af | bellard | if ((al1 > 0x99) || cf) { |
1122 | 2c0262af | bellard | al = (al - 0x60) & 0xff; |
1123 | 2c0262af | bellard | eflags |= CC_C; |
1124 | 2c0262af | bellard | } |
1125 | 2c0262af | bellard | EAX = (EAX & ~0xff) | al;
|
1126 | 2c0262af | bellard | /* well, speed is not an issue here, so we compute the flags by hand */
|
1127 | 2c0262af | bellard | eflags |= (al == 0) << 6; /* zf */ |
1128 | 2c0262af | bellard | eflags |= parity_table[al]; /* pf */
|
1129 | 2c0262af | bellard | eflags |= (al & 0x80); /* sf */ |
1130 | 2c0262af | bellard | CC_SRC = eflags; |
1131 | 647c5930 | pbrook | FORCE_RET(); |
1132 | 2c0262af | bellard | } |
1133 | 2c0262af | bellard | |
1134 | 2c0262af | bellard | /* segment handling */
|
1135 | 2c0262af | bellard | |
1136 | 2c0262af | bellard | /* never use it with R_CS */
|
1137 | 2c0262af | bellard | void OPPROTO op_movl_seg_T0(void) |
1138 | 2c0262af | bellard | { |
1139 | 3415a4dd | bellard | load_seg(PARAM1, T0); |
1140 | 2c0262af | bellard | } |
1141 | 2c0262af | bellard | |
1142 | 2c0262af | bellard | /* faster VM86 version */
|
1143 | 2c0262af | bellard | void OPPROTO op_movl_seg_T0_vm(void) |
1144 | 2c0262af | bellard | { |
1145 | 2c0262af | bellard | int selector;
|
1146 | 2c0262af | bellard | SegmentCache *sc; |
1147 | 2c0262af | bellard | |
1148 | 2c0262af | bellard | selector = T0 & 0xffff;
|
1149 | 2c0262af | bellard | /* env->segs[] access */
|
1150 | 2c0262af | bellard | sc = (SegmentCache *)((char *)env + PARAM1);
|
1151 | 2c0262af | bellard | sc->selector = selector; |
1152 | 14ce26e7 | bellard | sc->base = (selector << 4);
|
1153 | 2c0262af | bellard | } |
1154 | 2c0262af | bellard | |
1155 | 2c0262af | bellard | void OPPROTO op_movl_T0_seg(void) |
1156 | 2c0262af | bellard | { |
1157 | 2c0262af | bellard | T0 = env->segs[PARAM1].selector; |
1158 | 2c0262af | bellard | } |
1159 | 2c0262af | bellard | |
1160 | 2c0262af | bellard | void OPPROTO op_lsl(void) |
1161 | 2c0262af | bellard | { |
1162 | 2c0262af | bellard | helper_lsl(); |
1163 | 2c0262af | bellard | } |
1164 | 2c0262af | bellard | |
1165 | 2c0262af | bellard | void OPPROTO op_lar(void) |
1166 | 2c0262af | bellard | { |
1167 | 2c0262af | bellard | helper_lar(); |
1168 | 2c0262af | bellard | } |
1169 | 2c0262af | bellard | |
1170 | 3ab493de | bellard | void OPPROTO op_verr(void) |
1171 | 3ab493de | bellard | { |
1172 | 3ab493de | bellard | helper_verr(); |
1173 | 3ab493de | bellard | } |
1174 | 3ab493de | bellard | |
1175 | 3ab493de | bellard | void OPPROTO op_verw(void) |
1176 | 3ab493de | bellard | { |
1177 | 3ab493de | bellard | helper_verw(); |
1178 | 3ab493de | bellard | } |
1179 | 3ab493de | bellard | |
1180 | 3ab493de | bellard | void OPPROTO op_arpl(void) |
1181 | 3ab493de | bellard | { |
1182 | 3ab493de | bellard | if ((T0 & 3) < (T1 & 3)) { |
1183 | 3ab493de | bellard | /* XXX: emulate bug or 0xff3f0000 oring as in bochs ? */
|
1184 | 3ab493de | bellard | T0 = (T0 & ~3) | (T1 & 3); |
1185 | 3ab493de | bellard | T1 = CC_Z; |
1186 | 3ab493de | bellard | } else {
|
1187 | 3ab493de | bellard | T1 = 0;
|
1188 | 3ab493de | bellard | } |
1189 | 3ab493de | bellard | FORCE_RET(); |
1190 | 3ab493de | bellard | } |
1191 | 3ab493de | bellard | |
1192 | 3ab493de | bellard | void OPPROTO op_arpl_update(void) |
1193 | 3ab493de | bellard | { |
1194 | 3ab493de | bellard | int eflags;
|
1195 | 3ab493de | bellard | eflags = cc_table[CC_OP].compute_all(); |
1196 | 3ab493de | bellard | CC_SRC = (eflags & ~CC_Z) | T1; |
1197 | 3ab493de | bellard | } |
1198 | 3ab493de | bellard | |
1199 | 2c0262af | bellard | /* T0: segment, T1:eip */
|
1200 | 2c0262af | bellard | void OPPROTO op_ljmp_protected_T0_T1(void) |
1201 | 2c0262af | bellard | { |
1202 | 08cea4ee | bellard | helper_ljmp_protected_T0_T1(PARAM1); |
1203 | 2c0262af | bellard | } |
1204 | 2c0262af | bellard | |
1205 | 2c0262af | bellard | void OPPROTO op_lcall_real_T0_T1(void) |
1206 | 2c0262af | bellard | { |
1207 | 2c0262af | bellard | helper_lcall_real_T0_T1(PARAM1, PARAM2); |
1208 | 2c0262af | bellard | } |
1209 | 2c0262af | bellard | |
1210 | 2c0262af | bellard | void OPPROTO op_lcall_protected_T0_T1(void) |
1211 | 2c0262af | bellard | { |
1212 | 2c0262af | bellard | helper_lcall_protected_T0_T1(PARAM1, PARAM2); |
1213 | 2c0262af | bellard | } |
1214 | 2c0262af | bellard | |
1215 | 2c0262af | bellard | void OPPROTO op_iret_real(void) |
1216 | 2c0262af | bellard | { |
1217 | 2c0262af | bellard | helper_iret_real(PARAM1); |
1218 | 2c0262af | bellard | } |
1219 | 2c0262af | bellard | |
1220 | 2c0262af | bellard | void OPPROTO op_iret_protected(void) |
1221 | 2c0262af | bellard | { |
1222 | 08cea4ee | bellard | helper_iret_protected(PARAM1, PARAM2); |
1223 | 2c0262af | bellard | } |
1224 | 2c0262af | bellard | |
1225 | 2c0262af | bellard | void OPPROTO op_lret_protected(void) |
1226 | 2c0262af | bellard | { |
1227 | 2c0262af | bellard | helper_lret_protected(PARAM1, PARAM2); |
1228 | 2c0262af | bellard | } |
1229 | 2c0262af | bellard | |
1230 | 2c0262af | bellard | void OPPROTO op_lldt_T0(void) |
1231 | 2c0262af | bellard | { |
1232 | 2c0262af | bellard | helper_lldt_T0(); |
1233 | 2c0262af | bellard | } |
1234 | 2c0262af | bellard | |
1235 | 2c0262af | bellard | void OPPROTO op_ltr_T0(void) |
1236 | 2c0262af | bellard | { |
1237 | 2c0262af | bellard | helper_ltr_T0(); |
1238 | 2c0262af | bellard | } |
1239 | 2c0262af | bellard | |
1240 | 2c0262af | bellard | /* CR registers access */
|
1241 | 2c0262af | bellard | void OPPROTO op_movl_crN_T0(void) |
1242 | 2c0262af | bellard | { |
1243 | 2c0262af | bellard | helper_movl_crN_T0(PARAM1); |
1244 | 2c0262af | bellard | } |
1245 | 2c0262af | bellard | |
1246 | 82e41634 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1247 | 39c61f49 | bellard | void OPPROTO op_movtl_T0_cr8(void) |
1248 | 39c61f49 | bellard | { |
1249 | 39c61f49 | bellard | T0 = cpu_get_apic_tpr(env); |
1250 | 39c61f49 | bellard | } |
1251 | 82e41634 | bellard | #endif
|
1252 | 39c61f49 | bellard | |
1253 | 2c0262af | bellard | /* DR registers access */
|
1254 | 2c0262af | bellard | void OPPROTO op_movl_drN_T0(void) |
1255 | 2c0262af | bellard | { |
1256 | 2c0262af | bellard | helper_movl_drN_T0(PARAM1); |
1257 | 2c0262af | bellard | } |
1258 | 2c0262af | bellard | |
1259 | 2c0262af | bellard | void OPPROTO op_lmsw_T0(void) |
1260 | 2c0262af | bellard | { |
1261 | 710c15a2 | bellard | /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
|
1262 | 710c15a2 | bellard | if already set to one. */
|
1263 | 710c15a2 | bellard | T0 = (env->cr[0] & ~0xe) | (T0 & 0xf); |
1264 | 2c0262af | bellard | helper_movl_crN_T0(0);
|
1265 | 2c0262af | bellard | } |
1266 | 2c0262af | bellard | |
1267 | 2c0262af | bellard | void OPPROTO op_invlpg_A0(void) |
1268 | 2c0262af | bellard | { |
1269 | 2c0262af | bellard | helper_invlpg(A0); |
1270 | 2c0262af | bellard | } |
1271 | 2c0262af | bellard | |
1272 | 2c0262af | bellard | void OPPROTO op_movl_T0_env(void) |
1273 | 2c0262af | bellard | { |
1274 | 2c0262af | bellard | T0 = *(uint32_t *)((char *)env + PARAM1);
|
1275 | 2c0262af | bellard | } |
1276 | 2c0262af | bellard | |
1277 | 2c0262af | bellard | void OPPROTO op_movl_env_T0(void) |
1278 | 2c0262af | bellard | { |
1279 | 2c0262af | bellard | *(uint32_t *)((char *)env + PARAM1) = T0;
|
1280 | 2c0262af | bellard | } |
1281 | 2c0262af | bellard | |
1282 | 2c0262af | bellard | void OPPROTO op_movl_env_T1(void) |
1283 | 2c0262af | bellard | { |
1284 | 2c0262af | bellard | *(uint32_t *)((char *)env + PARAM1) = T1;
|
1285 | 2c0262af | bellard | } |
1286 | 2c0262af | bellard | |
1287 | 14ce26e7 | bellard | void OPPROTO op_movtl_T0_env(void) |
1288 | 14ce26e7 | bellard | { |
1289 | 14ce26e7 | bellard | T0 = *(target_ulong *)((char *)env + PARAM1);
|
1290 | 14ce26e7 | bellard | } |
1291 | 14ce26e7 | bellard | |
1292 | 14ce26e7 | bellard | void OPPROTO op_movtl_env_T0(void) |
1293 | 14ce26e7 | bellard | { |
1294 | 14ce26e7 | bellard | *(target_ulong *)((char *)env + PARAM1) = T0;
|
1295 | 14ce26e7 | bellard | } |
1296 | 14ce26e7 | bellard | |
1297 | 14ce26e7 | bellard | void OPPROTO op_movtl_T1_env(void) |
1298 | 14ce26e7 | bellard | { |
1299 | 14ce26e7 | bellard | T1 = *(target_ulong *)((char *)env + PARAM1);
|
1300 | 14ce26e7 | bellard | } |
1301 | 14ce26e7 | bellard | |
1302 | 14ce26e7 | bellard | void OPPROTO op_movtl_env_T1(void) |
1303 | 14ce26e7 | bellard | { |
1304 | 14ce26e7 | bellard | *(target_ulong *)((char *)env + PARAM1) = T1;
|
1305 | 14ce26e7 | bellard | } |
1306 | 14ce26e7 | bellard | |
1307 | 2c0262af | bellard | void OPPROTO op_clts(void) |
1308 | 2c0262af | bellard | { |
1309 | 2c0262af | bellard | env->cr[0] &= ~CR0_TS_MASK;
|
1310 | 7eee2a50 | bellard | env->hflags &= ~HF_TS_MASK; |
1311 | 2c0262af | bellard | } |
1312 | 2c0262af | bellard | |
1313 | 2c0262af | bellard | /* flags handling */
|
1314 | 2c0262af | bellard | |
1315 | 14ce26e7 | bellard | void OPPROTO op_goto_tb0(void) |
1316 | 2c0262af | bellard | { |
1317 | ae063a68 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
1318 | 14ce26e7 | bellard | } |
1319 | 14ce26e7 | bellard | |
1320 | 14ce26e7 | bellard | void OPPROTO op_goto_tb1(void) |
1321 | 14ce26e7 | bellard | { |
1322 | ae063a68 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
1323 | 14ce26e7 | bellard | } |
1324 | 14ce26e7 | bellard | |
1325 | 14ce26e7 | bellard | void OPPROTO op_jmp_label(void) |
1326 | 14ce26e7 | bellard | { |
1327 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
|
1328 | 2c0262af | bellard | } |
1329 | 2c0262af | bellard | |
1330 | 14ce26e7 | bellard | void OPPROTO op_jnz_T0_label(void) |
1331 | 2c0262af | bellard | { |
1332 | 2c0262af | bellard | if (T0)
|
1333 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
|
1334 | 39c61f49 | bellard | FORCE_RET(); |
1335 | 14ce26e7 | bellard | } |
1336 | 14ce26e7 | bellard | |
1337 | 14ce26e7 | bellard | void OPPROTO op_jz_T0_label(void) |
1338 | 14ce26e7 | bellard | { |
1339 | 14ce26e7 | bellard | if (!T0)
|
1340 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
|
1341 | 39c61f49 | bellard | FORCE_RET(); |
1342 | 2c0262af | bellard | } |
1343 | 2c0262af | bellard | |
1344 | 2c0262af | bellard | /* slow set cases (compute x86 flags) */
|
1345 | 2c0262af | bellard | void OPPROTO op_seto_T0_cc(void) |
1346 | 2c0262af | bellard | { |
1347 | 2c0262af | bellard | int eflags;
|
1348 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1349 | 2c0262af | bellard | T0 = (eflags >> 11) & 1; |
1350 | 2c0262af | bellard | } |
1351 | 2c0262af | bellard | |
1352 | 2c0262af | bellard | void OPPROTO op_setb_T0_cc(void) |
1353 | 2c0262af | bellard | { |
1354 | 2c0262af | bellard | T0 = cc_table[CC_OP].compute_c(); |
1355 | 2c0262af | bellard | } |
1356 | 2c0262af | bellard | |
1357 | 2c0262af | bellard | void OPPROTO op_setz_T0_cc(void) |
1358 | 2c0262af | bellard | { |
1359 | 2c0262af | bellard | int eflags;
|
1360 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1361 | 2c0262af | bellard | T0 = (eflags >> 6) & 1; |
1362 | 2c0262af | bellard | } |
1363 | 2c0262af | bellard | |
1364 | 2c0262af | bellard | void OPPROTO op_setbe_T0_cc(void) |
1365 | 2c0262af | bellard | { |
1366 | 2c0262af | bellard | int eflags;
|
1367 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1368 | 2c0262af | bellard | T0 = (eflags & (CC_Z | CC_C)) != 0;
|
1369 | 2c0262af | bellard | } |
1370 | 2c0262af | bellard | |
1371 | 2c0262af | bellard | void OPPROTO op_sets_T0_cc(void) |
1372 | 2c0262af | bellard | { |
1373 | 2c0262af | bellard | int eflags;
|
1374 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1375 | 2c0262af | bellard | T0 = (eflags >> 7) & 1; |
1376 | 2c0262af | bellard | } |
1377 | 2c0262af | bellard | |
1378 | 2c0262af | bellard | void OPPROTO op_setp_T0_cc(void) |
1379 | 2c0262af | bellard | { |
1380 | 2c0262af | bellard | int eflags;
|
1381 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1382 | 2c0262af | bellard | T0 = (eflags >> 2) & 1; |
1383 | 2c0262af | bellard | } |
1384 | 2c0262af | bellard | |
1385 | 2c0262af | bellard | void OPPROTO op_setl_T0_cc(void) |
1386 | 2c0262af | bellard | { |
1387 | 2c0262af | bellard | int eflags;
|
1388 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1389 | 2c0262af | bellard | T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1; |
1390 | 2c0262af | bellard | } |
1391 | 2c0262af | bellard | |
1392 | 2c0262af | bellard | void OPPROTO op_setle_T0_cc(void) |
1393 | 2c0262af | bellard | { |
1394 | 2c0262af | bellard | int eflags;
|
1395 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1396 | 2c0262af | bellard | T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0; |
1397 | 2c0262af | bellard | } |
1398 | 2c0262af | bellard | |
1399 | 2c0262af | bellard | void OPPROTO op_xor_T0_1(void) |
1400 | 2c0262af | bellard | { |
1401 | 2c0262af | bellard | T0 ^= 1;
|
1402 | 2c0262af | bellard | } |
1403 | 2c0262af | bellard | |
1404 | 2c0262af | bellard | void OPPROTO op_set_cc_op(void) |
1405 | 2c0262af | bellard | { |
1406 | 2c0262af | bellard | CC_OP = PARAM1; |
1407 | 2c0262af | bellard | } |
1408 | 2c0262af | bellard | |
1409 | 0b9dc5e4 | bellard | void OPPROTO op_mov_T0_cc(void) |
1410 | 0b9dc5e4 | bellard | { |
1411 | 0b9dc5e4 | bellard | T0 = cc_table[CC_OP].compute_all(); |
1412 | 0b9dc5e4 | bellard | } |
1413 | 0b9dc5e4 | bellard | |
1414 | 4136f33c | bellard | /* XXX: clear VIF/VIP in all ops ? */
|
1415 | 2c0262af | bellard | |
1416 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0(void) |
1417 | 2c0262af | bellard | { |
1418 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK)); |
1419 | 2c0262af | bellard | } |
1420 | 2c0262af | bellard | |
1421 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0(void) |
1422 | 2c0262af | bellard | { |
1423 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff);
|
1424 | 4136f33c | bellard | } |
1425 | 4136f33c | bellard | |
1426 | 4136f33c | bellard | void OPPROTO op_movl_eflags_T0_io(void) |
1427 | 4136f33c | bellard | { |
1428 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)); |
1429 | 4136f33c | bellard | } |
1430 | 4136f33c | bellard | |
1431 | 4136f33c | bellard | void OPPROTO op_movw_eflags_T0_io(void) |
1432 | 4136f33c | bellard | { |
1433 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff);
|
1434 | 2c0262af | bellard | } |
1435 | 2c0262af | bellard | |
1436 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0_cpl0(void) |
1437 | 2c0262af | bellard | { |
1438 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)); |
1439 | 2c0262af | bellard | } |
1440 | 2c0262af | bellard | |
1441 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0_cpl0(void) |
1442 | 2c0262af | bellard | { |
1443 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff);
|
1444 | 2c0262af | bellard | } |
1445 | 2c0262af | bellard | |
1446 | 2c0262af | bellard | #if 0
|
1447 | 2c0262af | bellard | /* vm86plus version */
|
1448 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0_vm(void)
|
1449 | 2c0262af | bellard | {
|
1450 | 2c0262af | bellard | int eflags;
|
1451 | 2c0262af | bellard | eflags = T0;
|
1452 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
1453 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1));
|
1454 | 2c0262af | bellard | /* we also update some system flags as in user mode */
|
1455 | 2c0262af | bellard | env->eflags = (env->eflags & ~(FL_UPDATE_MASK16 | VIF_MASK)) |
|
1456 | 2c0262af | bellard | (eflags & FL_UPDATE_MASK16);
|
1457 | 2c0262af | bellard | if (eflags & IF_MASK) {
|
1458 | 2c0262af | bellard | env->eflags |= VIF_MASK;
|
1459 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
|
1460 | 2c0262af | bellard | EIP = PARAM1;
|
1461 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
|
1462 | 2c0262af | bellard | }
|
1463 | 2c0262af | bellard | }
|
1464 | 2c0262af | bellard | FORCE_RET();
|
1465 | 2c0262af | bellard | }
|
1466 | 2c0262af | bellard | |
1467 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0_vm(void)
|
1468 | 2c0262af | bellard | {
|
1469 | 2c0262af | bellard | int eflags;
|
1470 | 2c0262af | bellard | eflags = T0;
|
1471 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
1472 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1));
|
1473 | 2c0262af | bellard | /* we also update some system flags as in user mode */
|
1474 | 2c0262af | bellard | env->eflags = (env->eflags & ~(FL_UPDATE_MASK32 | VIF_MASK)) |
|
1475 | 2c0262af | bellard | (eflags & FL_UPDATE_MASK32);
|
1476 | 2c0262af | bellard | if (eflags & IF_MASK) {
|
1477 | 2c0262af | bellard | env->eflags |= VIF_MASK;
|
1478 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
|
1479 | 2c0262af | bellard | EIP = PARAM1;
|
1480 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
|
1481 | 2c0262af | bellard | }
|
1482 | 2c0262af | bellard | }
|
1483 | 2c0262af | bellard | FORCE_RET();
|
1484 | 2c0262af | bellard | }
|
1485 | 2c0262af | bellard | #endif
|
1486 | 2c0262af | bellard | |
1487 | 2c0262af | bellard | /* XXX: compute only O flag */
|
1488 | 2c0262af | bellard | void OPPROTO op_movb_eflags_T0(void) |
1489 | 2c0262af | bellard | { |
1490 | 2c0262af | bellard | int of;
|
1491 | 2c0262af | bellard | of = cc_table[CC_OP].compute_all() & CC_O; |
1492 | 2c0262af | bellard | CC_SRC = (T0 & (CC_S | CC_Z | CC_A | CC_P | CC_C)) | of; |
1493 | 2c0262af | bellard | } |
1494 | 2c0262af | bellard | |
1495 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags(void) |
1496 | 2c0262af | bellard | { |
1497 | 2c0262af | bellard | int eflags;
|
1498 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1499 | 2c0262af | bellard | eflags |= (DF & DF_MASK); |
1500 | 2c0262af | bellard | eflags |= env->eflags & ~(VM_MASK | RF_MASK); |
1501 | 2c0262af | bellard | T0 = eflags; |
1502 | 2c0262af | bellard | } |
1503 | 2c0262af | bellard | |
1504 | 2c0262af | bellard | /* vm86plus version */
|
1505 | 2c0262af | bellard | #if 0
|
1506 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags_vm(void)
|
1507 | 2c0262af | bellard | {
|
1508 | 2c0262af | bellard | int eflags;
|
1509 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all();
|
1510 | 2c0262af | bellard | eflags |= (DF & DF_MASK);
|
1511 | 2c0262af | bellard | eflags |= env->eflags & ~(VM_MASK | RF_MASK | IF_MASK);
|
1512 | 2c0262af | bellard | if (env->eflags & VIF_MASK)
|
1513 | 2c0262af | bellard | eflags |= IF_MASK;
|
1514 | 2c0262af | bellard | T0 = eflags;
|
1515 | 2c0262af | bellard | }
|
1516 | 2c0262af | bellard | #endif
|
1517 | 2c0262af | bellard | |
1518 | 2c0262af | bellard | void OPPROTO op_cld(void) |
1519 | 2c0262af | bellard | { |
1520 | 2c0262af | bellard | DF = 1;
|
1521 | 2c0262af | bellard | } |
1522 | 2c0262af | bellard | |
1523 | 2c0262af | bellard | void OPPROTO op_std(void) |
1524 | 2c0262af | bellard | { |
1525 | 2c0262af | bellard | DF = -1;
|
1526 | 2c0262af | bellard | } |
1527 | 2c0262af | bellard | |
1528 | 2c0262af | bellard | void OPPROTO op_clc(void) |
1529 | 2c0262af | bellard | { |
1530 | 2c0262af | bellard | int eflags;
|
1531 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1532 | 2c0262af | bellard | eflags &= ~CC_C; |
1533 | 2c0262af | bellard | CC_SRC = eflags; |
1534 | 2c0262af | bellard | } |
1535 | 2c0262af | bellard | |
1536 | 2c0262af | bellard | void OPPROTO op_stc(void) |
1537 | 2c0262af | bellard | { |
1538 | 2c0262af | bellard | int eflags;
|
1539 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1540 | 2c0262af | bellard | eflags |= CC_C; |
1541 | 2c0262af | bellard | CC_SRC = eflags; |
1542 | 2c0262af | bellard | } |
1543 | 2c0262af | bellard | |
1544 | 2c0262af | bellard | void OPPROTO op_cmc(void) |
1545 | 2c0262af | bellard | { |
1546 | 2c0262af | bellard | int eflags;
|
1547 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1548 | 2c0262af | bellard | eflags ^= CC_C; |
1549 | 2c0262af | bellard | CC_SRC = eflags; |
1550 | 2c0262af | bellard | } |
1551 | 2c0262af | bellard | |
1552 | 2c0262af | bellard | void OPPROTO op_salc(void) |
1553 | 2c0262af | bellard | { |
1554 | 2c0262af | bellard | int cf;
|
1555 | 2c0262af | bellard | cf = cc_table[CC_OP].compute_c(); |
1556 | 2c0262af | bellard | EAX = (EAX & ~0xff) | ((-cf) & 0xff); |
1557 | 2c0262af | bellard | } |
1558 | 2c0262af | bellard | |
1559 | 2c0262af | bellard | static int compute_all_eflags(void) |
1560 | 2c0262af | bellard | { |
1561 | 2c0262af | bellard | return CC_SRC;
|
1562 | 2c0262af | bellard | } |
1563 | 2c0262af | bellard | |
1564 | 2c0262af | bellard | static int compute_c_eflags(void) |
1565 | 2c0262af | bellard | { |
1566 | 2c0262af | bellard | return CC_SRC & CC_C;
|
1567 | 2c0262af | bellard | } |
1568 | 2c0262af | bellard | |
1569 | 2c0262af | bellard | CCTable cc_table[CC_OP_NB] = { |
1570 | 2c0262af | bellard | [CC_OP_DYNAMIC] = { /* should never happen */ },
|
1571 | 2c0262af | bellard | |
1572 | 2c0262af | bellard | [CC_OP_EFLAGS] = { compute_all_eflags, compute_c_eflags }, |
1573 | 2c0262af | bellard | |
1574 | d36cd60e | bellard | [CC_OP_MULB] = { compute_all_mulb, compute_c_mull }, |
1575 | d36cd60e | bellard | [CC_OP_MULW] = { compute_all_mulw, compute_c_mull }, |
1576 | d36cd60e | bellard | [CC_OP_MULL] = { compute_all_mull, compute_c_mull }, |
1577 | 2c0262af | bellard | |
1578 | 2c0262af | bellard | [CC_OP_ADDB] = { compute_all_addb, compute_c_addb }, |
1579 | 2c0262af | bellard | [CC_OP_ADDW] = { compute_all_addw, compute_c_addw }, |
1580 | 2c0262af | bellard | [CC_OP_ADDL] = { compute_all_addl, compute_c_addl }, |
1581 | 2c0262af | bellard | |
1582 | 2c0262af | bellard | [CC_OP_ADCB] = { compute_all_adcb, compute_c_adcb }, |
1583 | 2c0262af | bellard | [CC_OP_ADCW] = { compute_all_adcw, compute_c_adcw }, |
1584 | 2c0262af | bellard | [CC_OP_ADCL] = { compute_all_adcl, compute_c_adcl }, |
1585 | 2c0262af | bellard | |
1586 | 2c0262af | bellard | [CC_OP_SUBB] = { compute_all_subb, compute_c_subb }, |
1587 | 2c0262af | bellard | [CC_OP_SUBW] = { compute_all_subw, compute_c_subw }, |
1588 | 2c0262af | bellard | [CC_OP_SUBL] = { compute_all_subl, compute_c_subl }, |
1589 | 2c0262af | bellard | |
1590 | 2c0262af | bellard | [CC_OP_SBBB] = { compute_all_sbbb, compute_c_sbbb }, |
1591 | 2c0262af | bellard | [CC_OP_SBBW] = { compute_all_sbbw, compute_c_sbbw }, |
1592 | 2c0262af | bellard | [CC_OP_SBBL] = { compute_all_sbbl, compute_c_sbbl }, |
1593 | 2c0262af | bellard | |
1594 | 2c0262af | bellard | [CC_OP_LOGICB] = { compute_all_logicb, compute_c_logicb }, |
1595 | 2c0262af | bellard | [CC_OP_LOGICW] = { compute_all_logicw, compute_c_logicw }, |
1596 | 2c0262af | bellard | [CC_OP_LOGICL] = { compute_all_logicl, compute_c_logicl }, |
1597 | 2c0262af | bellard | |
1598 | 2c0262af | bellard | [CC_OP_INCB] = { compute_all_incb, compute_c_incl }, |
1599 | 2c0262af | bellard | [CC_OP_INCW] = { compute_all_incw, compute_c_incl }, |
1600 | 2c0262af | bellard | [CC_OP_INCL] = { compute_all_incl, compute_c_incl }, |
1601 | 2c0262af | bellard | |
1602 | 2c0262af | bellard | [CC_OP_DECB] = { compute_all_decb, compute_c_incl }, |
1603 | 2c0262af | bellard | [CC_OP_DECW] = { compute_all_decw, compute_c_incl }, |
1604 | 2c0262af | bellard | [CC_OP_DECL] = { compute_all_decl, compute_c_incl }, |
1605 | 2c0262af | bellard | |
1606 | 2c0262af | bellard | [CC_OP_SHLB] = { compute_all_shlb, compute_c_shlb }, |
1607 | 2c0262af | bellard | [CC_OP_SHLW] = { compute_all_shlw, compute_c_shlw }, |
1608 | 2c0262af | bellard | [CC_OP_SHLL] = { compute_all_shll, compute_c_shll }, |
1609 | 2c0262af | bellard | |
1610 | 2c0262af | bellard | [CC_OP_SARB] = { compute_all_sarb, compute_c_sarl }, |
1611 | 2c0262af | bellard | [CC_OP_SARW] = { compute_all_sarw, compute_c_sarl }, |
1612 | 2c0262af | bellard | [CC_OP_SARL] = { compute_all_sarl, compute_c_sarl }, |
1613 | 14ce26e7 | bellard | |
1614 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1615 | 14ce26e7 | bellard | [CC_OP_MULQ] = { compute_all_mulq, compute_c_mull }, |
1616 | 14ce26e7 | bellard | |
1617 | 14ce26e7 | bellard | [CC_OP_ADDQ] = { compute_all_addq, compute_c_addq }, |
1618 | 14ce26e7 | bellard | |
1619 | 14ce26e7 | bellard | [CC_OP_ADCQ] = { compute_all_adcq, compute_c_adcq }, |
1620 | 14ce26e7 | bellard | |
1621 | 14ce26e7 | bellard | [CC_OP_SUBQ] = { compute_all_subq, compute_c_subq }, |
1622 | 14ce26e7 | bellard | |
1623 | 14ce26e7 | bellard | [CC_OP_SBBQ] = { compute_all_sbbq, compute_c_sbbq }, |
1624 | 14ce26e7 | bellard | |
1625 | 14ce26e7 | bellard | [CC_OP_LOGICQ] = { compute_all_logicq, compute_c_logicq }, |
1626 | 14ce26e7 | bellard | |
1627 | 14ce26e7 | bellard | [CC_OP_INCQ] = { compute_all_incq, compute_c_incl }, |
1628 | 14ce26e7 | bellard | |
1629 | 14ce26e7 | bellard | [CC_OP_DECQ] = { compute_all_decq, compute_c_incl }, |
1630 | 14ce26e7 | bellard | |
1631 | 14ce26e7 | bellard | [CC_OP_SHLQ] = { compute_all_shlq, compute_c_shlq }, |
1632 | 14ce26e7 | bellard | |
1633 | 14ce26e7 | bellard | [CC_OP_SARQ] = { compute_all_sarq, compute_c_sarl }, |
1634 | 14ce26e7 | bellard | #endif
|
1635 | 2c0262af | bellard | }; |
1636 | 2c0262af | bellard | |
1637 | 2c0262af | bellard | /* floating point support. Some of the code for complicated x87
|
1638 | 2c0262af | bellard | functions comes from the LGPL'ed x86 emulator found in the Willows
|
1639 | 2c0262af | bellard | TWIN windows emulator. */
|
1640 | 2c0262af | bellard | |
1641 | 2c0262af | bellard | /* fp load FT0 */
|
1642 | 2c0262af | bellard | |
1643 | 2c0262af | bellard | void OPPROTO op_flds_FT0_A0(void) |
1644 | 2c0262af | bellard | { |
1645 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1646 | 14ce26e7 | bellard | FP_CONVERT.i32 = ldl(A0); |
1647 | 2c0262af | bellard | FT0 = FP_CONVERT.f; |
1648 | 2c0262af | bellard | #else
|
1649 | 14ce26e7 | bellard | FT0 = ldfl(A0); |
1650 | 2c0262af | bellard | #endif
|
1651 | 2c0262af | bellard | } |
1652 | 2c0262af | bellard | |
1653 | 2c0262af | bellard | void OPPROTO op_fldl_FT0_A0(void) |
1654 | 2c0262af | bellard | { |
1655 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1656 | 14ce26e7 | bellard | FP_CONVERT.i64 = ldq(A0); |
1657 | 2c0262af | bellard | FT0 = FP_CONVERT.d; |
1658 | 2c0262af | bellard | #else
|
1659 | 14ce26e7 | bellard | FT0 = ldfq(A0); |
1660 | 2c0262af | bellard | #endif
|
1661 | 2c0262af | bellard | } |
1662 | 2c0262af | bellard | |
1663 | 2c0262af | bellard | /* helpers are needed to avoid static constant reference. XXX: find a better way */
|
1664 | 2c0262af | bellard | #ifdef USE_INT_TO_FLOAT_HELPERS
|
1665 | 2c0262af | bellard | |
1666 | 2c0262af | bellard | void helper_fild_FT0_A0(void) |
1667 | 2c0262af | bellard | { |
1668 | 14ce26e7 | bellard | FT0 = (CPU86_LDouble)ldsw(A0); |
1669 | 2c0262af | bellard | } |
1670 | 2c0262af | bellard | |
1671 | 2c0262af | bellard | void helper_fildl_FT0_A0(void) |
1672 | 2c0262af | bellard | { |
1673 | 14ce26e7 | bellard | FT0 = (CPU86_LDouble)((int32_t)ldl(A0)); |
1674 | 2c0262af | bellard | } |
1675 | 2c0262af | bellard | |
1676 | 2c0262af | bellard | void helper_fildll_FT0_A0(void) |
1677 | 2c0262af | bellard | { |
1678 | 14ce26e7 | bellard | FT0 = (CPU86_LDouble)((int64_t)ldq(A0)); |
1679 | 2c0262af | bellard | } |
1680 | 2c0262af | bellard | |
1681 | 2c0262af | bellard | void OPPROTO op_fild_FT0_A0(void) |
1682 | 2c0262af | bellard | { |
1683 | 2c0262af | bellard | helper_fild_FT0_A0(); |
1684 | 2c0262af | bellard | } |
1685 | 2c0262af | bellard | |
1686 | 2c0262af | bellard | void OPPROTO op_fildl_FT0_A0(void) |
1687 | 2c0262af | bellard | { |
1688 | 2c0262af | bellard | helper_fildl_FT0_A0(); |
1689 | 2c0262af | bellard | } |
1690 | 2c0262af | bellard | |
1691 | 2c0262af | bellard | void OPPROTO op_fildll_FT0_A0(void) |
1692 | 2c0262af | bellard | { |
1693 | 2c0262af | bellard | helper_fildll_FT0_A0(); |
1694 | 2c0262af | bellard | } |
1695 | 2c0262af | bellard | |
1696 | 2c0262af | bellard | #else
|
1697 | 2c0262af | bellard | |
1698 | 2c0262af | bellard | void OPPROTO op_fild_FT0_A0(void) |
1699 | 2c0262af | bellard | { |
1700 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1701 | 14ce26e7 | bellard | FP_CONVERT.i32 = ldsw(A0); |
1702 | 2c0262af | bellard | FT0 = (CPU86_LDouble)FP_CONVERT.i32; |
1703 | 2c0262af | bellard | #else
|
1704 | 14ce26e7 | bellard | FT0 = (CPU86_LDouble)ldsw(A0); |
1705 | 2c0262af | bellard | #endif
|
1706 | 2c0262af | bellard | } |
1707 | 2c0262af | bellard | |
1708 | 2c0262af | bellard | void OPPROTO op_fildl_FT0_A0(void) |
1709 | 2c0262af | bellard | { |
1710 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1711 | 14ce26e7 | bellard | FP_CONVERT.i32 = (int32_t) ldl(A0); |
1712 | 2c0262af | bellard | FT0 = (CPU86_LDouble)FP_CONVERT.i32; |
1713 | 2c0262af | bellard | #else
|
1714 | 14ce26e7 | bellard | FT0 = (CPU86_LDouble)((int32_t)ldl(A0)); |
1715 | 2c0262af | bellard | #endif
|
1716 | 2c0262af | bellard | } |
1717 | 2c0262af | bellard | |
1718 | 2c0262af | bellard | void OPPROTO op_fildll_FT0_A0(void) |
1719 | 2c0262af | bellard | { |
1720 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1721 | 14ce26e7 | bellard | FP_CONVERT.i64 = (int64_t) ldq(A0); |
1722 | 2c0262af | bellard | FT0 = (CPU86_LDouble)FP_CONVERT.i64; |
1723 | 2c0262af | bellard | #else
|
1724 | 14ce26e7 | bellard | FT0 = (CPU86_LDouble)((int64_t)ldq(A0)); |
1725 | 2c0262af | bellard | #endif
|
1726 | 2c0262af | bellard | } |
1727 | 2c0262af | bellard | #endif
|
1728 | 2c0262af | bellard | |
1729 | 2c0262af | bellard | /* fp load ST0 */
|
1730 | 2c0262af | bellard | |
1731 | 2c0262af | bellard | void OPPROTO op_flds_ST0_A0(void) |
1732 | 2c0262af | bellard | { |
1733 | 2c0262af | bellard | int new_fpstt;
|
1734 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1735 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1736 | 14ce26e7 | bellard | FP_CONVERT.i32 = ldl(A0); |
1737 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = FP_CONVERT.f; |
1738 | 2c0262af | bellard | #else
|
1739 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = ldfl(A0); |
1740 | 2c0262af | bellard | #endif
|
1741 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1742 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1743 | 2c0262af | bellard | } |
1744 | 2c0262af | bellard | |
1745 | 2c0262af | bellard | void OPPROTO op_fldl_ST0_A0(void) |
1746 | 2c0262af | bellard | { |
1747 | 2c0262af | bellard | int new_fpstt;
|
1748 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1749 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1750 | 14ce26e7 | bellard | FP_CONVERT.i64 = ldq(A0); |
1751 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = FP_CONVERT.d; |
1752 | 2c0262af | bellard | #else
|
1753 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = ldfq(A0); |
1754 | 2c0262af | bellard | #endif
|
1755 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1756 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1757 | 2c0262af | bellard | } |
1758 | 2c0262af | bellard | |
1759 | 2c0262af | bellard | void OPPROTO op_fldt_ST0_A0(void) |
1760 | 2c0262af | bellard | { |
1761 | 2c0262af | bellard | helper_fldt_ST0_A0(); |
1762 | 2c0262af | bellard | } |
1763 | 2c0262af | bellard | |
1764 | 2c0262af | bellard | /* helpers are needed to avoid static constant reference. XXX: find a better way */
|
1765 | 2c0262af | bellard | #ifdef USE_INT_TO_FLOAT_HELPERS
|
1766 | 2c0262af | bellard | |
1767 | 2c0262af | bellard | void helper_fild_ST0_A0(void) |
1768 | 2c0262af | bellard | { |
1769 | 2c0262af | bellard | int new_fpstt;
|
1770 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1771 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)ldsw(A0); |
1772 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1773 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1774 | 2c0262af | bellard | } |
1775 | 2c0262af | bellard | |
1776 | 2c0262af | bellard | void helper_fildl_ST0_A0(void) |
1777 | 2c0262af | bellard | { |
1778 | 2c0262af | bellard | int new_fpstt;
|
1779 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1780 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)((int32_t)ldl(A0)); |
1781 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1782 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1783 | 2c0262af | bellard | } |
1784 | 2c0262af | bellard | |
1785 | 2c0262af | bellard | void helper_fildll_ST0_A0(void) |
1786 | 2c0262af | bellard | { |
1787 | 2c0262af | bellard | int new_fpstt;
|
1788 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1789 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)((int64_t)ldq(A0)); |
1790 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1791 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1792 | 2c0262af | bellard | } |
1793 | 2c0262af | bellard | |
1794 | 2c0262af | bellard | void OPPROTO op_fild_ST0_A0(void) |
1795 | 2c0262af | bellard | { |
1796 | 2c0262af | bellard | helper_fild_ST0_A0(); |
1797 | 2c0262af | bellard | } |
1798 | 2c0262af | bellard | |
1799 | 2c0262af | bellard | void OPPROTO op_fildl_ST0_A0(void) |
1800 | 2c0262af | bellard | { |
1801 | 2c0262af | bellard | helper_fildl_ST0_A0(); |
1802 | 2c0262af | bellard | } |
1803 | 2c0262af | bellard | |
1804 | 2c0262af | bellard | void OPPROTO op_fildll_ST0_A0(void) |
1805 | 2c0262af | bellard | { |
1806 | 2c0262af | bellard | helper_fildll_ST0_A0(); |
1807 | 2c0262af | bellard | } |
1808 | 2c0262af | bellard | |
1809 | 2c0262af | bellard | #else
|
1810 | 2c0262af | bellard | |
1811 | 2c0262af | bellard | void OPPROTO op_fild_ST0_A0(void) |
1812 | 2c0262af | bellard | { |
1813 | 2c0262af | bellard | int new_fpstt;
|
1814 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1815 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1816 | 14ce26e7 | bellard | FP_CONVERT.i32 = ldsw(A0); |
1817 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)FP_CONVERT.i32; |
1818 | 2c0262af | bellard | #else
|
1819 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)ldsw(A0); |
1820 | 2c0262af | bellard | #endif
|
1821 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1822 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1823 | 2c0262af | bellard | } |
1824 | 2c0262af | bellard | |
1825 | 2c0262af | bellard | void OPPROTO op_fildl_ST0_A0(void) |
1826 | 2c0262af | bellard | { |
1827 | 2c0262af | bellard | int new_fpstt;
|
1828 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1829 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1830 | 14ce26e7 | bellard | FP_CONVERT.i32 = (int32_t) ldl(A0); |
1831 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)FP_CONVERT.i32; |
1832 | 2c0262af | bellard | #else
|
1833 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)((int32_t)ldl(A0)); |
1834 | 2c0262af | bellard | #endif
|
1835 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1836 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1837 | 2c0262af | bellard | } |
1838 | 2c0262af | bellard | |
1839 | 2c0262af | bellard | void OPPROTO op_fildll_ST0_A0(void) |
1840 | 2c0262af | bellard | { |
1841 | 2c0262af | bellard | int new_fpstt;
|
1842 | 2c0262af | bellard | new_fpstt = (env->fpstt - 1) & 7; |
1843 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1844 | 14ce26e7 | bellard | FP_CONVERT.i64 = (int64_t) ldq(A0); |
1845 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)FP_CONVERT.i64; |
1846 | 2c0262af | bellard | #else
|
1847 | 664e0f19 | bellard | env->fpregs[new_fpstt].d = (CPU86_LDouble)((int64_t)ldq(A0)); |
1848 | 2c0262af | bellard | #endif
|
1849 | 2c0262af | bellard | env->fpstt = new_fpstt; |
1850 | 2c0262af | bellard | env->fptags[new_fpstt] = 0; /* validate stack entry */ |
1851 | 2c0262af | bellard | } |
1852 | 2c0262af | bellard | |
1853 | 2c0262af | bellard | #endif
|
1854 | 2c0262af | bellard | |
1855 | 2c0262af | bellard | /* fp store */
|
1856 | 2c0262af | bellard | |
1857 | 2c0262af | bellard | void OPPROTO op_fsts_ST0_A0(void) |
1858 | 2c0262af | bellard | { |
1859 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
|
1860 | 2c0262af | bellard | FP_CONVERT.f = (float)ST0;
|
1861 | 14ce26e7 | bellard | stfl(A0, FP_CONVERT.f); |
1862 | 2c0262af | bellard | #else
|
1863 | 14ce26e7 | bellard | stfl(A0, (float)ST0);
|
1864 | 2c0262af | bellard | #endif
|
1865 | 6eea2b1b | bellard | FORCE_RET(); |
1866 | 2c0262af | bellard | } |
1867 | 2c0262af | bellard | |
1868 | 2c0262af | bellard | void OPPROTO op_fstl_ST0_A0(void) |
1869 | 2c0262af | bellard | { |
1870 | 14ce26e7 | bellard | stfq(A0, (double)ST0);
|
1871 | 6eea2b1b | bellard | FORCE_RET(); |
1872 | 2c0262af | bellard | } |
1873 | 2c0262af | bellard | |
1874 | 2c0262af | bellard | void OPPROTO op_fstt_ST0_A0(void) |
1875 | 2c0262af | bellard | { |
1876 | 2c0262af | bellard | helper_fstt_ST0_A0(); |
1877 | 2c0262af | bellard | } |
1878 | 2c0262af | bellard | |
1879 | 2c0262af | bellard | void OPPROTO op_fist_ST0_A0(void) |
1880 | 2c0262af | bellard | { |
1881 | 2c0262af | bellard | #if defined(__sparc__) && !defined(__sparc_v9__)
|
1882 | 2c0262af | bellard | register CPU86_LDouble d asm("o0"); |
1883 | 2c0262af | bellard | #else
|
1884 | 2c0262af | bellard | CPU86_LDouble d; |
1885 | 2c0262af | bellard | #endif
|
1886 | 2c0262af | bellard | int val;
|
1887 | 2c0262af | bellard | |
1888 | 2c0262af | bellard | d = ST0; |
1889 | 7a0e1f41 | bellard | val = floatx_to_int32(d, &env->fp_status); |
1890 | 2c0262af | bellard | if (val != (int16_t)val)
|
1891 | 2c0262af | bellard | val = -32768;
|
1892 | 14ce26e7 | bellard | stw(A0, val); |
1893 | 6eea2b1b | bellard | FORCE_RET(); |
1894 | 2c0262af | bellard | } |
1895 | 2c0262af | bellard | |
1896 | 2c0262af | bellard | void OPPROTO op_fistl_ST0_A0(void) |
1897 | 2c0262af | bellard | { |
1898 | 2c0262af | bellard | #if defined(__sparc__) && !defined(__sparc_v9__)
|
1899 | 2c0262af | bellard | register CPU86_LDouble d asm("o0"); |
1900 | 2c0262af | bellard | #else
|
1901 | 2c0262af | bellard | CPU86_LDouble d; |
1902 | 2c0262af | bellard | #endif
|
1903 | 2c0262af | bellard | int val;
|
1904 | 2c0262af | bellard | |
1905 | 2c0262af | bellard | d = ST0; |
1906 | 7a0e1f41 | bellard | val = floatx_to_int32(d, &env->fp_status); |
1907 | 14ce26e7 | bellard | stl(A0, val); |
1908 | 6eea2b1b | bellard | FORCE_RET(); |
1909 | 2c0262af | bellard | } |
1910 | 2c0262af | bellard | |
1911 | 2c0262af | bellard | void OPPROTO op_fistll_ST0_A0(void) |
1912 | 2c0262af | bellard | { |
1913 | 2c0262af | bellard | #if defined(__sparc__) && !defined(__sparc_v9__)
|
1914 | 2c0262af | bellard | register CPU86_LDouble d asm("o0"); |
1915 | 2c0262af | bellard | #else
|
1916 | 2c0262af | bellard | CPU86_LDouble d; |
1917 | 2c0262af | bellard | #endif
|
1918 | 2c0262af | bellard | int64_t val; |
1919 | 2c0262af | bellard | |
1920 | 2c0262af | bellard | d = ST0; |
1921 | 7a0e1f41 | bellard | val = floatx_to_int64(d, &env->fp_status); |
1922 | 14ce26e7 | bellard | stq(A0, val); |
1923 | 6eea2b1b | bellard | FORCE_RET(); |
1924 | 2c0262af | bellard | } |
1925 | 2c0262af | bellard | |
1926 | 465e9838 | bellard | void OPPROTO op_fistt_ST0_A0(void) |
1927 | 465e9838 | bellard | { |
1928 | 465e9838 | bellard | #if defined(__sparc__) && !defined(__sparc_v9__)
|
1929 | 465e9838 | bellard | register CPU86_LDouble d asm("o0"); |
1930 | 465e9838 | bellard | #else
|
1931 | 465e9838 | bellard | CPU86_LDouble d; |
1932 | 465e9838 | bellard | #endif
|
1933 | 465e9838 | bellard | int val;
|
1934 | 465e9838 | bellard | |
1935 | 465e9838 | bellard | d = ST0; |
1936 | 465e9838 | bellard | val = floatx_to_int32_round_to_zero(d, &env->fp_status); |
1937 | 465e9838 | bellard | if (val != (int16_t)val)
|
1938 | 465e9838 | bellard | val = -32768;
|
1939 | 465e9838 | bellard | stw(A0, val); |
1940 | 465e9838 | bellard | FORCE_RET(); |
1941 | 465e9838 | bellard | } |
1942 | 465e9838 | bellard | |
1943 | 465e9838 | bellard | void OPPROTO op_fisttl_ST0_A0(void) |
1944 | 465e9838 | bellard | { |
1945 | 465e9838 | bellard | #if defined(__sparc__) && !defined(__sparc_v9__)
|
1946 | 465e9838 | bellard | register CPU86_LDouble d asm("o0"); |
1947 | 465e9838 | bellard | #else
|
1948 | 465e9838 | bellard | CPU86_LDouble d; |
1949 | 465e9838 | bellard | #endif
|
1950 | 465e9838 | bellard | int val;
|
1951 | 465e9838 | bellard | |
1952 | 465e9838 | bellard | d = ST0; |
1953 | 465e9838 | bellard | val = floatx_to_int32_round_to_zero(d, &env->fp_status); |
1954 | 465e9838 | bellard | stl(A0, val); |
1955 | 465e9838 | bellard | FORCE_RET(); |
1956 | 465e9838 | bellard | } |
1957 | 465e9838 | bellard | |
1958 | 465e9838 | bellard | void OPPROTO op_fisttll_ST0_A0(void) |
1959 | 465e9838 | bellard | { |
1960 | 465e9838 | bellard | #if defined(__sparc__) && !defined(__sparc_v9__)
|
1961 | 465e9838 | bellard | register CPU86_LDouble d asm("o0"); |
1962 | 465e9838 | bellard | #else
|
1963 | 465e9838 | bellard | CPU86_LDouble d; |
1964 | 465e9838 | bellard | #endif
|
1965 | 465e9838 | bellard | int64_t val; |
1966 | 465e9838 | bellard | |
1967 | 465e9838 | bellard | d = ST0; |
1968 | 465e9838 | bellard | val = floatx_to_int64_round_to_zero(d, &env->fp_status); |
1969 | 465e9838 | bellard | stq(A0, val); |
1970 | 465e9838 | bellard | FORCE_RET(); |
1971 | 465e9838 | bellard | } |
1972 | 465e9838 | bellard | |
1973 | 2c0262af | bellard | void OPPROTO op_fbld_ST0_A0(void) |
1974 | 2c0262af | bellard | { |
1975 | 2c0262af | bellard | helper_fbld_ST0_A0(); |
1976 | 2c0262af | bellard | } |
1977 | 2c0262af | bellard | |
1978 | 2c0262af | bellard | void OPPROTO op_fbst_ST0_A0(void) |
1979 | 2c0262af | bellard | { |
1980 | 2c0262af | bellard | helper_fbst_ST0_A0(); |
1981 | 2c0262af | bellard | } |
1982 | 2c0262af | bellard | |
1983 | 2c0262af | bellard | /* FPU move */
|
1984 | 2c0262af | bellard | |
1985 | 2c0262af | bellard | void OPPROTO op_fpush(void) |
1986 | 2c0262af | bellard | { |
1987 | 2c0262af | bellard | fpush(); |
1988 | 2c0262af | bellard | } |
1989 | 2c0262af | bellard | |
1990 | 2c0262af | bellard | void OPPROTO op_fpop(void) |
1991 | 2c0262af | bellard | { |
1992 | 2c0262af | bellard | fpop(); |
1993 | 2c0262af | bellard | } |
1994 | 2c0262af | bellard | |
1995 | 2c0262af | bellard | void OPPROTO op_fdecstp(void) |
1996 | 2c0262af | bellard | { |
1997 | 2c0262af | bellard | env->fpstt = (env->fpstt - 1) & 7; |
1998 | 2c0262af | bellard | env->fpus &= (~0x4700);
|
1999 | 2c0262af | bellard | } |
2000 | 2c0262af | bellard | |
2001 | 2c0262af | bellard | void OPPROTO op_fincstp(void) |
2002 | 2c0262af | bellard | { |
2003 | 2c0262af | bellard | env->fpstt = (env->fpstt + 1) & 7; |
2004 | 2c0262af | bellard | env->fpus &= (~0x4700);
|
2005 | 2c0262af | bellard | } |
2006 | 2c0262af | bellard | |
2007 | 5fef40fb | bellard | void OPPROTO op_ffree_STN(void) |
2008 | 5fef40fb | bellard | { |
2009 | 5fef40fb | bellard | env->fptags[(env->fpstt + PARAM1) & 7] = 1; |
2010 | 5fef40fb | bellard | } |
2011 | 5fef40fb | bellard | |
2012 | 2c0262af | bellard | void OPPROTO op_fmov_ST0_FT0(void) |
2013 | 2c0262af | bellard | { |
2014 | 2c0262af | bellard | ST0 = FT0; |
2015 | 2c0262af | bellard | } |
2016 | 2c0262af | bellard | |
2017 | 2c0262af | bellard | void OPPROTO op_fmov_FT0_STN(void) |
2018 | 2c0262af | bellard | { |
2019 | 2c0262af | bellard | FT0 = ST(PARAM1); |
2020 | 2c0262af | bellard | } |
2021 | 2c0262af | bellard | |
2022 | 2c0262af | bellard | void OPPROTO op_fmov_ST0_STN(void) |
2023 | 2c0262af | bellard | { |
2024 | 2c0262af | bellard | ST0 = ST(PARAM1); |
2025 | 2c0262af | bellard | } |
2026 | 2c0262af | bellard | |
2027 | 2c0262af | bellard | void OPPROTO op_fmov_STN_ST0(void) |
2028 | 2c0262af | bellard | { |
2029 | 2c0262af | bellard | ST(PARAM1) = ST0; |
2030 | 2c0262af | bellard | } |
2031 | 2c0262af | bellard | |
2032 | 2c0262af | bellard | void OPPROTO op_fxchg_ST0_STN(void) |
2033 | 2c0262af | bellard | { |
2034 | 2c0262af | bellard | CPU86_LDouble tmp; |
2035 | 2c0262af | bellard | tmp = ST(PARAM1); |
2036 | 2c0262af | bellard | ST(PARAM1) = ST0; |
2037 | 2c0262af | bellard | ST0 = tmp; |
2038 | 2c0262af | bellard | } |
2039 | 2c0262af | bellard | |
2040 | 2c0262af | bellard | /* FPU operations */
|
2041 | 2c0262af | bellard | |
2042 | 43fb823b | bellard | const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500}; |
2043 | 43fb823b | bellard | |
2044 | 2c0262af | bellard | void OPPROTO op_fcom_ST0_FT0(void) |
2045 | 2c0262af | bellard | { |
2046 | 43fb823b | bellard | int ret;
|
2047 | 43fb823b | bellard | |
2048 | 43fb823b | bellard | ret = floatx_compare(ST0, FT0, &env->fp_status); |
2049 | 43fb823b | bellard | env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1]; |
2050 | 2c0262af | bellard | FORCE_RET(); |
2051 | 2c0262af | bellard | } |
2052 | 2c0262af | bellard | |
2053 | 2c0262af | bellard | void OPPROTO op_fucom_ST0_FT0(void) |
2054 | 2c0262af | bellard | { |
2055 | 43fb823b | bellard | int ret;
|
2056 | 43fb823b | bellard | |
2057 | 43fb823b | bellard | ret = floatx_compare_quiet(ST0, FT0, &env->fp_status); |
2058 | 43fb823b | bellard | env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret+ 1]; |
2059 | 2c0262af | bellard | FORCE_RET(); |
2060 | 2c0262af | bellard | } |
2061 | 2c0262af | bellard | |
2062 | 43fb823b | bellard | const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C}; |
2063 | 43fb823b | bellard | |
2064 | 2c0262af | bellard | void OPPROTO op_fcomi_ST0_FT0(void) |
2065 | 2c0262af | bellard | { |
2066 | 43fb823b | bellard | int eflags;
|
2067 | 43fb823b | bellard | int ret;
|
2068 | 43fb823b | bellard | |
2069 | 43fb823b | bellard | ret = floatx_compare(ST0, FT0, &env->fp_status); |
2070 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
2071 | 43fb823b | bellard | eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
|
2072 | 2c0262af | bellard | CC_SRC = eflags; |
2073 | 2c0262af | bellard | FORCE_RET(); |
2074 | 2c0262af | bellard | } |
2075 | 2c0262af | bellard | |
2076 | 2c0262af | bellard | void OPPROTO op_fucomi_ST0_FT0(void) |
2077 | 2c0262af | bellard | { |
2078 | 43fb823b | bellard | int eflags;
|
2079 | 43fb823b | bellard | int ret;
|
2080 | 43fb823b | bellard | |
2081 | 43fb823b | bellard | ret = floatx_compare_quiet(ST0, FT0, &env->fp_status); |
2082 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
2083 | 43fb823b | bellard | eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
|
2084 | 2c0262af | bellard | CC_SRC = eflags; |
2085 | 2c0262af | bellard | FORCE_RET(); |
2086 | 2c0262af | bellard | } |
2087 | 2c0262af | bellard | |
2088 | 80043406 | bellard | void OPPROTO op_fcmov_ST0_STN_T0(void) |
2089 | 80043406 | bellard | { |
2090 | 80043406 | bellard | if (T0) {
|
2091 | 80043406 | bellard | ST0 = ST(PARAM1); |
2092 | 80043406 | bellard | } |
2093 | 80043406 | bellard | FORCE_RET(); |
2094 | 80043406 | bellard | } |
2095 | 80043406 | bellard | |
2096 | 2c0262af | bellard | void OPPROTO op_fadd_ST0_FT0(void) |
2097 | 2c0262af | bellard | { |
2098 | 2c0262af | bellard | ST0 += FT0; |
2099 | 2c0262af | bellard | } |
2100 | 2c0262af | bellard | |
2101 | 2c0262af | bellard | void OPPROTO op_fmul_ST0_FT0(void) |
2102 | 2c0262af | bellard | { |
2103 | 2c0262af | bellard | ST0 *= FT0; |
2104 | 2c0262af | bellard | } |
2105 | 2c0262af | bellard | |
2106 | 2c0262af | bellard | void OPPROTO op_fsub_ST0_FT0(void) |
2107 | 2c0262af | bellard | { |
2108 | 2c0262af | bellard | ST0 -= FT0; |
2109 | 2c0262af | bellard | } |
2110 | 2c0262af | bellard | |
2111 | 2c0262af | bellard | void OPPROTO op_fsubr_ST0_FT0(void) |
2112 | 2c0262af | bellard | { |
2113 | 2c0262af | bellard | ST0 = FT0 - ST0; |
2114 | 2c0262af | bellard | } |
2115 | 2c0262af | bellard | |
2116 | 2c0262af | bellard | void OPPROTO op_fdiv_ST0_FT0(void) |
2117 | 2c0262af | bellard | { |
2118 | 2ee73ac3 | bellard | ST0 = helper_fdiv(ST0, FT0); |
2119 | 2c0262af | bellard | } |
2120 | 2c0262af | bellard | |
2121 | 2c0262af | bellard | void OPPROTO op_fdivr_ST0_FT0(void) |
2122 | 2c0262af | bellard | { |
2123 | 2ee73ac3 | bellard | ST0 = helper_fdiv(FT0, ST0); |
2124 | 2c0262af | bellard | } |
2125 | 2c0262af | bellard | |
2126 | 2c0262af | bellard | /* fp operations between STN and ST0 */
|
2127 | 2c0262af | bellard | |
2128 | 2c0262af | bellard | void OPPROTO op_fadd_STN_ST0(void) |
2129 | 2c0262af | bellard | { |
2130 | 2c0262af | bellard | ST(PARAM1) += ST0; |
2131 | 2c0262af | bellard | } |
2132 | 2c0262af | bellard | |
2133 | 2c0262af | bellard | void OPPROTO op_fmul_STN_ST0(void) |
2134 | 2c0262af | bellard | { |
2135 | 2c0262af | bellard | ST(PARAM1) *= ST0; |
2136 | 2c0262af | bellard | } |
2137 | 2c0262af | bellard | |
2138 | 2c0262af | bellard | void OPPROTO op_fsub_STN_ST0(void) |
2139 | 2c0262af | bellard | { |
2140 | 2c0262af | bellard | ST(PARAM1) -= ST0; |
2141 | 2c0262af | bellard | } |
2142 | 2c0262af | bellard | |
2143 | 2c0262af | bellard | void OPPROTO op_fsubr_STN_ST0(void) |
2144 | 2c0262af | bellard | { |
2145 | 2c0262af | bellard | CPU86_LDouble *p; |
2146 | 2c0262af | bellard | p = &ST(PARAM1); |
2147 | 2c0262af | bellard | *p = ST0 - *p; |
2148 | 2c0262af | bellard | } |
2149 | 2c0262af | bellard | |
2150 | 2c0262af | bellard | void OPPROTO op_fdiv_STN_ST0(void) |
2151 | 2c0262af | bellard | { |
2152 | 2ee73ac3 | bellard | CPU86_LDouble *p; |
2153 | 2ee73ac3 | bellard | p = &ST(PARAM1); |
2154 | 2ee73ac3 | bellard | *p = helper_fdiv(*p, ST0); |
2155 | 2c0262af | bellard | } |
2156 | 2c0262af | bellard | |
2157 | 2c0262af | bellard | void OPPROTO op_fdivr_STN_ST0(void) |
2158 | 2c0262af | bellard | { |
2159 | 2c0262af | bellard | CPU86_LDouble *p; |
2160 | 2c0262af | bellard | p = &ST(PARAM1); |
2161 | 2ee73ac3 | bellard | *p = helper_fdiv(ST0, *p); |
2162 | 2c0262af | bellard | } |
2163 | 2c0262af | bellard | |
2164 | 2c0262af | bellard | /* misc FPU operations */
|
2165 | 2c0262af | bellard | void OPPROTO op_fchs_ST0(void) |
2166 | 2c0262af | bellard | { |
2167 | 7a0e1f41 | bellard | ST0 = floatx_chs(ST0); |
2168 | 2c0262af | bellard | } |
2169 | 2c0262af | bellard | |
2170 | 2c0262af | bellard | void OPPROTO op_fabs_ST0(void) |
2171 | 2c0262af | bellard | { |
2172 | 7a0e1f41 | bellard | ST0 = floatx_abs(ST0); |
2173 | 2c0262af | bellard | } |
2174 | 2c0262af | bellard | |
2175 | 2c0262af | bellard | void OPPROTO op_fxam_ST0(void) |
2176 | 2c0262af | bellard | { |
2177 | 2c0262af | bellard | helper_fxam_ST0(); |
2178 | 2c0262af | bellard | } |
2179 | 2c0262af | bellard | |
2180 | 2c0262af | bellard | void OPPROTO op_fld1_ST0(void) |
2181 | 2c0262af | bellard | { |
2182 | 2c0262af | bellard | ST0 = f15rk[1];
|
2183 | 2c0262af | bellard | } |
2184 | 2c0262af | bellard | |
2185 | 2c0262af | bellard | void OPPROTO op_fldl2t_ST0(void) |
2186 | 2c0262af | bellard | { |
2187 | 2c0262af | bellard | ST0 = f15rk[6];
|
2188 | 2c0262af | bellard | } |
2189 | 2c0262af | bellard | |
2190 | 2c0262af | bellard | void OPPROTO op_fldl2e_ST0(void) |
2191 | 2c0262af | bellard | { |
2192 | 2c0262af | bellard | ST0 = f15rk[5];
|
2193 | 2c0262af | bellard | } |
2194 | 2c0262af | bellard | |
2195 | 2c0262af | bellard | void OPPROTO op_fldpi_ST0(void) |
2196 | 2c0262af | bellard | { |
2197 | 2c0262af | bellard | ST0 = f15rk[2];
|
2198 | 2c0262af | bellard | } |
2199 | 2c0262af | bellard | |
2200 | 2c0262af | bellard | void OPPROTO op_fldlg2_ST0(void) |
2201 | 2c0262af | bellard | { |
2202 | 2c0262af | bellard | ST0 = f15rk[3];
|
2203 | 2c0262af | bellard | } |
2204 | 2c0262af | bellard | |
2205 | 2c0262af | bellard | void OPPROTO op_fldln2_ST0(void) |
2206 | 2c0262af | bellard | { |
2207 | 2c0262af | bellard | ST0 = f15rk[4];
|
2208 | 2c0262af | bellard | } |
2209 | 2c0262af | bellard | |
2210 | 2c0262af | bellard | void OPPROTO op_fldz_ST0(void) |
2211 | 2c0262af | bellard | { |
2212 | 2c0262af | bellard | ST0 = f15rk[0];
|
2213 | 2c0262af | bellard | } |
2214 | 2c0262af | bellard | |
2215 | 2c0262af | bellard | void OPPROTO op_fldz_FT0(void) |
2216 | 2c0262af | bellard | { |
2217 | 6a8c397d | bellard | FT0 = f15rk[0];
|
2218 | 2c0262af | bellard | } |
2219 | 2c0262af | bellard | |
2220 | 2c0262af | bellard | /* associated heplers to reduce generated code length and to simplify
|
2221 | 2c0262af | bellard | relocation (FP constants are usually stored in .rodata section) */
|
2222 | 2c0262af | bellard | |
2223 | 2c0262af | bellard | void OPPROTO op_f2xm1(void) |
2224 | 2c0262af | bellard | { |
2225 | 2c0262af | bellard | helper_f2xm1(); |
2226 | 2c0262af | bellard | } |
2227 | 2c0262af | bellard | |
2228 | 2c0262af | bellard | void OPPROTO op_fyl2x(void) |
2229 | 2c0262af | bellard | { |
2230 | 2c0262af | bellard | helper_fyl2x(); |
2231 | 2c0262af | bellard | } |
2232 | 2c0262af | bellard | |
2233 | 2c0262af | bellard | void OPPROTO op_fptan(void) |
2234 | 2c0262af | bellard | { |
2235 | 2c0262af | bellard | helper_fptan(); |
2236 | 2c0262af | bellard | } |
2237 | 2c0262af | bellard | |
2238 | 2c0262af | bellard | void OPPROTO op_fpatan(void) |
2239 | 2c0262af | bellard | { |
2240 | 2c0262af | bellard | helper_fpatan(); |
2241 | 2c0262af | bellard | } |
2242 | 2c0262af | bellard | |
2243 | 2c0262af | bellard | void OPPROTO op_fxtract(void) |
2244 | 2c0262af | bellard | { |
2245 | 2c0262af | bellard | helper_fxtract(); |
2246 | 2c0262af | bellard | } |
2247 | 2c0262af | bellard | |
2248 | 2c0262af | bellard | void OPPROTO op_fprem1(void) |
2249 | 2c0262af | bellard | { |
2250 | 2c0262af | bellard | helper_fprem1(); |
2251 | 2c0262af | bellard | } |
2252 | 2c0262af | bellard | |
2253 | 2c0262af | bellard | |
2254 | 2c0262af | bellard | void OPPROTO op_fprem(void) |
2255 | 2c0262af | bellard | { |
2256 | 2c0262af | bellard | helper_fprem(); |
2257 | 2c0262af | bellard | } |
2258 | 2c0262af | bellard | |
2259 | 2c0262af | bellard | void OPPROTO op_fyl2xp1(void) |
2260 | 2c0262af | bellard | { |
2261 | 2c0262af | bellard | helper_fyl2xp1(); |
2262 | 2c0262af | bellard | } |
2263 | 2c0262af | bellard | |
2264 | 2c0262af | bellard | void OPPROTO op_fsqrt(void) |
2265 | 2c0262af | bellard | { |
2266 | 2c0262af | bellard | helper_fsqrt(); |
2267 | 2c0262af | bellard | } |
2268 | 2c0262af | bellard | |
2269 | 2c0262af | bellard | void OPPROTO op_fsincos(void) |
2270 | 2c0262af | bellard | { |
2271 | 2c0262af | bellard | helper_fsincos(); |
2272 | 2c0262af | bellard | } |
2273 | 2c0262af | bellard | |
2274 | 2c0262af | bellard | void OPPROTO op_frndint(void) |
2275 | 2c0262af | bellard | { |
2276 | 2c0262af | bellard | helper_frndint(); |
2277 | 2c0262af | bellard | } |
2278 | 2c0262af | bellard | |
2279 | 2c0262af | bellard | void OPPROTO op_fscale(void) |
2280 | 2c0262af | bellard | { |
2281 | 2c0262af | bellard | helper_fscale(); |
2282 | 2c0262af | bellard | } |
2283 | 2c0262af | bellard | |
2284 | 2c0262af | bellard | void OPPROTO op_fsin(void) |
2285 | 2c0262af | bellard | { |
2286 | 2c0262af | bellard | helper_fsin(); |
2287 | 2c0262af | bellard | } |
2288 | 2c0262af | bellard | |
2289 | 2c0262af | bellard | void OPPROTO op_fcos(void) |
2290 | 2c0262af | bellard | { |
2291 | 2c0262af | bellard | helper_fcos(); |
2292 | 2c0262af | bellard | } |
2293 | 2c0262af | bellard | |
2294 | 2c0262af | bellard | void OPPROTO op_fnstsw_A0(void) |
2295 | 2c0262af | bellard | { |
2296 | 2c0262af | bellard | int fpus;
|
2297 | 2c0262af | bellard | fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
2298 | 14ce26e7 | bellard | stw(A0, fpus); |
2299 | 6eea2b1b | bellard | FORCE_RET(); |
2300 | 2c0262af | bellard | } |
2301 | 2c0262af | bellard | |
2302 | 2c0262af | bellard | void OPPROTO op_fnstsw_EAX(void) |
2303 | 2c0262af | bellard | { |
2304 | 2c0262af | bellard | int fpus;
|
2305 | 2c0262af | bellard | fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
2306 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | fpus;
|
2307 | 2c0262af | bellard | } |
2308 | 2c0262af | bellard | |
2309 | 2c0262af | bellard | void OPPROTO op_fnstcw_A0(void) |
2310 | 2c0262af | bellard | { |
2311 | 14ce26e7 | bellard | stw(A0, env->fpuc); |
2312 | 6eea2b1b | bellard | FORCE_RET(); |
2313 | 2c0262af | bellard | } |
2314 | 2c0262af | bellard | |
2315 | 2c0262af | bellard | void OPPROTO op_fldcw_A0(void) |
2316 | 2c0262af | bellard | { |
2317 | 14ce26e7 | bellard | env->fpuc = lduw(A0); |
2318 | 7a0e1f41 | bellard | update_fp_status(); |
2319 | 2c0262af | bellard | } |
2320 | 2c0262af | bellard | |
2321 | 2c0262af | bellard | void OPPROTO op_fclex(void) |
2322 | 2c0262af | bellard | { |
2323 | 2c0262af | bellard | env->fpus &= 0x7f00;
|
2324 | 2c0262af | bellard | } |
2325 | 2c0262af | bellard | |
2326 | 2ee73ac3 | bellard | void OPPROTO op_fwait(void) |
2327 | 2ee73ac3 | bellard | { |
2328 | 2ee73ac3 | bellard | if (env->fpus & FPUS_SE)
|
2329 | 2ee73ac3 | bellard | fpu_raise_exception(); |
2330 | 2ee73ac3 | bellard | FORCE_RET(); |
2331 | 2ee73ac3 | bellard | } |
2332 | 2ee73ac3 | bellard | |
2333 | 2c0262af | bellard | void OPPROTO op_fninit(void) |
2334 | 2c0262af | bellard | { |
2335 | 2c0262af | bellard | env->fpus = 0;
|
2336 | 2c0262af | bellard | env->fpstt = 0;
|
2337 | 2c0262af | bellard | env->fpuc = 0x37f;
|
2338 | 2c0262af | bellard | env->fptags[0] = 1; |
2339 | 2c0262af | bellard | env->fptags[1] = 1; |
2340 | 2c0262af | bellard | env->fptags[2] = 1; |
2341 | 2c0262af | bellard | env->fptags[3] = 1; |
2342 | 2c0262af | bellard | env->fptags[4] = 1; |
2343 | 2c0262af | bellard | env->fptags[5] = 1; |
2344 | 2c0262af | bellard | env->fptags[6] = 1; |
2345 | 2c0262af | bellard | env->fptags[7] = 1; |
2346 | 2c0262af | bellard | } |
2347 | 2c0262af | bellard | |
2348 | 2c0262af | bellard | void OPPROTO op_fnstenv_A0(void) |
2349 | 2c0262af | bellard | { |
2350 | 14ce26e7 | bellard | helper_fstenv(A0, PARAM1); |
2351 | 2c0262af | bellard | } |
2352 | 2c0262af | bellard | |
2353 | 2c0262af | bellard | void OPPROTO op_fldenv_A0(void) |
2354 | 2c0262af | bellard | { |
2355 | 14ce26e7 | bellard | helper_fldenv(A0, PARAM1); |
2356 | 2c0262af | bellard | } |
2357 | 2c0262af | bellard | |
2358 | 2c0262af | bellard | void OPPROTO op_fnsave_A0(void) |
2359 | 2c0262af | bellard | { |
2360 | 14ce26e7 | bellard | helper_fsave(A0, PARAM1); |
2361 | 2c0262af | bellard | } |
2362 | 2c0262af | bellard | |
2363 | 2c0262af | bellard | void OPPROTO op_frstor_A0(void) |
2364 | 2c0262af | bellard | { |
2365 | 14ce26e7 | bellard | helper_frstor(A0, PARAM1); |
2366 | 2c0262af | bellard | } |
2367 | 2c0262af | bellard | |
2368 | 2c0262af | bellard | /* threading support */
|
2369 | 2c0262af | bellard | void OPPROTO op_lock(void) |
2370 | 2c0262af | bellard | { |
2371 | 2c0262af | bellard | cpu_lock(); |
2372 | 2c0262af | bellard | } |
2373 | 2c0262af | bellard | |
2374 | 2c0262af | bellard | void OPPROTO op_unlock(void) |
2375 | 2c0262af | bellard | { |
2376 | 2c0262af | bellard | cpu_unlock(); |
2377 | 2c0262af | bellard | } |
2378 | 2c0262af | bellard | |
2379 | 14ce26e7 | bellard | /* SSE support */
|
2380 | 14ce26e7 | bellard | static inline void memcpy16(void *d, void *s) |
2381 | 14ce26e7 | bellard | { |
2382 | 14ce26e7 | bellard | ((uint32_t *)d)[0] = ((uint32_t *)s)[0]; |
2383 | 14ce26e7 | bellard | ((uint32_t *)d)[1] = ((uint32_t *)s)[1]; |
2384 | 14ce26e7 | bellard | ((uint32_t *)d)[2] = ((uint32_t *)s)[2]; |
2385 | 14ce26e7 | bellard | ((uint32_t *)d)[3] = ((uint32_t *)s)[3]; |
2386 | 14ce26e7 | bellard | } |
2387 | 14ce26e7 | bellard | |
2388 | 14ce26e7 | bellard | void OPPROTO op_movo(void) |
2389 | 14ce26e7 | bellard | { |
2390 | 14ce26e7 | bellard | /* XXX: badly generated code */
|
2391 | 14ce26e7 | bellard | XMMReg *d, *s; |
2392 | 14ce26e7 | bellard | d = (XMMReg *)((char *)env + PARAM1);
|
2393 | 14ce26e7 | bellard | s = (XMMReg *)((char *)env + PARAM2);
|
2394 | 14ce26e7 | bellard | memcpy16(d, s); |
2395 | 14ce26e7 | bellard | } |
2396 | 14ce26e7 | bellard | |
2397 | 664e0f19 | bellard | void OPPROTO op_movq(void) |
2398 | 664e0f19 | bellard | { |
2399 | 664e0f19 | bellard | uint64_t *d, *s; |
2400 | 664e0f19 | bellard | d = (uint64_t *)((char *)env + PARAM1);
|
2401 | 664e0f19 | bellard | s = (uint64_t *)((char *)env + PARAM2);
|
2402 | 664e0f19 | bellard | *d = *s; |
2403 | 664e0f19 | bellard | } |
2404 | 664e0f19 | bellard | |
2405 | 664e0f19 | bellard | void OPPROTO op_movl(void) |
2406 | 664e0f19 | bellard | { |
2407 | 664e0f19 | bellard | uint32_t *d, *s; |
2408 | 664e0f19 | bellard | d = (uint32_t *)((char *)env + PARAM1);
|
2409 | 664e0f19 | bellard | s = (uint32_t *)((char *)env + PARAM2);
|
2410 | 664e0f19 | bellard | *d = *s; |
2411 | 664e0f19 | bellard | } |
2412 | 664e0f19 | bellard | |
2413 | 664e0f19 | bellard | void OPPROTO op_movq_env_0(void) |
2414 | 664e0f19 | bellard | { |
2415 | 664e0f19 | bellard | uint64_t *d; |
2416 | 664e0f19 | bellard | d = (uint64_t *)((char *)env + PARAM1);
|
2417 | 664e0f19 | bellard | *d = 0;
|
2418 | 664e0f19 | bellard | } |
2419 | 664e0f19 | bellard | |
2420 | 14ce26e7 | bellard | void OPPROTO op_fxsave_A0(void) |
2421 | 14ce26e7 | bellard | { |
2422 | 14ce26e7 | bellard | helper_fxsave(A0, PARAM1); |
2423 | 14ce26e7 | bellard | } |
2424 | 14ce26e7 | bellard | |
2425 | 14ce26e7 | bellard | void OPPROTO op_fxrstor_A0(void) |
2426 | 14ce26e7 | bellard | { |
2427 | 14ce26e7 | bellard | helper_fxrstor(A0, PARAM1); |
2428 | 14ce26e7 | bellard | } |
2429 | 664e0f19 | bellard | |
2430 | 664e0f19 | bellard | /* XXX: optimize by storing fptt and fptags in the static cpu state */
|
2431 | 664e0f19 | bellard | void OPPROTO op_enter_mmx(void) |
2432 | 664e0f19 | bellard | { |
2433 | 664e0f19 | bellard | env->fpstt = 0;
|
2434 | 664e0f19 | bellard | *(uint32_t *)(env->fptags) = 0;
|
2435 | 664e0f19 | bellard | *(uint32_t *)(env->fptags + 4) = 0; |
2436 | 664e0f19 | bellard | } |
2437 | 664e0f19 | bellard | |
2438 | 664e0f19 | bellard | void OPPROTO op_emms(void) |
2439 | 664e0f19 | bellard | { |
2440 | 664e0f19 | bellard | /* set to empty state */
|
2441 | 664e0f19 | bellard | *(uint32_t *)(env->fptags) = 0x01010101;
|
2442 | 664e0f19 | bellard | *(uint32_t *)(env->fptags + 4) = 0x01010101; |
2443 | 664e0f19 | bellard | } |
2444 | 664e0f19 | bellard | |
2445 | 664e0f19 | bellard | #define SHIFT 0 |
2446 | 664e0f19 | bellard | #include "ops_sse.h" |
2447 | 664e0f19 | bellard | |
2448 | 664e0f19 | bellard | #define SHIFT 1 |
2449 | 664e0f19 | bellard | #include "ops_sse.h" |