Archipelago » qemu

/*

 * QEMU USB EHCI Emulation

 *

 * Copyright(c) 2008  Emutex Ltd. (address@hidden)

 *

 * EHCI project was started by Mark Burkley, with contributions by

 * Niels de Vos.  David S. Ahern continued working on it.  Kevin Wolf,

 * Jan Kiszka and Vincent Palatin contributed bugfixes.

 *

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or(at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see <http://www.gnu.org/licenses/>.

 *

 * TODO:

 *  o Downstream port handoff

 */

#include "hw.h"

#include "qemu-timer.h"

#include "usb.h"

#include "pci.h"

#include "monitor.h"

#include "trace.h"

#define EHCI_DEBUG   0

#if EHCI_DEBUG

#define DPRINTF printf

#else

#define DPRINTF(...)

#endif

/* internal processing - reset HC to try and recover */

#define USB_RET_PROCERR   (-99)

#define MMIO_SIZE        0x1000

/* Capability Registers Base Address - section 2.2 */

#define CAPREGBASE       0x0000

#define CAPLENGTH        CAPREGBASE + 0x0000  // 1-byte, 0x0001 reserved

#define HCIVERSION       CAPREGBASE + 0x0002  // 2-bytes, i/f version #

#define HCSPARAMS        CAPREGBASE + 0x0004  // 4-bytes, structural params

#define HCCPARAMS        CAPREGBASE + 0x0008  // 4-bytes, capability params

#define EECP             HCCPARAMS + 1

#define HCSPPORTROUTE1   CAPREGBASE + 0x000c

#define HCSPPORTROUTE2   CAPREGBASE + 0x0010

#define OPREGBASE        0x0020        // Operational Registers Base Address

#define USBCMD           OPREGBASE + 0x0000

#define USBCMD_RUNSTOP   (1 << 0)      // run / Stop

#define USBCMD_HCRESET   (1 << 1)      // HC Reset

#define USBCMD_FLS       (3 << 2)      // Frame List Size

#define USBCMD_FLS_SH    2             // Frame List Size Shift

#define USBCMD_PSE       (1 << 4)      // Periodic Schedule Enable

#define USBCMD_ASE       (1 << 5)      // Asynch Schedule Enable

#define USBCMD_IAAD      (1 << 6)      // Int Asynch Advance Doorbell

#define USBCMD_LHCR      (1 << 7)      // Light Host Controller Reset

#define USBCMD_ASPMC     (3 << 8)      // Async Sched Park Mode Count

#define USBCMD_ASPME     (1 << 11)     // Async Sched Park Mode Enable

#define USBCMD_ITC       (0x7f << 16)  // Int Threshold Control

#define USBCMD_ITC_SH    16            // Int Threshold Control Shift

#define USBSTS           OPREGBASE + 0x0004

#define USBSTS_RO_MASK   0x0000003f

#define USBSTS_INT       (1 << 0)      // USB Interrupt

#define USBSTS_ERRINT    (1 << 1)      // Error Interrupt

#define USBSTS_PCD       (1 << 2)      // Port Change Detect

#define USBSTS_FLR       (1 << 3)      // Frame List Rollover

#define USBSTS_HSE       (1 << 4)      // Host System Error

#define USBSTS_IAA       (1 << 5)      // Interrupt on Async Advance

#define USBSTS_HALT      (1 << 12)     // HC Halted

#define USBSTS_REC       (1 << 13)     // Reclamation

#define USBSTS_PSS       (1 << 14)     // Periodic Schedule Status

#define USBSTS_ASS       (1 << 15)     // Asynchronous Schedule Status

/*

 *  Interrupt enable bits correspond to the interrupt active bits in USBSTS

 *  so no need to redefine here.

 */

#define USBINTR              OPREGBASE + 0x0008

#define USBINTR_MASK         0x0000003f

#define FRINDEX              OPREGBASE + 0x000c

#define CTRLDSSEGMENT        OPREGBASE + 0x0010

#define PERIODICLISTBASE     OPREGBASE + 0x0014

#define ASYNCLISTADDR        OPREGBASE + 0x0018

#define ASYNCLISTADDR_MASK   0xffffffe0

#define CONFIGFLAG           OPREGBASE + 0x0040

#define PORTSC               (OPREGBASE + 0x0044)

#define PORTSC_BEGIN         PORTSC

#define PORTSC_END           (PORTSC + 4 * NB_PORTS)

/*

 * Bits that are reserverd or are read-only are masked out of values

 * written to us by software

 */

#define PORTSC_RO_MASK       0x007021c5

#define PORTSC_RWC_MASK      0x0000002a

#define PORTSC_WKOC_E        (1 << 22)    // Wake on Over Current Enable

#define PORTSC_WKDS_E        (1 << 21)    // Wake on Disconnect Enable

#define PORTSC_WKCN_E        (1 << 20)    // Wake on Connect Enable

#define PORTSC_PTC           (15 << 16)   // Port Test Control

#define PORTSC_PTC_SH        16           // Port Test Control shift

#define PORTSC_PIC           (3 << 14)    // Port Indicator Control

#define PORTSC_PIC_SH        14           // Port Indicator Control Shift

#define PORTSC_POWNER        (1 << 13)    // Port Owner

#define PORTSC_PPOWER        (1 << 12)    // Port Power

#define PORTSC_LINESTAT      (3 << 10)    // Port Line Status

#define PORTSC_LINESTAT_SH   10           // Port Line Status Shift

#define PORTSC_PRESET        (1 << 8)     // Port Reset

#define PORTSC_SUSPEND       (1 << 7)     // Port Suspend

#define PORTSC_FPRES         (1 << 6)     // Force Port Resume

#define PORTSC_OCC           (1 << 5)     // Over Current Change

#define PORTSC_OCA           (1 << 4)     // Over Current Active

#define PORTSC_PEDC          (1 << 3)     // Port Enable/Disable Change

#define PORTSC_PED           (1 << 2)     // Port Enable/Disable

#define PORTSC_CSC           (1 << 1)     // Connect Status Change

#define PORTSC_CONNECT       (1 << 0)     // Current Connect Status

#define FRAME_TIMER_FREQ 1000

#define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)

#define NB_MAXINTRATE    8        // Max rate at which controller issues ints

#define NB_PORTS         4        // Number of downstream ports

#define BUFF_SIZE        5*4096   // Max bytes to transfer per transaction

#define MAX_ITERATIONS   20       // Max number of QH before we break the loop

#define MAX_QH           100      // Max allowable queue heads in a chain

/*  Internal periodic / asynchronous schedule state machine states

 */

typedef enum {

    EST_INACTIVE = 1000,

    EST_ACTIVE,

    EST_EXECUTING,

    EST_SLEEPING,

    /*  The following states are internal to the state machine function

    */

    EST_WAITLISTHEAD,

    EST_FETCHENTRY,

    EST_FETCHQH,

    EST_FETCHITD,

    EST_ADVANCEQUEUE,

    EST_FETCHQTD,

    EST_EXECUTE,

    EST_WRITEBACK,

    EST_HORIZONTALQH

} EHCI_STATES;

/* macros for accessing fields within next link pointer entry */

#define NLPTR_GET(x)             ((x) & 0xffffffe0)

#define NLPTR_TYPE_GET(x)        (((x) >> 1) & 3)

#define NLPTR_TBIT(x)            ((x) & 1)  // 1=invalid, 0=valid

/* link pointer types */

#define NLPTR_TYPE_ITD           0     // isoc xfer descriptor

#define NLPTR_TYPE_QH            1     // queue head

#define NLPTR_TYPE_STITD         2     // split xaction, isoc xfer descriptor

#define NLPTR_TYPE_FSTN          3     // frame span traversal node

/*  EHCI spec version 1.0 Section 3.3

 */

typedef struct EHCIitd {

    uint32_t next;

    uint32_t transact[8];

#define ITD_XACT_ACTIVE          (1 << 31)

#define ITD_XACT_DBERROR         (1 << 30)

#define ITD_XACT_BABBLE          (1 << 29)

#define ITD_XACT_XACTERR         (1 << 28)

#define ITD_XACT_LENGTH_MASK     0x0fff0000

#define ITD_XACT_LENGTH_SH       16

#define ITD_XACT_IOC             (1 << 15)

#define ITD_XACT_PGSEL_MASK      0x00007000

#define ITD_XACT_PGSEL_SH        12

#define ITD_XACT_OFFSET_MASK     0x00000fff

    uint32_t bufptr[7];

#define ITD_BUFPTR_MASK          0xfffff000

#define ITD_BUFPTR_SH            12

#define ITD_BUFPTR_EP_MASK       0x00000f00

#define ITD_BUFPTR_EP_SH         8

#define ITD_BUFPTR_DEVADDR_MASK  0x0000007f

#define ITD_BUFPTR_DEVADDR_SH    0

#define ITD_BUFPTR_DIRECTION     (1 << 11)

#define ITD_BUFPTR_MAXPKT_MASK   0x000007ff

#define ITD_BUFPTR_MAXPKT_SH     0

#define ITD_BUFPTR_MULT_MASK     0x00000003

} EHCIitd;

/*  EHCI spec version 1.0 Section 3.4

 */

typedef struct EHCIsitd {

    uint32_t next;                  // Standard next link pointer

    uint32_t epchar;

#define SITD_EPCHAR_IO              (1 << 31)

#define SITD_EPCHAR_PORTNUM_MASK    0x7f000000

#define SITD_EPCHAR_PORTNUM_SH      24

#define SITD_EPCHAR_HUBADD_MASK     0x007f0000

#define SITD_EPCHAR_HUBADDR_SH      16

#define SITD_EPCHAR_EPNUM_MASK      0x00000f00

#define SITD_EPCHAR_EPNUM_SH        8

#define SITD_EPCHAR_DEVADDR_MASK    0x0000007f

    uint32_t uframe;

#define SITD_UFRAME_CMASK_MASK      0x0000ff00

#define SITD_UFRAME_CMASK_SH        8

#define SITD_UFRAME_SMASK_MASK      0x000000ff

    uint32_t results;

#define SITD_RESULTS_IOC              (1 << 31)

#define SITD_RESULTS_PGSEL            (1 << 30)

#define SITD_RESULTS_TBYTES_MASK      0x03ff0000

#define SITD_RESULTS_TYBYTES_SH       16

#define SITD_RESULTS_CPROGMASK_MASK   0x0000ff00

#define SITD_RESULTS_CPROGMASK_SH     8

#define SITD_RESULTS_ACTIVE           (1 << 7)

#define SITD_RESULTS_ERR              (1 << 6)

#define SITD_RESULTS_DBERR            (1 << 5)

#define SITD_RESULTS_BABBLE           (1 << 4)

#define SITD_RESULTS_XACTERR          (1 << 3)

#define SITD_RESULTS_MISSEDUF         (1 << 2)

#define SITD_RESULTS_SPLITXSTATE      (1 << 1)

    uint32_t bufptr[2];

#define SITD_BUFPTR_MASK              0xfffff000

#define SITD_BUFPTR_CURROFF_MASK      0x00000fff

#define SITD_BUFPTR_TPOS_MASK         0x00000018

#define SITD_BUFPTR_TPOS_SH           3

#define SITD_BUFPTR_TCNT_MASK         0x00000007

    uint32_t backptr;                 // Standard next link pointer

} EHCIsitd;

/*  EHCI spec version 1.0 Section 3.5

 */

typedef struct EHCIqtd {

    uint32_t next;                    // Standard next link pointer

    uint32_t altnext;                 // Standard next link pointer

    uint32_t token;

#define QTD_TOKEN_DTOGGLE             (1 << 31)

#define QTD_TOKEN_TBYTES_MASK         0x7fff0000

#define QTD_TOKEN_TBYTES_SH           16

#define QTD_TOKEN_IOC                 (1 << 15)

#define QTD_TOKEN_CPAGE_MASK          0x00007000

#define QTD_TOKEN_CPAGE_SH            12

#define QTD_TOKEN_CERR_MASK           0x00000c00

#define QTD_TOKEN_CERR_SH             10

#define QTD_TOKEN_PID_MASK            0x00000300

#define QTD_TOKEN_PID_SH              8

#define QTD_TOKEN_ACTIVE              (1 << 7)

#define QTD_TOKEN_HALT                (1 << 6)

#define QTD_TOKEN_DBERR               (1 << 5)

#define QTD_TOKEN_BABBLE              (1 << 4)

#define QTD_TOKEN_XACTERR             (1 << 3)

#define QTD_TOKEN_MISSEDUF            (1 << 2)

#define QTD_TOKEN_SPLITXSTATE         (1 << 1)

#define QTD_TOKEN_PING                (1 << 0)

    uint32_t bufptr[5];               // Standard buffer pointer

#define QTD_BUFPTR_MASK               0xfffff000

} EHCIqtd;

/*  EHCI spec version 1.0 Section 3.6

 */

typedef struct EHCIqh {

    uint32_t next;                    // Standard next link pointer

    /* endpoint characteristics */

    uint32_t epchar;

#define QH_EPCHAR_RL_MASK             0xf0000000

#define QH_EPCHAR_RL_SH               28

#define QH_EPCHAR_C                   (1 << 27)

#define QH_EPCHAR_MPLEN_MASK          0x07FF0000

#define QH_EPCHAR_MPLEN_SH            16

#define QH_EPCHAR_H                   (1 << 15)

#define QH_EPCHAR_DTC                 (1 << 14)

#define QH_EPCHAR_EPS_MASK            0x00003000

#define QH_EPCHAR_EPS_SH              12

#define EHCI_QH_EPS_FULL              0

#define EHCI_QH_EPS_LOW               1

#define EHCI_QH_EPS_HIGH              2

#define EHCI_QH_EPS_RESERVED          3

#define QH_EPCHAR_EP_MASK             0x00000f00

#define QH_EPCHAR_EP_SH               8

#define QH_EPCHAR_I                   (1 << 7)

#define QH_EPCHAR_DEVADDR_MASK        0x0000007f

#define QH_EPCHAR_DEVADDR_SH          0

    /* endpoint capabilities */

    uint32_t epcap;

#define QH_EPCAP_MULT_MASK            0xc0000000

#define QH_EPCAP_MULT_SH              30

#define QH_EPCAP_PORTNUM_MASK         0x3f800000

#define QH_EPCAP_PORTNUM_SH           23

#define QH_EPCAP_HUBADDR_MASK         0x007f0000

#define QH_EPCAP_HUBADDR_SH           16

#define QH_EPCAP_CMASK_MASK           0x0000ff00

#define QH_EPCAP_CMASK_SH             8

#define QH_EPCAP_SMASK_MASK           0x000000ff

#define QH_EPCAP_SMASK_SH             0

    uint32_t current_qtd;             // Standard next link pointer

    uint32_t next_qtd;                // Standard next link pointer

    uint32_t altnext_qtd;

#define QH_ALTNEXT_NAKCNT_MASK        0x0000001e

#define QH_ALTNEXT_NAKCNT_SH          1

    uint32_t token;                   // Same as QTD token

    uint32_t bufptr[5];               // Standard buffer pointer

#define BUFPTR_CPROGMASK_MASK         0x000000ff

#define BUFPTR_FRAMETAG_MASK          0x0000001f

#define BUFPTR_SBYTES_MASK            0x00000fe0

#define BUFPTR_SBYTES_SH              5

} EHCIqh;

/*  EHCI spec version 1.0 Section 3.7

 */

typedef struct EHCIfstn {

    uint32_t next;                    // Standard next link pointer

    uint32_t backptr;                 // Standard next link pointer

} EHCIfstn;

typedef struct {

    PCIDevice dev;

    qemu_irq irq;

    target_phys_addr_t mem_base;

    int mem;

    int num_ports;

    /*

     *  EHCI spec version 1.0 Section 2.3

     *  Host Controller Operational Registers

     */

    union {

        uint8_t mmio[MMIO_SIZE];

        struct {

            uint8_t cap[OPREGBASE];

            uint32_t usbcmd;

            uint32_t usbsts;

            uint32_t usbintr;

            uint32_t frindex;

            uint32_t ctrldssegment;

            uint32_t periodiclistbase;

            uint32_t asynclistaddr;

            uint32_t notused[9];

            uint32_t configflag;

            uint32_t portsc[NB_PORTS];

        };

    };

    /*

     *  Internal states, shadow registers, etc

     */

    uint32_t sofv;

    QEMUTimer *frame_timer;

    int attach_poll_counter;

    int astate;                        // Current state in asynchronous schedule

    int pstate;                        // Current state in periodic schedule

    USBPort ports[NB_PORTS];

    uint8_t buffer[BUFF_SIZE];

    uint32_t usbsts_pending;

    /* cached data from guest - needs to be flushed

     * when guest removes an entry (doorbell, handshake sequence)

     */

    EHCIqh qh;             // copy of current QH (being worked on)

    uint32_t qhaddr;       // address QH read from

    EHCIqtd qtd;           // copy of current QTD (being worked on)

    uint32_t qtdaddr;      // address QTD read from

    uint32_t itdaddr;      // current ITD

    uint32_t fetch_addr;   // which address to look at next

    USBBus bus;

    USBPacket usb_packet;

    int async_complete;

    uint32_t tbytes;

    int pid;

    int exec_status;

    int isoch_pause;

    uint32_t last_run_usec;

    uint32_t frame_end_usec;

} EHCIState;

#define SET_LAST_RUN_CLOCK(s) \

    (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;

/* nifty macros from Arnon's EHCI version  */

#define get_field(data, field) \

    (((data) & field##_MASK) >> field##_SH)

#define set_field(data, newval, field) do { \

    uint32_t val = *data; \

    val &= ~ field##_MASK; \

    val |= ((newval) << field##_SH) & field##_MASK; \

    *data = val; \

    } while(0)

static const char *ehci_state_names[] = {

    [ EST_INACTIVE ]     = "INACTIVE",

    [ EST_ACTIVE ]       = "ACTIVE",

    [ EST_EXECUTING ]    = "EXECUTING",

    [ EST_SLEEPING ]     = "SLEEPING",

    [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",

    [ EST_FETCHENTRY ]   = "FETCH ENTRY",

    [ EST_FETCHQH ]      = "FETCH QH",

    [ EST_FETCHITD ]     = "FETCH ITD",

    [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",

    [ EST_FETCHQTD ]     = "FETCH QTD",

    [ EST_EXECUTE ]      = "EXECUTE",

    [ EST_WRITEBACK ]    = "WRITEBACK",

    [ EST_HORIZONTALQH ] = "HORIZONTALQH",

};

static const char *ehci_mmio_names[] = {

    [ CAPLENGTH ]        = "CAPLENGTH",

    [ HCIVERSION ]       = "HCIVERSION",

    [ HCSPARAMS ]        = "HCSPARAMS",

    [ HCCPARAMS ]        = "HCCPARAMS",

    [ USBCMD ]           = "USBCMD",

    [ USBSTS ]           = "USBSTS",

    [ USBINTR ]          = "USBINTR",

    [ FRINDEX ]          = "FRINDEX",

    [ PERIODICLISTBASE ] = "P-LIST BASE",

    [ ASYNCLISTADDR ]    = "A-LIST ADDR",

    [ PORTSC_BEGIN ]     = "PORTSC #0",

    [ PORTSC_BEGIN + 4]  = "PORTSC #1",

    [ PORTSC_BEGIN + 8]  = "PORTSC #2",

    [ PORTSC_BEGIN + 12] = "PORTSC #3",

    [ CONFIGFLAG ]       = "CONFIGFLAG",

};

static const char *nr2str(const char **n, size_t len, uint32_t nr)

{

    if (nr < len && n[nr] != NULL) {

        return n[nr];

    } else {

        return "unknown";

    }

}

static const char *state2str(uint32_t state)

{

    return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);

}

static const char *addr2str(target_phys_addr_t addr)

{

    return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);

}

static void ehci_trace_usbsts(uint32_t mask, int state)

{

    /* interrupts */

    if (mask & USBSTS_INT) {

        trace_usb_ehci_usbsts("INT", state);

    }

    if (mask & USBSTS_ERRINT) {

        trace_usb_ehci_usbsts("ERRINT", state);

    }

    if (mask & USBSTS_PCD) {

        trace_usb_ehci_usbsts("PCD", state);

    }

    if (mask & USBSTS_FLR) {

        trace_usb_ehci_usbsts("FLR", state);

    }

    if (mask & USBSTS_HSE) {

        trace_usb_ehci_usbsts("HSE", state);

    }

    if (mask & USBSTS_IAA) {

        trace_usb_ehci_usbsts("IAA", state);

    }

    /* status */

    if (mask & USBSTS_HALT) {

        trace_usb_ehci_usbsts("HALT", state);

    }

    if (mask & USBSTS_REC) {

        trace_usb_ehci_usbsts("REC", state);

    }

    if (mask & USBSTS_PSS) {

        trace_usb_ehci_usbsts("PSS", state);

    }

    if (mask & USBSTS_ASS) {

        trace_usb_ehci_usbsts("ASS", state);

    }

}

static inline void ehci_set_usbsts(EHCIState *s, int mask)

{

    if ((s->usbsts & mask) == mask) {

        return;

    }

    ehci_trace_usbsts(mask, 1);

    s->usbsts |= mask;

}

static inline void ehci_clear_usbsts(EHCIState *s, int mask)

{

    if ((s->usbsts & mask) == 0) {

        return;

    }

    ehci_trace_usbsts(mask, 0);

    s->usbsts &= ~mask;

}

static inline void ehci_set_interrupt(EHCIState *s, int intr)

{

    int level = 0;

    // TODO honour interrupt threshold requests

    ehci_set_usbsts(s, intr);

    if ((s->usbsts & USBINTR_MASK) & s->usbintr) {

        level = 1;

    }

    qemu_set_irq(s->irq, level);

}

static inline void ehci_record_interrupt(EHCIState *s, int intr)

{

    s->usbsts_pending |= intr;

}

static inline void ehci_commit_interrupt(EHCIState *s)

{

    if (!s->usbsts_pending) {

        return;

    }

    ehci_set_interrupt(s, s->usbsts_pending);

    s->usbsts_pending = 0;

}

static void ehci_set_state(EHCIState *s, int async, int state)

{

    if (async) {

        trace_usb_ehci_state("async", state2str(state));

        s->astate = state;

    } else {

        trace_usb_ehci_state("periodic", state2str(state));

        s->pstate = state;

    }

}

static int ehci_get_state(EHCIState *s, int async)

{

    return async ? s->astate : s->pstate;

}

static void ehci_trace_qh(EHCIState *s, target_phys_addr_t addr, EHCIqh *qh)

{

    trace_usb_ehci_qh(addr, qh->next,

                      qh->current_qtd, qh->next_qtd, qh->altnext_qtd,

                      get_field(qh->epchar, QH_EPCHAR_RL),

                      get_field(qh->epchar, QH_EPCHAR_MPLEN),

                      get_field(qh->epchar, QH_EPCHAR_EPS),

                      get_field(qh->epchar, QH_EPCHAR_EP),

                      get_field(qh->epchar, QH_EPCHAR_DEVADDR),

                      (bool)(qh->epchar & QH_EPCHAR_C),

                      (bool)(qh->epchar & QH_EPCHAR_H),

                      (bool)(qh->epchar & QH_EPCHAR_DTC),

                      (bool)(qh->epchar & QH_EPCHAR_I));

}

static void ehci_trace_qtd(EHCIState *s, target_phys_addr_t addr, EHCIqtd *qtd)

{

    trace_usb_ehci_qtd(addr, qtd->next, qtd->altnext,

                       get_field(qtd->token, QTD_TOKEN_TBYTES),

                       get_field(qtd->token, QTD_TOKEN_CPAGE),

                       get_field(qtd->token, QTD_TOKEN_CERR),

                       get_field(qtd->token, QTD_TOKEN_PID),

                       (bool)(qtd->token & QTD_TOKEN_IOC),

                       (bool)(qtd->token & QTD_TOKEN_ACTIVE),

                       (bool)(qtd->token & QTD_TOKEN_HALT),

                       (bool)(qtd->token & QTD_TOKEN_BABBLE),

                       (bool)(qtd->token & QTD_TOKEN_XACTERR));

}

static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)

{

    trace_usb_ehci_itd(addr, itd->next);

}

/* Attach or detach a device on root hub */

static void ehci_attach(USBPort *port)

{

    EHCIState *s = port->opaque;

    uint32_t *portsc = &s->portsc[port->index];

    DPRINTF("ehci_attach invoked for index %d, portsc 0x%x, desc %s\n",

           port->index, *portsc, port->dev->product_desc);

    *portsc |= PORTSC_CONNECT;

    *portsc |= PORTSC_CSC;

    /*

     *  If a high speed device is attached then we own this port(indicated

     *  by zero in the PORTSC_POWNER bit field) so set the status bit

     *  and set an interrupt if enabled.

     */

    if ( !(*portsc & PORTSC_POWNER)) {

        ehci_set_interrupt(s, USBSTS_PCD);

    }

}

static void ehci_detach(USBPort *port)

{

    EHCIState *s = port->opaque;

    uint32_t *portsc = &s->portsc[port->index];

    DPRINTF("ehci_attach invoked for index %d, portsc 0x%x\n",

           port->index, *portsc);

    *portsc &= ~PORTSC_CONNECT;

    *portsc |= PORTSC_CSC;

    /*

     *  If a high speed device is attached then we own this port(indicated

     *  by zero in the PORTSC_POWNER bit field) so set the status bit

     *  and set an interrupt if enabled.

     */

    if ( !(*portsc & PORTSC_POWNER)) {

        ehci_set_interrupt(s, USBSTS_PCD);

    }

}

/* 4.1 host controller initialization */

static void ehci_reset(void *opaque)

{

    EHCIState *s = opaque;

    uint8_t *pci_conf;

    int i;

    trace_usb_ehci_reset();

    pci_conf = s->dev.config;

    memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);

    s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;

    s->usbsts = USBSTS_HALT;

    s->astate = EST_INACTIVE;

    s->pstate = EST_INACTIVE;

    s->async_complete = 0;

    s->isoch_pause = -1;

    s->attach_poll_counter = 0;

    for(i = 0; i < NB_PORTS; i++) {

        s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;

        if (s->ports[i].dev) {

            usb_attach(&s->ports[i], s->ports[i].dev);

        }

    }

}

static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)

{

    EHCIState *s = ptr;

    uint32_t val;

    val = s->mmio[addr];

    return val;

}

static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)

{

    EHCIState *s = ptr;

    uint32_t val;

    val = s->mmio[addr] | (s->mmio[addr+1] << 8);

    return val;

}

static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)

{

    EHCIState *s = ptr;

    uint32_t val;

    val = s->mmio[addr] | (s->mmio[addr+1] << 8) |

          (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);

    trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);

    return val;

}

static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)

{

    fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");

    exit(1);

}

static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)

{

    fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");

    exit(1);

}

static void handle_port_status_write(EHCIState *s, int port, uint32_t val)

{

    uint32_t *portsc = &s->portsc[port];

    int rwc;

    USBDevice *dev = s->ports[port].dev;

    DPRINTF("port_status_write: "

            "PORTSC (port %d) curr %08X new %08X rw-clear %08X rw %08X\n",

            port, *portsc, val, (val & PORTSC_RWC_MASK), val & PORTSC_RO_MASK);

    rwc = val & PORTSC_RWC_MASK;

    val &= PORTSC_RO_MASK;

    // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);

    *portsc &= ~rwc;

    if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {

        DPRINTF("port_status_write: USBTRAN Port %d reset begin\n", port);

    }

    if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {

        DPRINTF("port_status_write: USBTRAN Port %d reset done\n", port);

        usb_attach(&s->ports[port], dev);

        // TODO how to handle reset of ports with no device

        if (dev) {

            usb_send_msg(dev, USB_MSG_RESET);

        }

        if (s->ports[port].dev) {

            DPRINTF("port_status_write: "

                    "Device was connected before reset, clearing CSC bit\n");

            *portsc &= ~PORTSC_CSC;

        }

        /*  Table 2.16 Set the enable bit(and enable bit change) to indicate

         *  to SW that this port has a high speed device attached

         *

         *  TODO - when to disable?

         */

        val |= PORTSC_PED;

        val |= PORTSC_PEDC;

    }

    *portsc &= ~PORTSC_RO_MASK;

    *portsc |= val;

    DPRINTF("port_status_write: Port %d status set to 0x%08x\n", port, *portsc);

}

static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)

{

    EHCIState *s = ptr;

    int i;

    trace_usb_ehci_mmio_writel(addr, addr2str(addr), val,

                               *(uint32_t *)(&s->mmio[addr]));

    /* Only aligned reads are allowed on OHCI */

    if (addr & 3) {

        fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"

                TARGET_FMT_plx "\n", addr);

        return;

    }

    if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {

        handle_port_status_write(s, (addr-PORTSC)/4, val);

        return;

    }

    if (addr < OPREGBASE) {

        fprintf(stderr, "usb-ehci: write attempt to read-only register"

                TARGET_FMT_plx "\n", addr);

        return;

    }

    /* Do any register specific pre-write processing here.  */

    switch(addr) {

    case USBCMD:

        if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {

            qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));

            SET_LAST_RUN_CLOCK(s);

            ehci_clear_usbsts(s, USBSTS_HALT);

        }

        if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {

            qemu_del_timer(s->frame_timer);

            // TODO - should finish out some stuff before setting halt

            ehci_set_usbsts(s, USBSTS_HALT);

        }

        if (val & USBCMD_HCRESET) {

            ehci_reset(s);

            val &= ~USBCMD_HCRESET;

        }

        /* not supporting dynamic frame list size at the moment */

        if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {

            fprintf(stderr, "attempt to set frame list size -- value %d\n",

                    val & USBCMD_FLS);

            val &= ~USBCMD_FLS;

        }

        break;

    case USBSTS:

        val &= USBSTS_RO_MASK;              // bits 6 thru 31 are RO

        ehci_clear_usbsts(s, val);          // bits 0 thru 5 are R/WC

        val = s->usbsts;

        ehci_set_interrupt(s, 0);

        break;

    case USBINTR:

        val &= USBINTR_MASK;

        break;

    case FRINDEX:

        s->sofv = val >> 3;

        break;

    case CONFIGFLAG:

        val &= 0x1;

        if (val) {

            for(i = 0; i < NB_PORTS; i++)

                s->portsc[i] &= ~PORTSC_POWNER;

        }

        break;

    case PERIODICLISTBASE:

        if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {

            fprintf(stderr,

              "ehci: PERIODIC list base register set while periodic schedule\n"

              "      is enabled and HC is enabled\n");

        }

        break;