root / hw / pl080.c @ 273a2142
History | View | Annotate | Download (9.6 kB)
1 | 5fafdf24 | ths | /*
|
---|---|---|---|
2 | e69954b9 | pbrook | * Arm PrimeCell PL080/PL081 DMA controller
|
3 | cdbdb648 | pbrook | *
|
4 | cdbdb648 | pbrook | * Copyright (c) 2006 CodeSourcery.
|
5 | cdbdb648 | pbrook | * Written by Paul Brook
|
6 | cdbdb648 | pbrook | *
|
7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
|
8 | cdbdb648 | pbrook | */
|
9 | cdbdb648 | pbrook | |
10 | b4496b13 | Paul Brook | #include "sysbus.h" |
11 | cdbdb648 | pbrook | |
12 | e69954b9 | pbrook | #define PL080_MAX_CHANNELS 8 |
13 | cdbdb648 | pbrook | #define PL080_CONF_E 0x1 |
14 | cdbdb648 | pbrook | #define PL080_CONF_M1 0x2 |
15 | cdbdb648 | pbrook | #define PL080_CONF_M2 0x4 |
16 | cdbdb648 | pbrook | |
17 | cdbdb648 | pbrook | #define PL080_CCONF_H 0x40000 |
18 | cdbdb648 | pbrook | #define PL080_CCONF_A 0x20000 |
19 | cdbdb648 | pbrook | #define PL080_CCONF_L 0x10000 |
20 | cdbdb648 | pbrook | #define PL080_CCONF_ITC 0x08000 |
21 | cdbdb648 | pbrook | #define PL080_CCONF_IE 0x04000 |
22 | cdbdb648 | pbrook | #define PL080_CCONF_E 0x00001 |
23 | cdbdb648 | pbrook | |
24 | cdbdb648 | pbrook | #define PL080_CCTRL_I 0x80000000 |
25 | cdbdb648 | pbrook | #define PL080_CCTRL_DI 0x08000000 |
26 | cdbdb648 | pbrook | #define PL080_CCTRL_SI 0x04000000 |
27 | cdbdb648 | pbrook | #define PL080_CCTRL_D 0x02000000 |
28 | cdbdb648 | pbrook | #define PL080_CCTRL_S 0x01000000 |
29 | cdbdb648 | pbrook | |
30 | cdbdb648 | pbrook | typedef struct { |
31 | cdbdb648 | pbrook | uint32_t src; |
32 | cdbdb648 | pbrook | uint32_t dest; |
33 | cdbdb648 | pbrook | uint32_t lli; |
34 | cdbdb648 | pbrook | uint32_t ctrl; |
35 | cdbdb648 | pbrook | uint32_t conf; |
36 | cdbdb648 | pbrook | } pl080_channel; |
37 | cdbdb648 | pbrook | |
38 | cdbdb648 | pbrook | typedef struct { |
39 | b4496b13 | Paul Brook | SysBusDevice busdev; |
40 | cdbdb648 | pbrook | uint8_t tc_int; |
41 | cdbdb648 | pbrook | uint8_t tc_mask; |
42 | cdbdb648 | pbrook | uint8_t err_int; |
43 | cdbdb648 | pbrook | uint8_t err_mask; |
44 | cdbdb648 | pbrook | uint32_t conf; |
45 | cdbdb648 | pbrook | uint32_t sync; |
46 | cdbdb648 | pbrook | uint32_t req_single; |
47 | cdbdb648 | pbrook | uint32_t req_burst; |
48 | e69954b9 | pbrook | pl080_channel chan[PL080_MAX_CHANNELS]; |
49 | e69954b9 | pbrook | int nchannels;
|
50 | cdbdb648 | pbrook | /* Flag to avoid recursive DMA invocations. */
|
51 | cdbdb648 | pbrook | int running;
|
52 | d537cf6c | pbrook | qemu_irq irq; |
53 | cdbdb648 | pbrook | } pl080_state; |
54 | cdbdb648 | pbrook | |
55 | cdbdb648 | pbrook | static const unsigned char pl080_id[] = |
56 | cdbdb648 | pbrook | { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
57 | cdbdb648 | pbrook | |
58 | e69954b9 | pbrook | static const unsigned char pl081_id[] = |
59 | e69954b9 | pbrook | { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
60 | e69954b9 | pbrook | |
61 | cdbdb648 | pbrook | static void pl080_update(pl080_state *s) |
62 | cdbdb648 | pbrook | { |
63 | cdbdb648 | pbrook | if ((s->tc_int & s->tc_mask)
|
64 | cdbdb648 | pbrook | || (s->err_int & s->err_mask)) |
65 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
66 | cdbdb648 | pbrook | else
|
67 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
68 | cdbdb648 | pbrook | } |
69 | cdbdb648 | pbrook | |
70 | cdbdb648 | pbrook | static void pl080_run(pl080_state *s) |
71 | cdbdb648 | pbrook | { |
72 | cdbdb648 | pbrook | int c;
|
73 | cdbdb648 | pbrook | int flow;
|
74 | cdbdb648 | pbrook | pl080_channel *ch; |
75 | cdbdb648 | pbrook | int swidth;
|
76 | cdbdb648 | pbrook | int dwidth;
|
77 | cdbdb648 | pbrook | int xsize;
|
78 | cdbdb648 | pbrook | int n;
|
79 | cdbdb648 | pbrook | int src_id;
|
80 | cdbdb648 | pbrook | int dest_id;
|
81 | cdbdb648 | pbrook | int size;
|
82 | b55266b5 | blueswir1 | uint8_t buff[4];
|
83 | cdbdb648 | pbrook | uint32_t req; |
84 | cdbdb648 | pbrook | |
85 | cdbdb648 | pbrook | s->tc_mask = 0;
|
86 | e69954b9 | pbrook | for (c = 0; c < s->nchannels; c++) { |
87 | cdbdb648 | pbrook | if (s->chan[c].conf & PL080_CCONF_ITC)
|
88 | cdbdb648 | pbrook | s->tc_mask |= 1 << c;
|
89 | cdbdb648 | pbrook | if (s->chan[c].conf & PL080_CCONF_IE)
|
90 | cdbdb648 | pbrook | s->err_mask |= 1 << c;
|
91 | cdbdb648 | pbrook | } |
92 | cdbdb648 | pbrook | |
93 | cdbdb648 | pbrook | if ((s->conf & PL080_CONF_E) == 0) |
94 | cdbdb648 | pbrook | return;
|
95 | cdbdb648 | pbrook | |
96 | 2ac71179 | Paul Brook | hw_error("DMA active\n");
|
97 | cdbdb648 | pbrook | /* If we are already in the middle of a DMA operation then indicate that
|
98 | cdbdb648 | pbrook | there may be new DMA requests and return immediately. */
|
99 | cdbdb648 | pbrook | if (s->running) {
|
100 | cdbdb648 | pbrook | s->running++; |
101 | cdbdb648 | pbrook | return;
|
102 | cdbdb648 | pbrook | } |
103 | cdbdb648 | pbrook | s->running = 1;
|
104 | cdbdb648 | pbrook | while (s->running) {
|
105 | e69954b9 | pbrook | for (c = 0; c < s->nchannels; c++) { |
106 | cdbdb648 | pbrook | ch = &s->chan[c]; |
107 | cdbdb648 | pbrook | again:
|
108 | cdbdb648 | pbrook | /* Test if thiws channel has any pending DMA requests. */
|
109 | cdbdb648 | pbrook | if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
|
110 | cdbdb648 | pbrook | != PL080_CCONF_E) |
111 | cdbdb648 | pbrook | continue;
|
112 | cdbdb648 | pbrook | flow = (ch->conf >> 11) & 7; |
113 | cdbdb648 | pbrook | if (flow >= 4) { |
114 | 2ac71179 | Paul Brook | hw_error( |
115 | cdbdb648 | pbrook | "pl080_run: Peripheral flow control not implemented\n");
|
116 | cdbdb648 | pbrook | } |
117 | cdbdb648 | pbrook | src_id = (ch->conf >> 1) & 0x1f; |
118 | cdbdb648 | pbrook | dest_id = (ch->conf >> 6) & 0x1f; |
119 | cdbdb648 | pbrook | size = ch->ctrl & 0xfff;
|
120 | cdbdb648 | pbrook | req = s->req_single | s->req_burst; |
121 | cdbdb648 | pbrook | switch (flow) {
|
122 | cdbdb648 | pbrook | case 0: |
123 | cdbdb648 | pbrook | break;
|
124 | cdbdb648 | pbrook | case 1: |
125 | cdbdb648 | pbrook | if ((req & (1u << dest_id)) == 0) |
126 | cdbdb648 | pbrook | size = 0;
|
127 | cdbdb648 | pbrook | break;
|
128 | cdbdb648 | pbrook | case 2: |
129 | cdbdb648 | pbrook | if ((req & (1u << src_id)) == 0) |
130 | cdbdb648 | pbrook | size = 0;
|
131 | cdbdb648 | pbrook | break;
|
132 | cdbdb648 | pbrook | case 3: |
133 | cdbdb648 | pbrook | if ((req & (1u << src_id)) == 0 |
134 | cdbdb648 | pbrook | || (req & (1u << dest_id)) == 0) |
135 | cdbdb648 | pbrook | size = 0;
|
136 | cdbdb648 | pbrook | break;
|
137 | cdbdb648 | pbrook | } |
138 | cdbdb648 | pbrook | if (!size)
|
139 | cdbdb648 | pbrook | continue;
|
140 | cdbdb648 | pbrook | |
141 | cdbdb648 | pbrook | /* Transfer one element. */
|
142 | cdbdb648 | pbrook | /* ??? Should transfer multiple elements for a burst request. */
|
143 | cdbdb648 | pbrook | /* ??? Unclear what the proper behavior is when source and
|
144 | cdbdb648 | pbrook | destination widths are different. */
|
145 | cdbdb648 | pbrook | swidth = 1 << ((ch->ctrl >> 18) & 7); |
146 | cdbdb648 | pbrook | dwidth = 1 << ((ch->ctrl >> 21) & 7); |
147 | cdbdb648 | pbrook | for (n = 0; n < dwidth; n+= swidth) { |
148 | cdbdb648 | pbrook | cpu_physical_memory_read(ch->src, buff + n, swidth); |
149 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_SI)
|
150 | cdbdb648 | pbrook | ch->src += swidth; |
151 | cdbdb648 | pbrook | } |
152 | cdbdb648 | pbrook | xsize = (dwidth < swidth) ? swidth : dwidth; |
153 | cdbdb648 | pbrook | /* ??? This may pad the value incorrectly for dwidth < 32. */
|
154 | cdbdb648 | pbrook | for (n = 0; n < xsize; n += dwidth) { |
155 | cdbdb648 | pbrook | cpu_physical_memory_write(ch->dest + n, buff + n, dwidth); |
156 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_DI)
|
157 | cdbdb648 | pbrook | ch->dest += swidth; |
158 | cdbdb648 | pbrook | } |
159 | cdbdb648 | pbrook | |
160 | cdbdb648 | pbrook | size--; |
161 | cdbdb648 | pbrook | ch->ctrl = (ch->ctrl & 0xfffff000) | size;
|
162 | cdbdb648 | pbrook | if (size == 0) { |
163 | cdbdb648 | pbrook | /* Transfer complete. */
|
164 | cdbdb648 | pbrook | if (ch->lli) {
|
165 | cdbdb648 | pbrook | ch->src = ldl_phys(ch->lli); |
166 | cdbdb648 | pbrook | ch->dest = ldl_phys(ch->lli + 4);
|
167 | cdbdb648 | pbrook | ch->ctrl = ldl_phys(ch->lli + 12);
|
168 | cdbdb648 | pbrook | ch->lli = ldl_phys(ch->lli + 8);
|
169 | cdbdb648 | pbrook | } else {
|
170 | cdbdb648 | pbrook | ch->conf &= ~PL080_CCONF_E; |
171 | cdbdb648 | pbrook | } |
172 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_I) {
|
173 | cdbdb648 | pbrook | s->tc_int |= 1 << c;
|
174 | cdbdb648 | pbrook | } |
175 | cdbdb648 | pbrook | } |
176 | cdbdb648 | pbrook | goto again;
|
177 | cdbdb648 | pbrook | } |
178 | cdbdb648 | pbrook | if (--s->running)
|
179 | cdbdb648 | pbrook | s->running = 1;
|
180 | cdbdb648 | pbrook | } |
181 | cdbdb648 | pbrook | } |
182 | cdbdb648 | pbrook | |
183 | cdbdb648 | pbrook | static uint32_t pl080_read(void *opaque, target_phys_addr_t offset) |
184 | cdbdb648 | pbrook | { |
185 | cdbdb648 | pbrook | pl080_state *s = (pl080_state *)opaque; |
186 | cdbdb648 | pbrook | uint32_t i; |
187 | cdbdb648 | pbrook | uint32_t mask; |
188 | cdbdb648 | pbrook | |
189 | cdbdb648 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) { |
190 | e69954b9 | pbrook | if (s->nchannels == 8) { |
191 | e69954b9 | pbrook | return pl080_id[(offset - 0xfe0) >> 2]; |
192 | e69954b9 | pbrook | } else {
|
193 | e69954b9 | pbrook | return pl081_id[(offset - 0xfe0) >> 2]; |
194 | e69954b9 | pbrook | } |
195 | cdbdb648 | pbrook | } |
196 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x200) { |
197 | cdbdb648 | pbrook | i = (offset & 0xe0) >> 5; |
198 | e69954b9 | pbrook | if (i >= s->nchannels)
|
199 | e69954b9 | pbrook | goto bad_offset;
|
200 | cdbdb648 | pbrook | switch (offset >> 2) { |
201 | cdbdb648 | pbrook | case 0: /* SrcAddr */ |
202 | cdbdb648 | pbrook | return s->chan[i].src;
|
203 | cdbdb648 | pbrook | case 1: /* DestAddr */ |
204 | cdbdb648 | pbrook | return s->chan[i].dest;
|
205 | cdbdb648 | pbrook | case 2: /* LLI */ |
206 | cdbdb648 | pbrook | return s->chan[i].lli;
|
207 | cdbdb648 | pbrook | case 3: /* Control */ |
208 | cdbdb648 | pbrook | return s->chan[i].ctrl;
|
209 | cdbdb648 | pbrook | case 4: /* Configuration */ |
210 | cdbdb648 | pbrook | return s->chan[i].conf;
|
211 | cdbdb648 | pbrook | default:
|
212 | cdbdb648 | pbrook | goto bad_offset;
|
213 | cdbdb648 | pbrook | } |
214 | cdbdb648 | pbrook | } |
215 | cdbdb648 | pbrook | switch (offset >> 2) { |
216 | cdbdb648 | pbrook | case 0: /* IntStatus */ |
217 | cdbdb648 | pbrook | return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
|
218 | cdbdb648 | pbrook | case 1: /* IntTCStatus */ |
219 | cdbdb648 | pbrook | return (s->tc_int & s->tc_mask);
|
220 | cdbdb648 | pbrook | case 3: /* IntErrorStatus */ |
221 | cdbdb648 | pbrook | return (s->err_int & s->err_mask);
|
222 | cdbdb648 | pbrook | case 5: /* RawIntTCStatus */ |
223 | cdbdb648 | pbrook | return s->tc_int;
|
224 | cdbdb648 | pbrook | case 6: /* RawIntErrorStatus */ |
225 | cdbdb648 | pbrook | return s->err_int;
|
226 | cdbdb648 | pbrook | case 7: /* EnbldChns */ |
227 | cdbdb648 | pbrook | mask = 0;
|
228 | e69954b9 | pbrook | for (i = 0; i < s->nchannels; i++) { |
229 | cdbdb648 | pbrook | if (s->chan[i].conf & PL080_CCONF_E)
|
230 | cdbdb648 | pbrook | mask |= 1 << i;
|
231 | cdbdb648 | pbrook | } |
232 | cdbdb648 | pbrook | return mask;
|
233 | cdbdb648 | pbrook | case 8: /* SoftBReq */ |
234 | cdbdb648 | pbrook | case 9: /* SoftSReq */ |
235 | cdbdb648 | pbrook | case 10: /* SoftLBReq */ |
236 | cdbdb648 | pbrook | case 11: /* SoftLSReq */ |
237 | cdbdb648 | pbrook | /* ??? Implement these. */
|
238 | cdbdb648 | pbrook | return 0; |
239 | cdbdb648 | pbrook | case 12: /* Configuration */ |
240 | cdbdb648 | pbrook | return s->conf;
|
241 | cdbdb648 | pbrook | case 13: /* Sync */ |
242 | cdbdb648 | pbrook | return s->sync;
|
243 | cdbdb648 | pbrook | default:
|
244 | cdbdb648 | pbrook | bad_offset:
|
245 | 2ac71179 | Paul Brook | hw_error("pl080_read: Bad offset %x\n", (int)offset); |
246 | cdbdb648 | pbrook | return 0; |
247 | cdbdb648 | pbrook | } |
248 | cdbdb648 | pbrook | } |
249 | cdbdb648 | pbrook | |
250 | cdbdb648 | pbrook | static void pl080_write(void *opaque, target_phys_addr_t offset, |
251 | cdbdb648 | pbrook | uint32_t value) |
252 | cdbdb648 | pbrook | { |
253 | cdbdb648 | pbrook | pl080_state *s = (pl080_state *)opaque; |
254 | cdbdb648 | pbrook | int i;
|
255 | cdbdb648 | pbrook | |
256 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x200) { |
257 | cdbdb648 | pbrook | i = (offset & 0xe0) >> 5; |
258 | e69954b9 | pbrook | if (i >= s->nchannels)
|
259 | e69954b9 | pbrook | goto bad_offset;
|
260 | cdbdb648 | pbrook | switch (offset >> 2) { |
261 | cdbdb648 | pbrook | case 0: /* SrcAddr */ |
262 | cdbdb648 | pbrook | s->chan[i].src = value; |
263 | cdbdb648 | pbrook | break;
|
264 | cdbdb648 | pbrook | case 1: /* DestAddr */ |
265 | cdbdb648 | pbrook | s->chan[i].dest = value; |
266 | cdbdb648 | pbrook | break;
|
267 | cdbdb648 | pbrook | case 2: /* LLI */ |
268 | cdbdb648 | pbrook | s->chan[i].lli = value; |
269 | cdbdb648 | pbrook | break;
|
270 | cdbdb648 | pbrook | case 3: /* Control */ |
271 | cdbdb648 | pbrook | s->chan[i].ctrl = value; |
272 | cdbdb648 | pbrook | break;
|
273 | cdbdb648 | pbrook | case 4: /* Configuration */ |
274 | cdbdb648 | pbrook | s->chan[i].conf = value; |
275 | cdbdb648 | pbrook | pl080_run(s); |
276 | cdbdb648 | pbrook | break;
|
277 | cdbdb648 | pbrook | } |
278 | cdbdb648 | pbrook | } |
279 | cdbdb648 | pbrook | switch (offset >> 2) { |
280 | cdbdb648 | pbrook | case 2: /* IntTCClear */ |
281 | cdbdb648 | pbrook | s->tc_int &= ~value; |
282 | cdbdb648 | pbrook | break;
|
283 | cdbdb648 | pbrook | case 4: /* IntErrorClear */ |
284 | cdbdb648 | pbrook | s->err_int &= ~value; |
285 | cdbdb648 | pbrook | break;
|
286 | cdbdb648 | pbrook | case 8: /* SoftBReq */ |
287 | cdbdb648 | pbrook | case 9: /* SoftSReq */ |
288 | cdbdb648 | pbrook | case 10: /* SoftLBReq */ |
289 | cdbdb648 | pbrook | case 11: /* SoftLSReq */ |
290 | cdbdb648 | pbrook | /* ??? Implement these. */
|
291 | 2ac71179 | Paul Brook | hw_error("pl080_write: Soft DMA not implemented\n");
|
292 | cdbdb648 | pbrook | break;
|
293 | cdbdb648 | pbrook | case 12: /* Configuration */ |
294 | cdbdb648 | pbrook | s->conf = value; |
295 | cdbdb648 | pbrook | if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
|
296 | 2ac71179 | Paul Brook | hw_error("pl080_write: Big-endian DMA not implemented\n");
|
297 | cdbdb648 | pbrook | } |
298 | cdbdb648 | pbrook | pl080_run(s); |
299 | cdbdb648 | pbrook | break;
|
300 | cdbdb648 | pbrook | case 13: /* Sync */ |
301 | cdbdb648 | pbrook | s->sync = value; |
302 | cdbdb648 | pbrook | break;
|
303 | cdbdb648 | pbrook | default:
|
304 | e69954b9 | pbrook | bad_offset:
|
305 | 2ac71179 | Paul Brook | hw_error("pl080_write: Bad offset %x\n", (int)offset); |
306 | cdbdb648 | pbrook | } |
307 | cdbdb648 | pbrook | pl080_update(s); |
308 | cdbdb648 | pbrook | } |
309 | cdbdb648 | pbrook | |
310 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pl080_readfn[] = { |
311 | cdbdb648 | pbrook | pl080_read, |
312 | cdbdb648 | pbrook | pl080_read, |
313 | cdbdb648 | pbrook | pl080_read |
314 | cdbdb648 | pbrook | }; |
315 | cdbdb648 | pbrook | |
316 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pl080_writefn[] = { |
317 | cdbdb648 | pbrook | pl080_write, |
318 | cdbdb648 | pbrook | pl080_write, |
319 | cdbdb648 | pbrook | pl080_write |
320 | cdbdb648 | pbrook | }; |
321 | cdbdb648 | pbrook | |
322 | 81a322d4 | Gerd Hoffmann | static int pl08x_init(SysBusDevice *dev, int nchannels) |
323 | cdbdb648 | pbrook | { |
324 | cdbdb648 | pbrook | int iomemtype;
|
325 | b4496b13 | Paul Brook | pl080_state *s = FROM_SYSBUS(pl080_state, dev); |
326 | cdbdb648 | pbrook | |
327 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(pl080_readfn, |
328 | cdbdb648 | pbrook | pl080_writefn, s); |
329 | b4496b13 | Paul Brook | sysbus_init_mmio(dev, 0x1000, iomemtype);
|
330 | b4496b13 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
331 | e69954b9 | pbrook | s->nchannels = nchannels; |
332 | cdbdb648 | pbrook | /* ??? Save/restore. */
|
333 | 81a322d4 | Gerd Hoffmann | return 0; |
334 | cdbdb648 | pbrook | } |
335 | b4496b13 | Paul Brook | |
336 | 81a322d4 | Gerd Hoffmann | static int pl080_init(SysBusDevice *dev) |
337 | b4496b13 | Paul Brook | { |
338 | 81a322d4 | Gerd Hoffmann | return pl08x_init(dev, 8); |
339 | b4496b13 | Paul Brook | } |
340 | b4496b13 | Paul Brook | |
341 | 81a322d4 | Gerd Hoffmann | static int pl081_init(SysBusDevice *dev) |
342 | b4496b13 | Paul Brook | { |
343 | 81a322d4 | Gerd Hoffmann | return pl08x_init(dev, 2); |
344 | b4496b13 | Paul Brook | } |
345 | b4496b13 | Paul Brook | |
346 | b4496b13 | Paul Brook | /* The PL080 and PL081 are the same except for the number of channels
|
347 | b4496b13 | Paul Brook | they implement (8 and 2 respectively). */
|
348 | b4496b13 | Paul Brook | static void pl080_register_devices(void) |
349 | b4496b13 | Paul Brook | { |
350 | b4496b13 | Paul Brook | sysbus_register_dev("pl080", sizeof(pl080_state), pl080_init); |
351 | b4496b13 | Paul Brook | sysbus_register_dev("pl081", sizeof(pl080_state), pl081_init); |
352 | b4496b13 | Paul Brook | } |
353 | b4496b13 | Paul Brook | |
354 | b4496b13 | Paul Brook | device_init(pl080_register_devices) |