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/*
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h" |
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#include "qemu-timer.h" |
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#include "sun4m.h" |
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#include "nvram.h" |
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#include "sparc32_dma.h" |
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#include "fdc.h" |
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#include "sysemu.h" |
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#include "net.h" |
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#include "boards.h" |
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#include "firmware_abi.h" |
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#include "scsi.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "fw_cfg.h" |
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#include "escc.h" |
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#include "qdev-addr.h" |
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//#define DEBUG_IRQ
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/*
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* Sun4m architecture was used in the following machines:
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*
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* SPARCserver 6xxMP/xx
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* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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* SPARCclassic X (4/10)
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* SPARCstation LX/ZX (4/30)
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* SPARCstation Voyager
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* SPARCstation 10/xx, SPARCserver 10/xx
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* SPARCstation 5, SPARCserver 5
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* Sun4d architecture was used in the following machines:
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*
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* SPARCcenter 2000
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* SPARCserver 1000
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*
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* Sun4c architecture was used in the following machines:
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* SPARCstation 1/1+, SPARCserver 1/1+
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* SPARCstation SLC
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* SPARCstation IPC
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* SPARCstation ELC
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* SPARCstation IPX
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00004000 |
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#define CMDLINE_ADDR 0x007ff000 |
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#define INITRD_LOAD_ADDR 0x00800000 |
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#define PROM_SIZE_MAX (1024 * 1024) |
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#define PROM_VADDR 0xffd00000 |
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#define PROM_FILENAME "openbios-sparc32" |
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#define CFG_ADDR 0xd00000510ULL |
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#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
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#define MAX_CPUS 16 |
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#define MAX_PILS 16 |
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#define ESCC_CLOCK 4915200 |
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struct sun4m_hwdef {
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target_phys_addr_t iommu_base, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
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target_phys_addr_t ecc_base; |
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uint32_t ecc_version; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iommu_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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#define MAX_IOUNITS 5 |
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struct sun4d_hwdef {
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target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
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target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base; |
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target_phys_addr_t espdma_base, esp_base; |
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target_phys_addr_t ledma_base, le_base; |
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target_phys_addr_t tcx_base; |
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target_phys_addr_t sbi_base; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iounit_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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struct sun4c_hwdef {
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target_phys_addr_t iommu_base, slavio_base; |
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
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target_phys_addr_t serial_base, fd_base; |
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
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target_phys_addr_t tcx_base, aux1_base; |
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uint8_t nvram_machine_id; |
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uint16_t machine_id; |
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uint32_t iommu_version; |
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uint64_t max_mem; |
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const char * const default_cpu_model; |
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}; |
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int DMA_get_channel_mode (int nchan) |
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{ |
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return 0; |
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} |
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int DMA_read_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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int DMA_write_memory (int nchan, void *buf, int pos, int size) |
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{ |
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return 0; |
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} |
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void DMA_hold_DREQ (int nchan) {} |
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void DMA_release_DREQ (int nchan) {} |
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void DMA_schedule(int nchan) {} |
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void DMA_init (int high_page_enable) {} |
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void DMA_register_channel (int nchan, |
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DMA_transfer_handler transfer_handler, |
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void *opaque)
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{ |
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} |
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static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
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{ |
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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return 0; |
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} |
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static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
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const char *boot_devices, ram_addr_t RAM_size, |
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uint32_t kernel_size, |
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int width, int height, int depth, |
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int nvram_machine_id, const char *arch) |
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{ |
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unsigned int i; |
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uint32_t start, end; |
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image)); |
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start = 0;
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM; |
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pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
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end = start + sizeof(struct OpenBIOS_nvpart_v1); |
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for (i = 0; i < nb_prom_envs; i++) |
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end = OpenBIOS_set_var(image, end, prom_envs[i]); |
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15); |
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OpenBIOS_finish_partition(part_header, end - start); |
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// free partition
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start = end; |
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE; |
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pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start); |
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
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nvram_machine_id); |
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for (i = 0; i < sizeof(image); i++) |
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m48t59_write(nvram, i, image[i]); |
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} |
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static DeviceState *slavio_intctl;
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void pic_info(Monitor *mon)
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{ |
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if (slavio_intctl)
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slavio_pic_info(mon, slavio_intctl); |
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} |
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void irq_info(Monitor *mon)
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{ |
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if (slavio_intctl)
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slavio_irq_info(mon, slavio_intctl); |
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} |
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void cpu_check_irqs(CPUState *env)
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{ |
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if (env->pil_in && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i; |
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for (i = 15; i > 0; i--) { |
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if (env->pil_in & (1 << i)) { |
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index) {
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DPRINTF("Set CPU IRQ %d\n", i);
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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break;
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} |
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} |
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
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DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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static void cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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CPUState *env = opaque; |
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if (level) {
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DPRINTF("Raise CPU IRQ %d\n", irq);
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env->halted = 0;
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env->pil_in |= 1 << irq;
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cpu_check_irqs(env); |
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} else {
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DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env); |
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} |
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} |
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static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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} |
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static void main_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 0;
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} |
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static void secondary_cpu_reset(void *opaque) |
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{ |
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CPUState *env = opaque; |
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cpu_reset(env); |
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env->halted = 1;
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} |
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static void cpu_halt_signal(void *opaque, int irq, int level) |
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{ |
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if (level && cpu_single_env)
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
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} |
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static unsigned long sun4m_load_kernel(const char *kernel_filename, |
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const char *initrd_filename, |
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ram_addr_t RAM_size) |
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{ |
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int linux_boot;
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unsigned int i; |
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long initrd_size, kernel_size;
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
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NULL);
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if (kernel_size < 0) |
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR); |
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if (kernel_size < 0) |
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kernel_size = load_image_targphys(kernel_filename, |
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KERNEL_LOAD_ADDR, |
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RAM_size - KERNEL_LOAD_ADDR); |
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if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename, |
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INITRD_LOAD_ADDR, |
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RAM_size - INITRD_LOAD_ADDR); |
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if (initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} |
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if (initrd_size > 0) { |
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
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if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
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stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
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break;
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} |
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} |
340 |
} |
341 |
} |
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return kernel_size;
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} |
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static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
349 |
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dev = qdev_create(NULL, "iommu"); |
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qdev_prop_set_uint32(dev, "version", version);
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qdev_init(dev); |
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s = sysbus_from_qdev(dev); |
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sysbus_connect_irq(s, 0, irq);
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sysbus_mmio_map(s, 0, addr);
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return s;
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} |
359 |
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static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
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void *iommu, qemu_irq *dev_irq)
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{ |
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DeviceState *dev; |
364 |
SysBusDevice *s; |
365 |
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dev = qdev_create(NULL, "sparc32_dma"); |
367 |
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
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qdev_init(dev); |
369 |
s = sysbus_from_qdev(dev); |
370 |
sysbus_connect_irq(s, 0, parent_irq);
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*dev_irq = qdev_get_gpio_in(dev, 0);
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sysbus_mmio_map(s, 0, daddr);
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373 |
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return s;
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} |
376 |
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static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
378 |
void *dma_opaque, qemu_irq irq)
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{ |
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DeviceState *dev; |
381 |
SysBusDevice *s; |
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qemu_irq reset; |
383 |
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qemu_check_nic_model(&nd_table[0], "lance"); |
385 |
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dev = qdev_create(NULL, "lance"); |
387 |
dev->nd = nd; |
388 |
qdev_prop_set_ptr(dev, "dma", dma_opaque);
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qdev_init(dev); |
390 |
s = sysbus_from_qdev(dev); |
391 |
sysbus_mmio_map(s, 0, leaddr);
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sysbus_connect_irq(s, 0, irq);
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reset = qdev_get_gpio_in(dev, 0);
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qdev_connect_gpio_out(dma_opaque, 0, reset);
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} |
396 |
|
397 |
static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
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target_phys_addr_t addrg, |
399 |
qemu_irq **parent_irq) |
400 |
{ |
401 |
DeviceState *dev; |
402 |
SysBusDevice *s; |
403 |
unsigned int i, j; |
404 |
|
405 |
dev = qdev_create(NULL, "slavio_intctl"); |
406 |
qdev_init(dev); |
407 |
|
408 |
s = sysbus_from_qdev(dev); |
409 |
|
410 |
for (i = 0; i < MAX_CPUS; i++) { |
411 |
for (j = 0; j < MAX_PILS; j++) { |
412 |
sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
413 |
} |
414 |
} |
415 |
sysbus_mmio_map(s, 0, addrg);
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416 |
for (i = 0; i < MAX_CPUS; i++) { |
417 |
sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
418 |
} |
419 |
|
420 |
return dev;
|
421 |
} |
422 |
|
423 |
#define SYS_TIMER_OFFSET 0x10000ULL |
424 |
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
425 |
|
426 |
static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
427 |
qemu_irq *cpu_irqs, unsigned int num_cpus) |
428 |
{ |
429 |
DeviceState *dev; |
430 |
SysBusDevice *s; |
431 |
unsigned int i; |
432 |
|
433 |
dev = qdev_create(NULL, "slavio_timer"); |
434 |
qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
435 |
qdev_init(dev); |
436 |
s = sysbus_from_qdev(dev); |
437 |
sysbus_connect_irq(s, 0, master_irq);
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438 |
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
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439 |
|
440 |
for (i = 0; i < MAX_CPUS; i++) { |
441 |
sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
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sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
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} |
444 |
} |
445 |
|
446 |
#define MISC_LEDS 0x01600000 |
447 |
#define MISC_CFG 0x01800000 |
448 |
#define MISC_DIAG 0x01a00000 |
449 |
#define MISC_MDM 0x01b00000 |
450 |
#define MISC_SYS 0x01f00000 |
451 |
|
452 |
static void slavio_misc_init(target_phys_addr_t base, |
453 |
target_phys_addr_t aux1_base, |
454 |
target_phys_addr_t aux2_base, qemu_irq irq, |
455 |
qemu_irq fdc_tc) |
456 |
{ |
457 |
DeviceState *dev; |
458 |
SysBusDevice *s; |
459 |
|
460 |
dev = qdev_create(NULL, "slavio_misc"); |
461 |
qdev_init(dev); |
462 |
s = sysbus_from_qdev(dev); |
463 |
if (base) {
|
464 |
/* 8 bit registers */
|
465 |
/* Slavio control */
|
466 |
sysbus_mmio_map(s, 0, base + MISC_CFG);
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467 |
/* Diagnostics */
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468 |
sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
469 |
/* Modem control */
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470 |
sysbus_mmio_map(s, 2, base + MISC_MDM);
|
471 |
/* 16 bit registers */
|
472 |
/* ss600mp diag LEDs */
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473 |
sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
474 |
/* 32 bit registers */
|
475 |
/* System control */
|
476 |
sysbus_mmio_map(s, 4, base + MISC_SYS);
|
477 |
} |
478 |
if (aux1_base) {
|
479 |
/* AUX 1 (Misc System Functions) */
|
480 |
sysbus_mmio_map(s, 5, aux1_base);
|
481 |
} |
482 |
if (aux2_base) {
|
483 |
/* AUX 2 (Software Powerdown Control) */
|
484 |
sysbus_mmio_map(s, 6, aux2_base);
|
485 |
} |
486 |
sysbus_connect_irq(s, 0, irq);
|
487 |
sysbus_connect_irq(s, 1, fdc_tc);
|
488 |
qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
489 |
} |
490 |
|
491 |
static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
492 |
{ |
493 |
DeviceState *dev; |
494 |
SysBusDevice *s; |
495 |
|
496 |
dev = qdev_create(NULL, "eccmemctl"); |
497 |
qdev_prop_set_uint32(dev, "version", version);
|
498 |
qdev_init(dev); |
499 |
s = sysbus_from_qdev(dev); |
500 |
sysbus_connect_irq(s, 0, irq);
|
501 |
sysbus_mmio_map(s, 0, base);
|
502 |
if (version == 0) { // SS-600MP only |
503 |
sysbus_mmio_map(s, 1, base + 0x1000); |
504 |
} |
505 |
} |
506 |
|
507 |
static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
508 |
{ |
509 |
DeviceState *dev; |
510 |
SysBusDevice *s; |
511 |
|
512 |
dev = qdev_create(NULL, "apc"); |
513 |
qdev_init(dev); |
514 |
s = sysbus_from_qdev(dev); |
515 |
/* Power management (APC) XXX: not a Slavio device */
|
516 |
sysbus_mmio_map(s, 0, power_base);
|
517 |
sysbus_connect_irq(s, 0, cpu_halt);
|
518 |
} |
519 |
|
520 |
static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
521 |
int height, int depth) |
522 |
{ |
523 |
DeviceState *dev; |
524 |
SysBusDevice *s; |
525 |
|
526 |
dev = qdev_create(NULL, "SUNW,tcx"); |
527 |
qdev_prop_set_taddr(dev, "addr", addr);
|
528 |
qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
529 |
qdev_prop_set_uint16(dev, "width", width);
|
530 |
qdev_prop_set_uint16(dev, "height", height);
|
531 |
qdev_prop_set_uint16(dev, "depth", depth);
|
532 |
qdev_init(dev); |
533 |
s = sysbus_from_qdev(dev); |
534 |
/* 8-bit plane */
|
535 |
sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
536 |
/* DAC */
|
537 |
sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
538 |
/* TEC (dummy) */
|
539 |
sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
540 |
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
541 |
sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
542 |
if (depth == 24) { |
543 |
/* 24-bit plane */
|
544 |
sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
545 |
/* Control plane */
|
546 |
sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
547 |
} else {
|
548 |
/* THC 8 bit (dummy) */
|
549 |
sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
550 |
} |
551 |
} |
552 |
|
553 |
/* NCR89C100/MACIO Internal ID register */
|
554 |
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
555 |
|
556 |
static void idreg_init(target_phys_addr_t addr) |
557 |
{ |
558 |
DeviceState *dev; |
559 |
SysBusDevice *s; |
560 |
|
561 |
dev = qdev_create(NULL, "macio_idreg"); |
562 |
qdev_init(dev); |
563 |
s = sysbus_from_qdev(dev); |
564 |
|
565 |
sysbus_mmio_map(s, 0, addr);
|
566 |
cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
567 |
} |
568 |
|
569 |
static int idreg_init1(SysBusDevice *dev) |
570 |
{ |
571 |
ram_addr_t idreg_offset; |
572 |
|
573 |
idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
|
574 |
sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
|
575 |
return 0; |
576 |
} |
577 |
|
578 |
static SysBusDeviceInfo idreg_info = {
|
579 |
.init = idreg_init1, |
580 |
.qdev.name = "macio_idreg",
|
581 |
.qdev.size = sizeof(SysBusDevice),
|
582 |
}; |
583 |
|
584 |
static void idreg_register_devices(void) |
585 |
{ |
586 |
sysbus_register_withprop(&idreg_info); |
587 |
} |
588 |
|
589 |
device_init(idreg_register_devices); |
590 |
|
591 |
/* Boot PROM (OpenBIOS) */
|
592 |
static void prom_init(target_phys_addr_t addr, const char *bios_name) |
593 |
{ |
594 |
DeviceState *dev; |
595 |
SysBusDevice *s; |
596 |
char *filename;
|
597 |
int ret;
|
598 |
|
599 |
dev = qdev_create(NULL, "openprom"); |
600 |
qdev_init(dev); |
601 |
s = sysbus_from_qdev(dev); |
602 |
|
603 |
sysbus_mmio_map(s, 0, addr);
|
604 |
|
605 |
/* load boot prom */
|
606 |
if (bios_name == NULL) { |
607 |
bios_name = PROM_FILENAME; |
608 |
} |
609 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
610 |
if (filename) {
|
611 |
ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL); |
612 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
613 |
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
614 |
} |
615 |
qemu_free(filename); |
616 |
} else {
|
617 |
ret = -1;
|
618 |
} |
619 |
if (ret < 0 || ret > PROM_SIZE_MAX) { |
620 |
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
621 |
exit(1);
|
622 |
} |
623 |
} |
624 |
|
625 |
static int prom_init1(SysBusDevice *dev) |
626 |
{ |
627 |
ram_addr_t prom_offset; |
628 |
|
629 |
prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
630 |
sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
631 |
return 0; |
632 |
} |
633 |
|
634 |
static SysBusDeviceInfo prom_info = {
|
635 |
.init = prom_init1, |
636 |
.qdev.name = "openprom",
|
637 |
.qdev.size = sizeof(SysBusDevice),
|
638 |
.qdev.props = (Property[]) { |
639 |
{/* end of property list */}
|
640 |
} |
641 |
}; |
642 |
|
643 |
static void prom_register_devices(void) |
644 |
{ |
645 |
sysbus_register_withprop(&prom_info); |
646 |
} |
647 |
|
648 |
device_init(prom_register_devices); |
649 |
|
650 |
typedef struct RamDevice |
651 |
{ |
652 |
SysBusDevice busdev; |
653 |
uint64_t size; |
654 |
} RamDevice; |
655 |
|
656 |
/* System RAM */
|
657 |
static int ram_init1(SysBusDevice *dev) |
658 |
{ |
659 |
ram_addr_t RAM_size, ram_offset; |
660 |
RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
661 |
|
662 |
RAM_size = d->size; |
663 |
|
664 |
ram_offset = qemu_ram_alloc(RAM_size); |
665 |
sysbus_init_mmio(dev, RAM_size, ram_offset); |
666 |
return 0; |
667 |
} |
668 |
|
669 |
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
670 |
uint64_t max_mem) |
671 |
{ |
672 |
DeviceState *dev; |
673 |
SysBusDevice *s; |
674 |
RamDevice *d; |
675 |
|
676 |
/* allocate RAM */
|
677 |
if ((uint64_t)RAM_size > max_mem) {
|
678 |
fprintf(stderr, |
679 |
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
680 |
(unsigned int)(RAM_size / (1024 * 1024)), |
681 |
(unsigned int)(max_mem / (1024 * 1024))); |
682 |
exit(1);
|
683 |
} |
684 |
dev = qdev_create(NULL, "memory"); |
685 |
s = sysbus_from_qdev(dev); |
686 |
|
687 |
d = FROM_SYSBUS(RamDevice, s); |
688 |
d->size = RAM_size; |
689 |
qdev_init(dev); |
690 |
|
691 |
sysbus_mmio_map(s, 0, addr);
|
692 |
} |
693 |
|
694 |
static SysBusDeviceInfo ram_info = {
|
695 |
.init = ram_init1, |
696 |
.qdev.name = "memory",
|
697 |
.qdev.size = sizeof(RamDevice),
|
698 |
.qdev.props = (Property[]) { |
699 |
DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
700 |
DEFINE_PROP_END_OF_LIST(), |
701 |
} |
702 |
}; |
703 |
|
704 |
static void ram_register_devices(void) |
705 |
{ |
706 |
sysbus_register_withprop(&ram_info); |
707 |
} |
708 |
|
709 |
device_init(ram_register_devices); |
710 |
|
711 |
static CPUState *cpu_devinit(const char *cpu_model, unsigned int id, |
712 |
uint64_t prom_addr, qemu_irq **cpu_irqs) |
713 |
{ |
714 |
CPUState *env; |
715 |
|
716 |
env = cpu_init(cpu_model); |
717 |
if (!env) {
|
718 |
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
719 |
exit(1);
|
720 |
} |
721 |
|
722 |
cpu_sparc_set_id(env, id); |
723 |
if (id == 0) { |
724 |
qemu_register_reset(main_cpu_reset, env); |
725 |
} else {
|
726 |
qemu_register_reset(secondary_cpu_reset, env); |
727 |
env->halted = 1;
|
728 |
} |
729 |
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
730 |
env->prom_addr = prom_addr; |
731 |
|
732 |
return env;
|
733 |
} |
734 |
|
735 |
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
736 |
const char *boot_device, |
737 |
const char *kernel_filename, |
738 |
const char *kernel_cmdline, |
739 |
const char *initrd_filename, const char *cpu_model) |
740 |
{ |
741 |
CPUState *envs[MAX_CPUS]; |
742 |
unsigned int i; |
743 |
void *iommu, *espdma, *ledma, *nvram;
|
744 |
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
745 |
espdma_irq, ledma_irq; |
746 |
qemu_irq esp_reset; |
747 |
qemu_irq fdc_tc; |
748 |
qemu_irq *cpu_halt; |
749 |
unsigned long kernel_size; |
750 |
BlockDriverState *fd[MAX_FD]; |
751 |
void *fw_cfg;
|
752 |
DriveInfo *dinfo; |
753 |
|
754 |
/* init CPUs */
|
755 |
if (!cpu_model)
|
756 |
cpu_model = hwdef->default_cpu_model; |
757 |
|
758 |
for(i = 0; i < smp_cpus; i++) { |
759 |
envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
760 |
} |
761 |
|
762 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
763 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
764 |
|
765 |
|
766 |
/* set up devices */
|
767 |
ram_init(0, RAM_size, hwdef->max_mem);
|
768 |
|
769 |
prom_init(hwdef->slavio_base, bios_name); |
770 |
|
771 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
772 |
hwdef->intctl_base + 0x10000ULL,
|
773 |
cpu_irqs); |
774 |
|
775 |
for (i = 0; i < 32; i++) { |
776 |
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
777 |
} |
778 |
for (i = 0; i < MAX_CPUS; i++) { |
779 |
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
780 |
} |
781 |
|
782 |
if (hwdef->idreg_base) {
|
783 |
idreg_init(hwdef->idreg_base); |
784 |
} |
785 |
|
786 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
787 |
slavio_irq[30]);
|
788 |
|
789 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
790 |
iommu, &espdma_irq); |
791 |
|
792 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
793 |
slavio_irq[16], iommu, &ledma_irq);
|
794 |
|
795 |
if (graphic_depth != 8 && graphic_depth != 24) { |
796 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
797 |
exit (1);
|
798 |
} |
799 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
800 |
graphic_depth); |
801 |
|
802 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
803 |
|
804 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
805 |
|
806 |
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
807 |
|
808 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
809 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
810 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
811 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
812 |
escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
813 |
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
814 |
|
815 |
cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
816 |
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
817 |
slavio_irq[30], fdc_tc);
|
818 |
|
819 |
if (hwdef->apc_base) {
|
820 |
apc_init(hwdef->apc_base, cpu_halt[0]);
|
821 |
} |
822 |
|
823 |
if (hwdef->fd_base) {
|
824 |
/* there is zero or one floppy drive */
|
825 |
memset(fd, 0, sizeof(fd)); |
826 |
dinfo = drive_get(IF_FLOPPY, 0, 0); |
827 |
if (dinfo)
|
828 |
fd[0] = dinfo->bdrv;
|
829 |
|
830 |
sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
831 |
&fdc_tc); |
832 |
} |
833 |
|
834 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
835 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
836 |
exit(1);
|
837 |
} |
838 |
|
839 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
840 |
esp_init(hwdef->esp_base, 2,
|
841 |
espdma_memory_read, espdma_memory_write, |
842 |
espdma, espdma_irq, &esp_reset); |
843 |
|
844 |
|
845 |
if (hwdef->cs_base) {
|
846 |
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
847 |
slavio_irq[5]);
|
848 |
} |
849 |
|
850 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
851 |
RAM_size); |
852 |
|
853 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
854 |
boot_device, RAM_size, kernel_size, graphic_width, |
855 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
856 |
"Sun4m");
|
857 |
|
858 |
if (hwdef->ecc_base)
|
859 |
ecc_init(hwdef->ecc_base, slavio_irq[28],
|
860 |
hwdef->ecc_version); |
861 |
|
862 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
863 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
864 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
865 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
866 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
867 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
868 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
869 |
if (kernel_cmdline) {
|
870 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
871 |
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
872 |
} else {
|
873 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
874 |
} |
875 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
876 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
877 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
878 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
879 |
} |
880 |
|
881 |
enum {
|
882 |
ss2_id = 0,
|
883 |
ss5_id = 32,
|
884 |
vger_id, |
885 |
lx_id, |
886 |
ss4_id, |
887 |
scls_id, |
888 |
sbook_id, |
889 |
ss10_id = 64,
|
890 |
ss20_id, |
891 |
ss600mp_id, |
892 |
ss1000_id = 96,
|
893 |
ss2000_id, |
894 |
}; |
895 |
|
896 |
static const struct sun4m_hwdef sun4m_hwdefs[] = { |
897 |
/* SS-5 */
|
898 |
{ |
899 |
.iommu_base = 0x10000000,
|
900 |
.tcx_base = 0x50000000,
|
901 |
.cs_base = 0x6c000000,
|
902 |
.slavio_base = 0x70000000,
|
903 |
.ms_kb_base = 0x71000000,
|
904 |
.serial_base = 0x71100000,
|
905 |
.nvram_base = 0x71200000,
|
906 |
.fd_base = 0x71400000,
|
907 |
.counter_base = 0x71d00000,
|
908 |
.intctl_base = 0x71e00000,
|
909 |
.idreg_base = 0x78000000,
|
910 |
.dma_base = 0x78400000,
|
911 |
.esp_base = 0x78800000,
|
912 |
.le_base = 0x78c00000,
|
913 |
.apc_base = 0x6a000000,
|
914 |
.aux1_base = 0x71900000,
|
915 |
.aux2_base = 0x71910000,
|
916 |
.nvram_machine_id = 0x80,
|
917 |
.machine_id = ss5_id, |
918 |
.iommu_version = 0x05000000,
|
919 |
.max_mem = 0x10000000,
|
920 |
.default_cpu_model = "Fujitsu MB86904",
|
921 |
}, |
922 |
/* SS-10 */
|
923 |
{ |
924 |
.iommu_base = 0xfe0000000ULL,
|
925 |
.tcx_base = 0xe20000000ULL,
|
926 |
.slavio_base = 0xff0000000ULL,
|
927 |
.ms_kb_base = 0xff1000000ULL,
|
928 |
.serial_base = 0xff1100000ULL,
|
929 |
.nvram_base = 0xff1200000ULL,
|
930 |
.fd_base = 0xff1700000ULL,
|
931 |
.counter_base = 0xff1300000ULL,
|
932 |
.intctl_base = 0xff1400000ULL,
|
933 |
.idreg_base = 0xef0000000ULL,
|
934 |
.dma_base = 0xef0400000ULL,
|
935 |
.esp_base = 0xef0800000ULL,
|
936 |
.le_base = 0xef0c00000ULL,
|
937 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
938 |
.aux1_base = 0xff1800000ULL,
|
939 |
.aux2_base = 0xff1a01000ULL,
|
940 |
.ecc_base = 0xf00000000ULL,
|
941 |
.ecc_version = 0x10000000, // version 0, implementation 1 |
942 |
.nvram_machine_id = 0x72,
|
943 |
.machine_id = ss10_id, |
944 |
.iommu_version = 0x03000000,
|
945 |
.max_mem = 0xf00000000ULL,
|
946 |
.default_cpu_model = "TI SuperSparc II",
|
947 |
}, |
948 |
/* SS-600MP */
|
949 |
{ |
950 |
.iommu_base = 0xfe0000000ULL,
|
951 |
.tcx_base = 0xe20000000ULL,
|
952 |
.slavio_base = 0xff0000000ULL,
|
953 |
.ms_kb_base = 0xff1000000ULL,
|
954 |
.serial_base = 0xff1100000ULL,
|
955 |
.nvram_base = 0xff1200000ULL,
|
956 |
.counter_base = 0xff1300000ULL,
|
957 |
.intctl_base = 0xff1400000ULL,
|
958 |
.dma_base = 0xef0081000ULL,
|
959 |
.esp_base = 0xef0080000ULL,
|
960 |
.le_base = 0xef0060000ULL,
|
961 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
962 |
.aux1_base = 0xff1800000ULL,
|
963 |
.aux2_base = 0xff1a01000ULL, // XXX should not exist |
964 |
.ecc_base = 0xf00000000ULL,
|
965 |
.ecc_version = 0x00000000, // version 0, implementation 0 |
966 |
.nvram_machine_id = 0x71,
|
967 |
.machine_id = ss600mp_id, |
968 |
.iommu_version = 0x01000000,
|
969 |
.max_mem = 0xf00000000ULL,
|
970 |
.default_cpu_model = "TI SuperSparc II",
|
971 |
}, |
972 |
/* SS-20 */
|
973 |
{ |
974 |
.iommu_base = 0xfe0000000ULL,
|
975 |
.tcx_base = 0xe20000000ULL,
|
976 |
.slavio_base = 0xff0000000ULL,
|
977 |
.ms_kb_base = 0xff1000000ULL,
|
978 |
.serial_base = 0xff1100000ULL,
|
979 |
.nvram_base = 0xff1200000ULL,
|
980 |
.fd_base = 0xff1700000ULL,
|
981 |
.counter_base = 0xff1300000ULL,
|
982 |
.intctl_base = 0xff1400000ULL,
|
983 |
.idreg_base = 0xef0000000ULL,
|
984 |
.dma_base = 0xef0400000ULL,
|
985 |
.esp_base = 0xef0800000ULL,
|
986 |
.le_base = 0xef0c00000ULL,
|
987 |
.apc_base = 0xefa000000ULL, // XXX should not exist |
988 |
.aux1_base = 0xff1800000ULL,
|
989 |
.aux2_base = 0xff1a01000ULL,
|
990 |
.ecc_base = 0xf00000000ULL,
|
991 |
.ecc_version = 0x20000000, // version 0, implementation 2 |
992 |
.nvram_machine_id = 0x72,
|
993 |
.machine_id = ss20_id, |
994 |
.iommu_version = 0x13000000,
|
995 |
.max_mem = 0xf00000000ULL,
|
996 |
.default_cpu_model = "TI SuperSparc II",
|
997 |
}, |
998 |
/* Voyager */
|
999 |
{ |
1000 |
.iommu_base = 0x10000000,
|
1001 |
.tcx_base = 0x50000000,
|
1002 |
.slavio_base = 0x70000000,
|
1003 |
.ms_kb_base = 0x71000000,
|
1004 |
.serial_base = 0x71100000,
|
1005 |
.nvram_base = 0x71200000,
|
1006 |
.fd_base = 0x71400000,
|
1007 |
.counter_base = 0x71d00000,
|
1008 |
.intctl_base = 0x71e00000,
|
1009 |
.idreg_base = 0x78000000,
|
1010 |
.dma_base = 0x78400000,
|
1011 |
.esp_base = 0x78800000,
|
1012 |
.le_base = 0x78c00000,
|
1013 |
.apc_base = 0x71300000, // pmc |
1014 |
.aux1_base = 0x71900000,
|
1015 |
.aux2_base = 0x71910000,
|
1016 |
.nvram_machine_id = 0x80,
|
1017 |
.machine_id = vger_id, |
1018 |
.iommu_version = 0x05000000,
|
1019 |
.max_mem = 0x10000000,
|
1020 |
.default_cpu_model = "Fujitsu MB86904",
|
1021 |
}, |
1022 |
/* LX */
|
1023 |
{ |
1024 |
.iommu_base = 0x10000000,
|
1025 |
.tcx_base = 0x50000000,
|
1026 |
.slavio_base = 0x70000000,
|
1027 |
.ms_kb_base = 0x71000000,
|
1028 |
.serial_base = 0x71100000,
|
1029 |
.nvram_base = 0x71200000,
|
1030 |
.fd_base = 0x71400000,
|
1031 |
.counter_base = 0x71d00000,
|
1032 |
.intctl_base = 0x71e00000,
|
1033 |
.idreg_base = 0x78000000,
|
1034 |
.dma_base = 0x78400000,
|
1035 |
.esp_base = 0x78800000,
|
1036 |
.le_base = 0x78c00000,
|
1037 |
.aux1_base = 0x71900000,
|
1038 |
.aux2_base = 0x71910000,
|
1039 |
.nvram_machine_id = 0x80,
|
1040 |
.machine_id = lx_id, |
1041 |
.iommu_version = 0x04000000,
|
1042 |
.max_mem = 0x10000000,
|
1043 |
.default_cpu_model = "TI MicroSparc I",
|
1044 |
}, |
1045 |
/* SS-4 */
|
1046 |
{ |
1047 |
.iommu_base = 0x10000000,
|
1048 |
.tcx_base = 0x50000000,
|
1049 |
.cs_base = 0x6c000000,
|
1050 |
.slavio_base = 0x70000000,
|
1051 |
.ms_kb_base = 0x71000000,
|
1052 |
.serial_base = 0x71100000,
|
1053 |
.nvram_base = 0x71200000,
|
1054 |
.fd_base = 0x71400000,
|
1055 |
.counter_base = 0x71d00000,
|
1056 |
.intctl_base = 0x71e00000,
|
1057 |
.idreg_base = 0x78000000,
|
1058 |
.dma_base = 0x78400000,
|
1059 |
.esp_base = 0x78800000,
|
1060 |
.le_base = 0x78c00000,
|
1061 |
.apc_base = 0x6a000000,
|
1062 |
.aux1_base = 0x71900000,
|
1063 |
.aux2_base = 0x71910000,
|
1064 |
.nvram_machine_id = 0x80,
|
1065 |
.machine_id = ss4_id, |
1066 |
.iommu_version = 0x05000000,
|
1067 |
.max_mem = 0x10000000,
|
1068 |
.default_cpu_model = "Fujitsu MB86904",
|
1069 |
}, |
1070 |
/* SPARCClassic */
|
1071 |
{ |
1072 |
.iommu_base = 0x10000000,
|
1073 |
.tcx_base = 0x50000000,
|
1074 |
.slavio_base = 0x70000000,
|
1075 |
.ms_kb_base = 0x71000000,
|
1076 |
.serial_base = 0x71100000,
|
1077 |
.nvram_base = 0x71200000,
|
1078 |
.fd_base = 0x71400000,
|
1079 |
.counter_base = 0x71d00000,
|
1080 |
.intctl_base = 0x71e00000,
|
1081 |
.idreg_base = 0x78000000,
|
1082 |
.dma_base = 0x78400000,
|
1083 |
.esp_base = 0x78800000,
|
1084 |
.le_base = 0x78c00000,
|
1085 |
.apc_base = 0x6a000000,
|
1086 |
.aux1_base = 0x71900000,
|
1087 |
.aux2_base = 0x71910000,
|
1088 |
.nvram_machine_id = 0x80,
|
1089 |
.machine_id = scls_id, |
1090 |
.iommu_version = 0x05000000,
|
1091 |
.max_mem = 0x10000000,
|
1092 |
.default_cpu_model = "TI MicroSparc I",
|
1093 |
}, |
1094 |
/* SPARCbook */
|
1095 |
{ |
1096 |
.iommu_base = 0x10000000,
|
1097 |
.tcx_base = 0x50000000, // XXX |
1098 |
.slavio_base = 0x70000000,
|
1099 |
.ms_kb_base = 0x71000000,
|
1100 |
.serial_base = 0x71100000,
|
1101 |
.nvram_base = 0x71200000,
|
1102 |
.fd_base = 0x71400000,
|
1103 |
.counter_base = 0x71d00000,
|
1104 |
.intctl_base = 0x71e00000,
|
1105 |
.idreg_base = 0x78000000,
|
1106 |
.dma_base = 0x78400000,
|
1107 |
.esp_base = 0x78800000,
|
1108 |
.le_base = 0x78c00000,
|
1109 |
.apc_base = 0x6a000000,
|
1110 |
.aux1_base = 0x71900000,
|
1111 |
.aux2_base = 0x71910000,
|
1112 |
.nvram_machine_id = 0x80,
|
1113 |
.machine_id = sbook_id, |
1114 |
.iommu_version = 0x05000000,
|
1115 |
.max_mem = 0x10000000,
|
1116 |
.default_cpu_model = "TI MicroSparc I",
|
1117 |
}, |
1118 |
}; |
1119 |
|
1120 |
/* SPARCstation 5 hardware initialisation */
|
1121 |
static void ss5_init(ram_addr_t RAM_size, |
1122 |
const char *boot_device, |
1123 |
const char *kernel_filename, const char *kernel_cmdline, |
1124 |
const char *initrd_filename, const char *cpu_model) |
1125 |
{ |
1126 |
sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1127 |
kernel_cmdline, initrd_filename, cpu_model); |
1128 |
} |
1129 |
|
1130 |
/* SPARCstation 10 hardware initialisation */
|
1131 |
static void ss10_init(ram_addr_t RAM_size, |
1132 |
const char *boot_device, |
1133 |
const char *kernel_filename, const char *kernel_cmdline, |
1134 |
const char *initrd_filename, const char *cpu_model) |
1135 |
{ |
1136 |
sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1137 |
kernel_cmdline, initrd_filename, cpu_model); |
1138 |
} |
1139 |
|
1140 |
/* SPARCserver 600MP hardware initialisation */
|
1141 |
static void ss600mp_init(ram_addr_t RAM_size, |
1142 |
const char *boot_device, |
1143 |
const char *kernel_filename, |
1144 |
const char *kernel_cmdline, |
1145 |
const char *initrd_filename, const char *cpu_model) |
1146 |
{ |
1147 |
sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1148 |
kernel_cmdline, initrd_filename, cpu_model); |
1149 |
} |
1150 |
|
1151 |
/* SPARCstation 20 hardware initialisation */
|
1152 |
static void ss20_init(ram_addr_t RAM_size, |
1153 |
const char *boot_device, |
1154 |
const char *kernel_filename, const char *kernel_cmdline, |
1155 |
const char *initrd_filename, const char *cpu_model) |
1156 |
{ |
1157 |
sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1158 |
kernel_cmdline, initrd_filename, cpu_model); |
1159 |
} |
1160 |
|
1161 |
/* SPARCstation Voyager hardware initialisation */
|
1162 |
static void vger_init(ram_addr_t RAM_size, |
1163 |
const char *boot_device, |
1164 |
const char *kernel_filename, const char *kernel_cmdline, |
1165 |
const char *initrd_filename, const char *cpu_model) |
1166 |
{ |
1167 |
sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1168 |
kernel_cmdline, initrd_filename, cpu_model); |
1169 |
} |
1170 |
|
1171 |
/* SPARCstation LX hardware initialisation */
|
1172 |
static void ss_lx_init(ram_addr_t RAM_size, |
1173 |
const char *boot_device, |
1174 |
const char *kernel_filename, const char *kernel_cmdline, |
1175 |
const char *initrd_filename, const char *cpu_model) |
1176 |
{ |
1177 |
sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1178 |
kernel_cmdline, initrd_filename, cpu_model); |
1179 |
} |
1180 |
|
1181 |
/* SPARCstation 4 hardware initialisation */
|
1182 |
static void ss4_init(ram_addr_t RAM_size, |
1183 |
const char *boot_device, |
1184 |
const char *kernel_filename, const char *kernel_cmdline, |
1185 |
const char *initrd_filename, const char *cpu_model) |
1186 |
{ |
1187 |
sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1188 |
kernel_cmdline, initrd_filename, cpu_model); |
1189 |
} |
1190 |
|
1191 |
/* SPARCClassic hardware initialisation */
|
1192 |
static void scls_init(ram_addr_t RAM_size, |
1193 |
const char *boot_device, |
1194 |
const char *kernel_filename, const char *kernel_cmdline, |
1195 |
const char *initrd_filename, const char *cpu_model) |
1196 |
{ |
1197 |
sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1198 |
kernel_cmdline, initrd_filename, cpu_model); |
1199 |
} |
1200 |
|
1201 |
/* SPARCbook hardware initialisation */
|
1202 |
static void sbook_init(ram_addr_t RAM_size, |
1203 |
const char *boot_device, |
1204 |
const char *kernel_filename, const char *kernel_cmdline, |
1205 |
const char *initrd_filename, const char *cpu_model) |
1206 |
{ |
1207 |
sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1208 |
kernel_cmdline, initrd_filename, cpu_model); |
1209 |
} |
1210 |
|
1211 |
static QEMUMachine ss5_machine = {
|
1212 |
.name = "SS-5",
|
1213 |
.desc = "Sun4m platform, SPARCstation 5",
|
1214 |
.init = ss5_init, |
1215 |
.use_scsi = 1,
|
1216 |
.is_default = 1,
|
1217 |
}; |
1218 |
|
1219 |
static QEMUMachine ss10_machine = {
|
1220 |
.name = "SS-10",
|
1221 |
.desc = "Sun4m platform, SPARCstation 10",
|
1222 |
.init = ss10_init, |
1223 |
.use_scsi = 1,
|
1224 |
.max_cpus = 4,
|
1225 |
}; |
1226 |
|
1227 |
static QEMUMachine ss600mp_machine = {
|
1228 |
.name = "SS-600MP",
|
1229 |
.desc = "Sun4m platform, SPARCserver 600MP",
|
1230 |
.init = ss600mp_init, |
1231 |
.use_scsi = 1,
|
1232 |
.max_cpus = 4,
|
1233 |
}; |
1234 |
|
1235 |
static QEMUMachine ss20_machine = {
|
1236 |
.name = "SS-20",
|
1237 |
.desc = "Sun4m platform, SPARCstation 20",
|
1238 |
.init = ss20_init, |
1239 |
.use_scsi = 1,
|
1240 |
.max_cpus = 4,
|
1241 |
}; |
1242 |
|
1243 |
static QEMUMachine voyager_machine = {
|
1244 |
.name = "Voyager",
|
1245 |
.desc = "Sun4m platform, SPARCstation Voyager",
|
1246 |
.init = vger_init, |
1247 |
.use_scsi = 1,
|
1248 |
}; |
1249 |
|
1250 |
static QEMUMachine ss_lx_machine = {
|
1251 |
.name = "LX",
|
1252 |
.desc = "Sun4m platform, SPARCstation LX",
|
1253 |
.init = ss_lx_init, |
1254 |
.use_scsi = 1,
|
1255 |
}; |
1256 |
|
1257 |
static QEMUMachine ss4_machine = {
|
1258 |
.name = "SS-4",
|
1259 |
.desc = "Sun4m platform, SPARCstation 4",
|
1260 |
.init = ss4_init, |
1261 |
.use_scsi = 1,
|
1262 |
}; |
1263 |
|
1264 |
static QEMUMachine scls_machine = {
|
1265 |
.name = "SPARCClassic",
|
1266 |
.desc = "Sun4m platform, SPARCClassic",
|
1267 |
.init = scls_init, |
1268 |
.use_scsi = 1,
|
1269 |
}; |
1270 |
|
1271 |
static QEMUMachine sbook_machine = {
|
1272 |
.name = "SPARCbook",
|
1273 |
.desc = "Sun4m platform, SPARCbook",
|
1274 |
.init = sbook_init, |
1275 |
.use_scsi = 1,
|
1276 |
}; |
1277 |
|
1278 |
static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1279 |
/* SS-1000 */
|
1280 |
{ |
1281 |
.iounit_bases = { |
1282 |
0xfe0200000ULL,
|
1283 |
0xfe1200000ULL,
|
1284 |
0xfe2200000ULL,
|
1285 |
0xfe3200000ULL,
|
1286 |
-1,
|
1287 |
}, |
1288 |
.tcx_base = 0x820000000ULL,
|
1289 |
.slavio_base = 0xf00000000ULL,
|
1290 |
.ms_kb_base = 0xf00240000ULL,
|
1291 |
.serial_base = 0xf00200000ULL,
|
1292 |
.nvram_base = 0xf00280000ULL,
|
1293 |
.counter_base = 0xf00300000ULL,
|
1294 |
.espdma_base = 0x800081000ULL,
|
1295 |
.esp_base = 0x800080000ULL,
|
1296 |
.ledma_base = 0x800040000ULL,
|
1297 |
.le_base = 0x800060000ULL,
|
1298 |
.sbi_base = 0xf02800000ULL,
|
1299 |
.nvram_machine_id = 0x80,
|
1300 |
.machine_id = ss1000_id, |
1301 |
.iounit_version = 0x03000000,
|
1302 |
.max_mem = 0xf00000000ULL,
|
1303 |
.default_cpu_model = "TI SuperSparc II",
|
1304 |
}, |
1305 |
/* SS-2000 */
|
1306 |
{ |
1307 |
.iounit_bases = { |
1308 |
0xfe0200000ULL,
|
1309 |
0xfe1200000ULL,
|
1310 |
0xfe2200000ULL,
|
1311 |
0xfe3200000ULL,
|
1312 |
0xfe4200000ULL,
|
1313 |
}, |
1314 |
.tcx_base = 0x820000000ULL,
|
1315 |
.slavio_base = 0xf00000000ULL,
|
1316 |
.ms_kb_base = 0xf00240000ULL,
|
1317 |
.serial_base = 0xf00200000ULL,
|
1318 |
.nvram_base = 0xf00280000ULL,
|
1319 |
.counter_base = 0xf00300000ULL,
|
1320 |
.espdma_base = 0x800081000ULL,
|
1321 |
.esp_base = 0x800080000ULL,
|
1322 |
.ledma_base = 0x800040000ULL,
|
1323 |
.le_base = 0x800060000ULL,
|
1324 |
.sbi_base = 0xf02800000ULL,
|
1325 |
.nvram_machine_id = 0x80,
|
1326 |
.machine_id = ss2000_id, |
1327 |
.iounit_version = 0x03000000,
|
1328 |
.max_mem = 0xf00000000ULL,
|
1329 |
.default_cpu_model = "TI SuperSparc II",
|
1330 |
}, |
1331 |
}; |
1332 |
|
1333 |
static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
|
1334 |
{ |
1335 |
DeviceState *dev; |
1336 |
SysBusDevice *s; |
1337 |
unsigned int i; |
1338 |
|
1339 |
dev = qdev_create(NULL, "sbi"); |
1340 |
qdev_init(dev); |
1341 |
|
1342 |
s = sysbus_from_qdev(dev); |
1343 |
|
1344 |
for (i = 0; i < MAX_CPUS; i++) { |
1345 |
sysbus_connect_irq(s, i, *parent_irq[i]); |
1346 |
} |
1347 |
|
1348 |
sysbus_mmio_map(s, 0, addr);
|
1349 |
|
1350 |
return dev;
|
1351 |
} |
1352 |
|
1353 |
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1354 |
const char *boot_device, |
1355 |
const char *kernel_filename, |
1356 |
const char *kernel_cmdline, |
1357 |
const char *initrd_filename, const char *cpu_model) |
1358 |
{ |
1359 |
CPUState *envs[MAX_CPUS]; |
1360 |
unsigned int i; |
1361 |
void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1362 |
qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1363 |
espdma_irq, ledma_irq; |
1364 |
qemu_irq esp_reset; |
1365 |
unsigned long kernel_size; |
1366 |
void *fw_cfg;
|
1367 |
DeviceState *dev; |
1368 |
|
1369 |
/* init CPUs */
|
1370 |
if (!cpu_model)
|
1371 |
cpu_model = hwdef->default_cpu_model; |
1372 |
|
1373 |
for(i = 0; i < smp_cpus; i++) { |
1374 |
envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1375 |
} |
1376 |
|
1377 |
for (i = smp_cpus; i < MAX_CPUS; i++)
|
1378 |
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1379 |
|
1380 |
/* set up devices */
|
1381 |
ram_init(0, RAM_size, hwdef->max_mem);
|
1382 |
|
1383 |
prom_init(hwdef->slavio_base, bios_name); |
1384 |
|
1385 |
dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1386 |
|
1387 |
for (i = 0; i < 32; i++) { |
1388 |
sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1389 |
} |
1390 |
for (i = 0; i < MAX_CPUS; i++) { |
1391 |
sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1392 |
} |
1393 |
|
1394 |
for (i = 0; i < MAX_IOUNITS; i++) |
1395 |
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1396 |
iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1397 |
hwdef->iounit_version, |
1398 |
sbi_irq[0]);
|
1399 |
|
1400 |
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1401 |
iounits[0], &espdma_irq);
|
1402 |
|
1403 |
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1404 |
iounits[0], &ledma_irq);
|
1405 |
|
1406 |
if (graphic_depth != 8 && graphic_depth != 24) { |
1407 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1408 |
exit (1);
|
1409 |
} |
1410 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1411 |
graphic_depth); |
1412 |
|
1413 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1414 |
|
1415 |
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1416 |
|
1417 |
slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1418 |
|
1419 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1420 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1421 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1422 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1423 |
escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1424 |
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1425 |
|
1426 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
1427 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
1428 |
exit(1);
|
1429 |
} |
1430 |
|
1431 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
1432 |
esp_init(hwdef->esp_base, 2,
|
1433 |
espdma_memory_read, espdma_memory_write, |
1434 |
espdma, espdma_irq, &esp_reset); |
1435 |
|
1436 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1437 |
RAM_size); |
1438 |
|
1439 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1440 |
boot_device, RAM_size, kernel_size, graphic_width, |
1441 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1442 |
"Sun4d");
|
1443 |
|
1444 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1445 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1446 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1447 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1448 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1449 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1450 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1451 |
if (kernel_cmdline) {
|
1452 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1453 |
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1454 |
} else {
|
1455 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1456 |
} |
1457 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1458 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1459 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1460 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1461 |
} |
1462 |
|
1463 |
/* SPARCserver 1000 hardware initialisation */
|
1464 |
static void ss1000_init(ram_addr_t RAM_size, |
1465 |
const char *boot_device, |
1466 |
const char *kernel_filename, const char *kernel_cmdline, |
1467 |
const char *initrd_filename, const char *cpu_model) |
1468 |
{ |
1469 |
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1470 |
kernel_cmdline, initrd_filename, cpu_model); |
1471 |
} |
1472 |
|
1473 |
/* SPARCcenter 2000 hardware initialisation */
|
1474 |
static void ss2000_init(ram_addr_t RAM_size, |
1475 |
const char *boot_device, |
1476 |
const char *kernel_filename, const char *kernel_cmdline, |
1477 |
const char *initrd_filename, const char *cpu_model) |
1478 |
{ |
1479 |
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1480 |
kernel_cmdline, initrd_filename, cpu_model); |
1481 |
} |
1482 |
|
1483 |
static QEMUMachine ss1000_machine = {
|
1484 |
.name = "SS-1000",
|
1485 |
.desc = "Sun4d platform, SPARCserver 1000",
|
1486 |
.init = ss1000_init, |
1487 |
.use_scsi = 1,
|
1488 |
.max_cpus = 8,
|
1489 |
}; |
1490 |
|
1491 |
static QEMUMachine ss2000_machine = {
|
1492 |
.name = "SS-2000",
|
1493 |
.desc = "Sun4d platform, SPARCcenter 2000",
|
1494 |
.init = ss2000_init, |
1495 |
.use_scsi = 1,
|
1496 |
.max_cpus = 20,
|
1497 |
}; |
1498 |
|
1499 |
static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1500 |
/* SS-2 */
|
1501 |
{ |
1502 |
.iommu_base = 0xf8000000,
|
1503 |
.tcx_base = 0xfe000000,
|
1504 |
.slavio_base = 0xf6000000,
|
1505 |
.intctl_base = 0xf5000000,
|
1506 |
.counter_base = 0xf3000000,
|
1507 |
.ms_kb_base = 0xf0000000,
|
1508 |
.serial_base = 0xf1000000,
|
1509 |
.nvram_base = 0xf2000000,
|
1510 |
.fd_base = 0xf7200000,
|
1511 |
.dma_base = 0xf8400000,
|
1512 |
.esp_base = 0xf8800000,
|
1513 |
.le_base = 0xf8c00000,
|
1514 |
.aux1_base = 0xf7400003,
|
1515 |
.nvram_machine_id = 0x55,
|
1516 |
.machine_id = ss2_id, |
1517 |
.max_mem = 0x10000000,
|
1518 |
.default_cpu_model = "Cypress CY7C601",
|
1519 |
}, |
1520 |
}; |
1521 |
|
1522 |
static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
|
1523 |
qemu_irq *parent_irq) |
1524 |
{ |
1525 |
DeviceState *dev; |
1526 |
SysBusDevice *s; |
1527 |
unsigned int i; |
1528 |
|
1529 |
dev = qdev_create(NULL, "sun4c_intctl"); |
1530 |
qdev_init(dev); |
1531 |
|
1532 |
s = sysbus_from_qdev(dev); |
1533 |
|
1534 |
for (i = 0; i < MAX_PILS; i++) { |
1535 |
sysbus_connect_irq(s, i, parent_irq[i]); |
1536 |
} |
1537 |
sysbus_mmio_map(s, 0, addr);
|
1538 |
|
1539 |
return dev;
|
1540 |
} |
1541 |
|
1542 |
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1543 |
const char *boot_device, |
1544 |
const char *kernel_filename, |
1545 |
const char *kernel_cmdline, |
1546 |
const char *initrd_filename, const char *cpu_model) |
1547 |
{ |
1548 |
CPUState *env; |
1549 |
void *iommu, *espdma, *ledma, *nvram;
|
1550 |
qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1551 |
qemu_irq esp_reset; |
1552 |
qemu_irq fdc_tc; |
1553 |
unsigned long kernel_size; |
1554 |
BlockDriverState *fd[MAX_FD]; |
1555 |
void *fw_cfg;
|
1556 |
DeviceState *dev; |
1557 |
unsigned int i; |
1558 |
DriveInfo *dinfo; |
1559 |
|
1560 |
/* init CPU */
|
1561 |
if (!cpu_model)
|
1562 |
cpu_model = hwdef->default_cpu_model; |
1563 |
|
1564 |
env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1565 |
|
1566 |
/* set up devices */
|
1567 |
ram_init(0, RAM_size, hwdef->max_mem);
|
1568 |
|
1569 |
prom_init(hwdef->slavio_base, bios_name); |
1570 |
|
1571 |
dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1572 |
|
1573 |
for (i = 0; i < 8; i++) { |
1574 |
slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1575 |
} |
1576 |
|
1577 |
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1578 |
slavio_irq[1]);
|
1579 |
|
1580 |
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1581 |
iommu, &espdma_irq); |
1582 |
|
1583 |
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1584 |
slavio_irq[3], iommu, &ledma_irq);
|
1585 |
|
1586 |
if (graphic_depth != 8 && graphic_depth != 24) { |
1587 |
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1588 |
exit (1);
|
1589 |
} |
1590 |
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1591 |
graphic_depth); |
1592 |
|
1593 |
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1594 |
|
1595 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1596 |
|
1597 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1598 |
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1599 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1600 |
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1601 |
escc_init(hwdef->serial_base, slavio_irq[1],
|
1602 |
slavio_irq[1], serial_hds[0], serial_hds[1], |
1603 |
ESCC_CLOCK, 1);
|
1604 |
|
1605 |
slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1606 |
|
1607 |
if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1608 |
/* there is zero or one floppy drive */
|
1609 |
memset(fd, 0, sizeof(fd)); |
1610 |
dinfo = drive_get(IF_FLOPPY, 0, 0); |
1611 |
if (dinfo)
|
1612 |
fd[0] = dinfo->bdrv;
|
1613 |
|
1614 |
sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1615 |
&fdc_tc); |
1616 |
} |
1617 |
|
1618 |
if (drive_get_max_bus(IF_SCSI) > 0) { |
1619 |
fprintf(stderr, "qemu: too many SCSI bus\n");
|
1620 |
exit(1);
|
1621 |
} |
1622 |
|
1623 |
esp_reset = qdev_get_gpio_in(espdma, 0);
|
1624 |
esp_init(hwdef->esp_base, 2,
|
1625 |
espdma_memory_read, espdma_memory_write, |
1626 |
espdma, espdma_irq, &esp_reset); |
1627 |
|
1628 |
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1629 |
RAM_size); |
1630 |
|
1631 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1632 |
boot_device, RAM_size, kernel_size, graphic_width, |
1633 |
graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1634 |
"Sun4c");
|
1635 |
|
1636 |
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1637 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1638 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1639 |
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1640 |
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1641 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1642 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1643 |
if (kernel_cmdline) {
|
1644 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1645 |
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1646 |
} else {
|
1647 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1648 |
} |
1649 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1650 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1651 |
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1652 |
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1653 |
} |
1654 |
|
1655 |
/* SPARCstation 2 hardware initialisation */
|
1656 |
static void ss2_init(ram_addr_t RAM_size, |
1657 |
const char *boot_device, |
1658 |
const char *kernel_filename, const char *kernel_cmdline, |
1659 |
const char *initrd_filename, const char *cpu_model) |
1660 |
{ |
1661 |
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1662 |
kernel_cmdline, initrd_filename, cpu_model); |
1663 |
} |
1664 |
|
1665 |
static QEMUMachine ss2_machine = {
|
1666 |
.name = "SS-2",
|
1667 |
.desc = "Sun4c platform, SPARCstation 2",
|
1668 |
.init = ss2_init, |
1669 |
.use_scsi = 1,
|
1670 |
}; |
1671 |
|
1672 |
static void ss2_machine_init(void) |
1673 |
{ |
1674 |
qemu_register_machine(&ss5_machine); |
1675 |
qemu_register_machine(&ss10_machine); |
1676 |
qemu_register_machine(&ss600mp_machine); |
1677 |
qemu_register_machine(&ss20_machine); |
1678 |
qemu_register_machine(&voyager_machine); |
1679 |
qemu_register_machine(&ss_lx_machine); |
1680 |
qemu_register_machine(&ss4_machine); |
1681 |
qemu_register_machine(&scls_machine); |
1682 |
qemu_register_machine(&sbook_machine); |
1683 |
qemu_register_machine(&ss1000_machine); |
1684 |
qemu_register_machine(&ss2000_machine); |
1685 |
qemu_register_machine(&ss2_machine); |
1686 |
} |
1687 |
|
1688 |
machine_init(ss2_machine_init); |