root / target-mips / op_helper.c @ 273af660
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 2d0e944d | ths | #include <stdlib.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 05f778c8 | ths | #include "host-utils.h" |
24 | 05f778c8 | ths | |
25 | 273af660 | ths | #ifdef __s390__
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26 | 273af660 | ths | # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) |
27 | 273af660 | ths | #else
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28 | 273af660 | ths | # define GETPC() (__builtin_return_address(0)) |
29 | 273af660 | ths | #endif
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30 | 4ad40f36 | bellard | |
31 | 6af0bf9c | bellard | /*****************************************************************************/
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32 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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33 | 6af0bf9c | bellard | |
34 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
35 | 6af0bf9c | bellard | { |
36 | 6af0bf9c | bellard | #if 1 |
37 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
38 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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39 | 6af0bf9c | bellard | #endif
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40 | 6af0bf9c | bellard | env->exception_index = exception; |
41 | 6af0bf9c | bellard | env->error_code = error_code; |
42 | 6af0bf9c | bellard | T0 = 0;
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43 | 6af0bf9c | bellard | cpu_loop_exit(); |
44 | 6af0bf9c | bellard | } |
45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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47 | 6af0bf9c | bellard | { |
48 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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49 | 6af0bf9c | bellard | } |
50 | 6af0bf9c | bellard | |
51 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
52 | 4ad40f36 | bellard | { |
53 | 4ad40f36 | bellard | TranslationBlock *tb; |
54 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
55 | 4ad40f36 | bellard | |
56 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
57 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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58 | 4ad40f36 | bellard | } |
59 | 4ad40f36 | bellard | |
60 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code) |
61 | 4ad40f36 | bellard | { |
62 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
63 | e397ee33 | ths | do_raise_exception_err (exception, error_code); |
64 | e397ee33 | ths | } |
65 | e397ee33 | ths | |
66 | e397ee33 | ths | void do_raise_exception_direct (uint32_t exception)
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67 | e397ee33 | ths | { |
68 | e397ee33 | ths | do_raise_exception_direct_err (exception, 0);
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69 | 4ad40f36 | bellard | } |
70 | 4ad40f36 | bellard | |
71 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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72 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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73 | c570fd16 | ths | /* Those might call libgcc functions. */
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74 | c570fd16 | ths | void do_dsll (void) |
75 | c570fd16 | ths | { |
76 | c570fd16 | ths | T0 = T0 << T1; |
77 | c570fd16 | ths | } |
78 | c570fd16 | ths | |
79 | c570fd16 | ths | void do_dsll32 (void) |
80 | c570fd16 | ths | { |
81 | c570fd16 | ths | T0 = T0 << (T1 + 32);
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82 | c570fd16 | ths | } |
83 | c570fd16 | ths | |
84 | c570fd16 | ths | void do_dsra (void) |
85 | c570fd16 | ths | { |
86 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
87 | c570fd16 | ths | } |
88 | c570fd16 | ths | |
89 | c570fd16 | ths | void do_dsra32 (void) |
90 | c570fd16 | ths | { |
91 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
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92 | c570fd16 | ths | } |
93 | c570fd16 | ths | |
94 | c570fd16 | ths | void do_dsrl (void) |
95 | c570fd16 | ths | { |
96 | c570fd16 | ths | T0 = T0 >> T1; |
97 | c570fd16 | ths | } |
98 | c570fd16 | ths | |
99 | c570fd16 | ths | void do_dsrl32 (void) |
100 | c570fd16 | ths | { |
101 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
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102 | c570fd16 | ths | } |
103 | c570fd16 | ths | |
104 | c570fd16 | ths | void do_drotr (void) |
105 | c570fd16 | ths | { |
106 | c570fd16 | ths | target_ulong tmp; |
107 | c570fd16 | ths | |
108 | c570fd16 | ths | if (T1) {
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109 | c570fd16 | ths | tmp = T0 << (0x40 - T1);
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110 | c570fd16 | ths | T0 = (T0 >> T1) | tmp; |
111 | 5a63bcb2 | ths | } |
112 | c570fd16 | ths | } |
113 | c570fd16 | ths | |
114 | c570fd16 | ths | void do_drotr32 (void) |
115 | c570fd16 | ths | { |
116 | c570fd16 | ths | target_ulong tmp; |
117 | c570fd16 | ths | |
118 | c570fd16 | ths | if (T1) {
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119 | c570fd16 | ths | tmp = T0 << (0x40 - (32 + T1)); |
120 | c570fd16 | ths | T0 = (T0 >> (32 + T1)) | tmp;
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121 | 5a63bcb2 | ths | } |
122 | c570fd16 | ths | } |
123 | c570fd16 | ths | |
124 | c570fd16 | ths | void do_dsllv (void) |
125 | c570fd16 | ths | { |
126 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
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127 | c570fd16 | ths | } |
128 | c570fd16 | ths | |
129 | c570fd16 | ths | void do_dsrav (void) |
130 | c570fd16 | ths | { |
131 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
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132 | c570fd16 | ths | } |
133 | c570fd16 | ths | |
134 | c570fd16 | ths | void do_dsrlv (void) |
135 | c570fd16 | ths | { |
136 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
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137 | c570fd16 | ths | } |
138 | c570fd16 | ths | |
139 | c570fd16 | ths | void do_drotrv (void) |
140 | c570fd16 | ths | { |
141 | c570fd16 | ths | target_ulong tmp; |
142 | c570fd16 | ths | |
143 | c570fd16 | ths | T0 &= 0x3F;
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144 | c570fd16 | ths | if (T0) {
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145 | c570fd16 | ths | tmp = T1 << (0x40 - T0);
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146 | c570fd16 | ths | T0 = (T1 >> T0) | tmp; |
147 | c570fd16 | ths | } else
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148 | c570fd16 | ths | T0 = T1; |
149 | c570fd16 | ths | } |
150 | 05f778c8 | ths | |
151 | 05f778c8 | ths | void do_dclo (void) |
152 | 05f778c8 | ths | { |
153 | 05f778c8 | ths | T0 = clo64(T0); |
154 | 05f778c8 | ths | } |
155 | 05f778c8 | ths | |
156 | 05f778c8 | ths | void do_dclz (void) |
157 | 05f778c8 | ths | { |
158 | 05f778c8 | ths | T0 = clz64(T0); |
159 | 05f778c8 | ths | } |
160 | 05f778c8 | ths | |
161 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
162 | 540635ba | ths | #endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ |
163 | c570fd16 | ths | |
164 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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165 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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166 | aa343735 | ths | static always_inline uint64_t get_HILO (void) |
167 | 6af0bf9c | bellard | { |
168 | ead9360e | ths | return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc]; |
169 | 6af0bf9c | bellard | } |
170 | 6af0bf9c | bellard | |
171 | aa343735 | ths | static always_inline void set_HILO (uint64_t HILO) |
172 | 6af0bf9c | bellard | { |
173 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)HILO;
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174 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
175 | 6af0bf9c | bellard | } |
176 | 6af0bf9c | bellard | |
177 | 6af0bf9c | bellard | void do_mult (void) |
178 | 6af0bf9c | bellard | { |
179 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
180 | 6af0bf9c | bellard | } |
181 | 6af0bf9c | bellard | |
182 | 6af0bf9c | bellard | void do_multu (void) |
183 | 6af0bf9c | bellard | { |
184 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
185 | 6af0bf9c | bellard | } |
186 | 6af0bf9c | bellard | |
187 | 6af0bf9c | bellard | void do_madd (void) |
188 | 6af0bf9c | bellard | { |
189 | 6af0bf9c | bellard | int64_t tmp; |
190 | 6af0bf9c | bellard | |
191 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
192 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
193 | 6af0bf9c | bellard | } |
194 | 6af0bf9c | bellard | |
195 | 6af0bf9c | bellard | void do_maddu (void) |
196 | 6af0bf9c | bellard | { |
197 | 6af0bf9c | bellard | uint64_t tmp; |
198 | 6af0bf9c | bellard | |
199 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
200 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
201 | 6af0bf9c | bellard | } |
202 | 6af0bf9c | bellard | |
203 | 6af0bf9c | bellard | void do_msub (void) |
204 | 6af0bf9c | bellard | { |
205 | 6af0bf9c | bellard | int64_t tmp; |
206 | 6af0bf9c | bellard | |
207 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
208 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
209 | 6af0bf9c | bellard | } |
210 | 6af0bf9c | bellard | |
211 | 6af0bf9c | bellard | void do_msubu (void) |
212 | 6af0bf9c | bellard | { |
213 | 6af0bf9c | bellard | uint64_t tmp; |
214 | 6af0bf9c | bellard | |
215 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
216 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
217 | 6af0bf9c | bellard | } |
218 | 6af0bf9c | bellard | #endif
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219 | 6af0bf9c | bellard | |
220 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
221 | 80c27194 | ths | void do_div (void) |
222 | 80c27194 | ths | { |
223 | 80c27194 | ths | /* 64bit datatypes because we may see overflow/underflow. */
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224 | 80c27194 | ths | if (T1 != 0) { |
225 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
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226 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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227 | 80c27194 | ths | } |
228 | 80c27194 | ths | } |
229 | 80c27194 | ths | #endif
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230 | 80c27194 | ths | |
231 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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232 | c570fd16 | ths | void do_ddiv (void) |
233 | c570fd16 | ths | { |
234 | c570fd16 | ths | if (T1 != 0) { |
235 | 2d0e944d | ths | lldiv_t res = lldiv((int64_t)T0, (int64_t)T1); |
236 | ead9360e | ths | env->LO[0][env->current_tc] = res.quot;
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237 | ead9360e | ths | env->HI[0][env->current_tc] = res.rem;
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238 | c570fd16 | ths | } |
239 | c570fd16 | ths | } |
240 | c570fd16 | ths | |
241 | 12a4b2aa | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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242 | c570fd16 | ths | void do_ddivu (void) |
243 | c570fd16 | ths | { |
244 | c570fd16 | ths | if (T1 != 0) { |
245 | ead9360e | ths | env->LO[0][env->current_tc] = T0 / T1;
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246 | ead9360e | ths | env->HI[0][env->current_tc] = T0 % T1;
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247 | c570fd16 | ths | } |
248 | c570fd16 | ths | } |
249 | c570fd16 | ths | #endif
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250 | 540635ba | ths | #endif /* TARGET_MIPSN32 || TARGET_MIPS64 */ |
251 | c570fd16 | ths | |
252 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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253 | 873eb012 | ths | void do_mfc0_random (void) |
254 | 048f6b4d | bellard | { |
255 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
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256 | 048f6b4d | bellard | } |
257 | 873eb012 | ths | |
258 | 873eb012 | ths | void do_mfc0_count (void) |
259 | 873eb012 | ths | { |
260 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
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261 | 873eb012 | ths | } |
262 | 873eb012 | ths | |
263 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
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264 | 048f6b4d | bellard | { |
265 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
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266 | 8c0fdd85 | ths | } |
267 | 8c0fdd85 | ths | |
268 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
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269 | 8c0fdd85 | ths | { |
270 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
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271 | 8c0fdd85 | ths | } |
272 | 8c0fdd85 | ths | |
273 | 42532189 | ths | void cpu_mips_start_count(CPUState *env)
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274 | 42532189 | ths | { |
275 | 42532189 | ths | cpu_abort(env, "start count\n");
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276 | 42532189 | ths | } |
277 | 42532189 | ths | |
278 | 42532189 | ths | void cpu_mips_stop_count(CPUState *env)
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279 | 42532189 | ths | { |
280 | 42532189 | ths | cpu_abort(env, "stop count\n");
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281 | 42532189 | ths | } |
282 | 42532189 | ths | |
283 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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284 | 4de9b249 | ths | { |
285 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
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286 | 4de9b249 | ths | } |
287 | 4de9b249 | ths | |
288 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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289 | 8c0fdd85 | ths | { |
290 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
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291 | 8c0fdd85 | ths | } |
292 | 8c0fdd85 | ths | |
293 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
294 | 8c0fdd85 | ths | { |
295 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
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296 | 048f6b4d | bellard | } |
297 | 048f6b4d | bellard | |
298 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
299 | 8c0fdd85 | ths | { |
300 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
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301 | 8c0fdd85 | ths | } |
302 | 8c0fdd85 | ths | |
303 | 048f6b4d | bellard | #else
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304 | 048f6b4d | bellard | |
305 | 6af0bf9c | bellard | /* CP0 helpers */
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306 | 873eb012 | ths | void do_mfc0_random (void) |
307 | 6af0bf9c | bellard | { |
308 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
309 | 873eb012 | ths | } |
310 | 6af0bf9c | bellard | |
311 | 873eb012 | ths | void do_mfc0_count (void) |
312 | 873eb012 | ths | { |
313 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
314 | 6af0bf9c | bellard | } |
315 | 6af0bf9c | bellard | |
316 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
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317 | 6af0bf9c | bellard | { |
318 | f41c52f1 | ths | fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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319 | f41c52f1 | ths | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
320 | f41c52f1 | ths | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
321 | f41c52f1 | ths | env->CP0_Cause); |
322 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
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323 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
324 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
325 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
326 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
327 | 623a930e | ths | } |
328 | 8c0fdd85 | ths | } |
329 | 8c0fdd85 | ths | |
330 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
331 | 8c0fdd85 | ths | { |
332 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
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333 | 6af0bf9c | bellard | } |
334 | 6af0bf9c | bellard | |
335 | 6ea83fed | bellard | void fpu_handle_exception(void) |
336 | 6ea83fed | bellard | { |
337 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
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338 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status);
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339 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
340 | 6ea83fed | bellard | |
341 | ead9360e | ths | enable = GET_FP_ENABLE(env->fpu->fcr31); |
342 | 6ea83fed | bellard | |
343 | 3b46e624 | ths | /* determine current flags */
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344 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
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345 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
346 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
347 | 6ea83fed | bellard | } |
348 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
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349 | 3b46e624 | ths | cpuflags |= FP_DIV0; |
350 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
351 | 6ea83fed | bellard | } |
352 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
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353 | 3b46e624 | ths | cpuflags |= FP_OVERFLOW; |
354 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
355 | 6ea83fed | bellard | } |
356 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
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357 | 3b46e624 | ths | cpuflags |= FP_UNDERFLOW; |
358 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
359 | 6ea83fed | bellard | } |
360 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
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361 | 5fafdf24 | ths | cpuflags |= FP_INEXACT; |
362 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
363 | 6ea83fed | bellard | } |
364 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, cpuflags); |
365 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, cause); |
366 | 6ea83fed | bellard | #else
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367 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, 0);
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368 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, 0);
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369 | 6ea83fed | bellard | #endif
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370 | 6ea83fed | bellard | } |
371 | 6ea83fed | bellard | |
372 | 6af0bf9c | bellard | /* TLB management */
|
373 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
374 | 814b9a47 | ths | { |
375 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
|
376 | 814b9a47 | ths | tlb_flush (env, flush_global); |
377 | ead9360e | ths | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
378 | 814b9a47 | ths | } |
379 | 814b9a47 | ths | |
380 | 29929e34 | ths | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
381 | 814b9a47 | ths | { |
382 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
|
383 | ead9360e | ths | while (env->tlb->tlb_in_use > first) {
|
384 | ead9360e | ths | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
385 | 814b9a47 | ths | } |
386 | 814b9a47 | ths | } |
387 | 814b9a47 | ths | |
388 | 29929e34 | ths | static void r4k_fill_tlb (int idx) |
389 | 6af0bf9c | bellard | { |
390 | 29929e34 | ths | r4k_tlb_t *tlb; |
391 | 6af0bf9c | bellard | |
392 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
393 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
394 | f2e9ebef | ths | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
395 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
396 | e034e2c3 | ths | tlb->VPN &= env->SEGMask; |
397 | 100ce988 | ths | #endif
|
398 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
|
399 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
400 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
401 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
402 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
403 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
404 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
405 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
406 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
407 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
408 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
409 | 6af0bf9c | bellard | } |
410 | 6af0bf9c | bellard | |
411 | 29929e34 | ths | void r4k_do_tlbwi (void) |
412 | 6af0bf9c | bellard | { |
413 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
|
414 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
|
415 | 814b9a47 | ths | that might be a further win. */
|
416 | ead9360e | ths | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
417 | 814b9a47 | ths | |
418 | ead9360e | ths | r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
|
419 | ead9360e | ths | r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb); |
420 | 6af0bf9c | bellard | } |
421 | 6af0bf9c | bellard | |
422 | 29929e34 | ths | void r4k_do_tlbwr (void) |
423 | 6af0bf9c | bellard | { |
424 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
425 | 6af0bf9c | bellard | |
426 | 29929e34 | ths | r4k_invalidate_tlb(env, r, 1);
|
427 | 29929e34 | ths | r4k_fill_tlb(r); |
428 | 6af0bf9c | bellard | } |
429 | 6af0bf9c | bellard | |
430 | 29929e34 | ths | void r4k_do_tlbp (void) |
431 | 6af0bf9c | bellard | { |
432 | 29929e34 | ths | r4k_tlb_t *tlb; |
433 | f2e9ebef | ths | target_ulong mask; |
434 | 6af0bf9c | bellard | target_ulong tag; |
435 | f2e9ebef | ths | target_ulong VPN; |
436 | 6af0bf9c | bellard | uint8_t ASID; |
437 | 6af0bf9c | bellard | int i;
|
438 | 6af0bf9c | bellard | |
439 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
440 | ead9360e | ths | for (i = 0; i < env->tlb->nb_tlb; i++) { |
441 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
442 | f2e9ebef | ths | /* 1k pages are not supported. */
|
443 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
444 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
445 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
446 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
447 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
448 | 6af0bf9c | bellard | /* TLB match */
|
449 | 9c2149c8 | ths | env->CP0_Index = i; |
450 | 6af0bf9c | bellard | break;
|
451 | 6af0bf9c | bellard | } |
452 | 6af0bf9c | bellard | } |
453 | ead9360e | ths | if (i == env->tlb->nb_tlb) {
|
454 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
|
455 | ead9360e | ths | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
456 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
457 | f2e9ebef | ths | /* 1k pages are not supported. */
|
458 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
459 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
460 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
461 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
|
462 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
463 | 29929e34 | ths | r4k_mips_tlb_flush_extra (env, i); |
464 | 814b9a47 | ths | break;
|
465 | 814b9a47 | ths | } |
466 | 814b9a47 | ths | } |
467 | 814b9a47 | ths | |
468 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
|
469 | 6af0bf9c | bellard | } |
470 | 6af0bf9c | bellard | } |
471 | 6af0bf9c | bellard | |
472 | 29929e34 | ths | void r4k_do_tlbr (void) |
473 | 6af0bf9c | bellard | { |
474 | 29929e34 | ths | r4k_tlb_t *tlb; |
475 | 09c56b84 | pbrook | uint8_t ASID; |
476 | 6af0bf9c | bellard | |
477 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
478 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb]; |
479 | 4ad40f36 | bellard | |
480 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
481 | 814b9a47 | ths | if (ASID != tlb->ASID)
|
482 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
|
483 | 814b9a47 | ths | |
484 | ead9360e | ths | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
485 | 4ad40f36 | bellard | |
486 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
487 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
488 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
489 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
490 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
491 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
492 | 6af0bf9c | bellard | } |
493 | 6af0bf9c | bellard | |
494 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
495 | 048f6b4d | bellard | |
496 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
497 | 6af0bf9c | bellard | { |
498 | 6af0bf9c | bellard | if (loglevel)
|
499 | 3594c774 | ths | fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
500 | 6af0bf9c | bellard | } |
501 | 6af0bf9c | bellard | |
502 | 6af0bf9c | bellard | void dump_sc (void) |
503 | 6af0bf9c | bellard | { |
504 | 6af0bf9c | bellard | if (loglevel) {
|
505 | 3594c774 | ths | fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
506 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
507 | 6af0bf9c | bellard | } |
508 | 6af0bf9c | bellard | } |
509 | 6af0bf9c | bellard | |
510 | f41c52f1 | ths | void debug_pre_eret (void) |
511 | 6af0bf9c | bellard | { |
512 | f41c52f1 | ths | fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
513 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
514 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
515 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
516 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
517 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
518 | f41c52f1 | ths | fputs("\n", logfile);
|
519 | f41c52f1 | ths | } |
520 | f41c52f1 | ths | |
521 | f41c52f1 | ths | void debug_post_eret (void) |
522 | f41c52f1 | ths | { |
523 | 744e0915 | ths | fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
524 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
525 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
526 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
527 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
528 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
529 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
|
530 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
531 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
532 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
533 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
534 | 623a930e | ths | } |
535 | 6af0bf9c | bellard | } |
536 | 6af0bf9c | bellard | |
537 | 6af0bf9c | bellard | void do_pmon (int function) |
538 | 6af0bf9c | bellard | { |
539 | 6af0bf9c | bellard | function /= 2;
|
540 | 6af0bf9c | bellard | switch (function) {
|
541 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
542 | ead9360e | ths | if (env->gpr[4][env->current_tc] == 0) |
543 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
544 | 6af0bf9c | bellard | /* Fall through */
|
545 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
546 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
547 | 6af0bf9c | bellard | break;
|
548 | 6af0bf9c | bellard | case 3: |
549 | 6af0bf9c | bellard | case 12: |
550 | ead9360e | ths | printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF)); |
551 | 6af0bf9c | bellard | break;
|
552 | 6af0bf9c | bellard | case 17: |
553 | 6af0bf9c | bellard | break;
|
554 | 6af0bf9c | bellard | case 158: |
555 | 6af0bf9c | bellard | { |
556 | ead9360e | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc]; |
557 | 6af0bf9c | bellard | printf("%s", fmt);
|
558 | 6af0bf9c | bellard | } |
559 | 6af0bf9c | bellard | break;
|
560 | 6af0bf9c | bellard | } |
561 | 6af0bf9c | bellard | } |
562 | e37e863f | bellard | |
563 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
564 | e37e863f | bellard | |
565 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
566 | 4ad40f36 | bellard | |
567 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
568 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
569 | e37e863f | bellard | |
570 | e37e863f | bellard | #define SHIFT 0 |
571 | e37e863f | bellard | #include "softmmu_template.h" |
572 | e37e863f | bellard | |
573 | e37e863f | bellard | #define SHIFT 1 |
574 | e37e863f | bellard | #include "softmmu_template.h" |
575 | e37e863f | bellard | |
576 | e37e863f | bellard | #define SHIFT 2 |
577 | e37e863f | bellard | #include "softmmu_template.h" |
578 | e37e863f | bellard | |
579 | e37e863f | bellard | #define SHIFT 3 |
580 | e37e863f | bellard | #include "softmmu_template.h" |
581 | e37e863f | bellard | |
582 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
583 | 4ad40f36 | bellard | { |
584 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
585 | 4ad40f36 | bellard | do_restore_state (retaddr); |
586 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
587 | 4ad40f36 | bellard | } |
588 | 4ad40f36 | bellard | |
589 | 6ebbf390 | j_mayer | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
590 | e37e863f | bellard | { |
591 | e37e863f | bellard | TranslationBlock *tb; |
592 | e37e863f | bellard | CPUState *saved_env; |
593 | e37e863f | bellard | unsigned long pc; |
594 | e37e863f | bellard | int ret;
|
595 | e37e863f | bellard | |
596 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
597 | e37e863f | bellard | generated code */
|
598 | e37e863f | bellard | saved_env = env; |
599 | e37e863f | bellard | env = cpu_single_env; |
600 | 6ebbf390 | j_mayer | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
601 | e37e863f | bellard | if (ret) {
|
602 | e37e863f | bellard | if (retaddr) {
|
603 | e37e863f | bellard | /* now we have a real cpu fault */
|
604 | e37e863f | bellard | pc = (unsigned long)retaddr; |
605 | e37e863f | bellard | tb = tb_find_pc(pc); |
606 | e37e863f | bellard | if (tb) {
|
607 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
608 | e37e863f | bellard | a virtual CPU fault */
|
609 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
610 | e37e863f | bellard | } |
611 | e37e863f | bellard | } |
612 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
613 | e37e863f | bellard | } |
614 | e37e863f | bellard | env = saved_env; |
615 | e37e863f | bellard | } |
616 | e37e863f | bellard | |
617 | 647de6ca | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
618 | 647de6ca | ths | int unused)
|
619 | 647de6ca | ths | { |
620 | 647de6ca | ths | if (is_exec)
|
621 | 647de6ca | ths | do_raise_exception(EXCP_IBE); |
622 | 647de6ca | ths | else
|
623 | 647de6ca | ths | do_raise_exception(EXCP_DBE); |
624 | 647de6ca | ths | } |
625 | e37e863f | bellard | #endif
|
626 | fd4a04eb | ths | |
627 | fd4a04eb | ths | /* Complex FPU operations which may need stack space. */
|
628 | fd4a04eb | ths | |
629 | 8dfdb87c | ths | #define FLOAT_SIGN32 (1 << 31) |
630 | 8dfdb87c | ths | #define FLOAT_SIGN64 (1ULL << 63) |
631 | 8dfdb87c | ths | #define FLOAT_ONE32 (0x3f8 << 20) |
632 | 8dfdb87c | ths | #define FLOAT_ONE64 (0x3ffULL << 52) |
633 | 8dfdb87c | ths | #define FLOAT_TWO32 (1 << 30) |
634 | 8dfdb87c | ths | #define FLOAT_TWO64 (1ULL << 62) |
635 | 54454097 | ths | #define FLOAT_QNAN32 0x7fbfffff |
636 | 54454097 | ths | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
637 | 54454097 | ths | #define FLOAT_SNAN32 0x7fffffff |
638 | 54454097 | ths | #define FLOAT_SNAN64 0x7fffffffffffffffULL |
639 | 8dfdb87c | ths | |
640 | fd4a04eb | ths | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
641 | fd4a04eb | ths | unsigned int ieee_rm[] = { |
642 | fd4a04eb | ths | float_round_nearest_even, |
643 | fd4a04eb | ths | float_round_to_zero, |
644 | fd4a04eb | ths | float_round_up, |
645 | fd4a04eb | ths | float_round_down |
646 | fd4a04eb | ths | }; |
647 | fd4a04eb | ths | |
648 | fd4a04eb | ths | #define RESTORE_ROUNDING_MODE \
|
649 | ead9360e | ths | set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
650 | fd4a04eb | ths | |
651 | ead9360e | ths | void do_cfc1 (int reg) |
652 | fd4a04eb | ths | { |
653 | ead9360e | ths | switch (reg) {
|
654 | ead9360e | ths | case 0: |
655 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr0; |
656 | ead9360e | ths | break;
|
657 | ead9360e | ths | case 25: |
658 | ead9360e | ths | T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); |
659 | ead9360e | ths | break;
|
660 | ead9360e | ths | case 26: |
661 | ead9360e | ths | T0 = env->fpu->fcr31 & 0x0003f07c;
|
662 | ead9360e | ths | break;
|
663 | ead9360e | ths | case 28: |
664 | ead9360e | ths | T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); |
665 | ead9360e | ths | break;
|
666 | ead9360e | ths | default:
|
667 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr31; |
668 | ead9360e | ths | break;
|
669 | ead9360e | ths | } |
670 | ead9360e | ths | } |
671 | ead9360e | ths | |
672 | ead9360e | ths | void do_ctc1 (int reg) |
673 | ead9360e | ths | { |
674 | ead9360e | ths | switch(reg) {
|
675 | fd4a04eb | ths | case 25: |
676 | fd4a04eb | ths | if (T0 & 0xffffff00) |
677 | fd4a04eb | ths | return;
|
678 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | |
679 | fd4a04eb | ths | ((T0 & 0x1) << 23); |
680 | fd4a04eb | ths | break;
|
681 | fd4a04eb | ths | case 26: |
682 | fd4a04eb | ths | if (T0 & 0x007c0000) |
683 | fd4a04eb | ths | return;
|
684 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); |
685 | fd4a04eb | ths | break;
|
686 | fd4a04eb | ths | case 28: |
687 | fd4a04eb | ths | if (T0 & 0x007c0000) |
688 | fd4a04eb | ths | return;
|
689 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | |
690 | fd4a04eb | ths | ((T0 & 0x4) << 22); |
691 | fd4a04eb | ths | break;
|
692 | fd4a04eb | ths | case 31: |
693 | fd4a04eb | ths | if (T0 & 0x007c0000) |
694 | fd4a04eb | ths | return;
|
695 | ead9360e | ths | env->fpu->fcr31 = T0; |
696 | fd4a04eb | ths | break;
|
697 | fd4a04eb | ths | default:
|
698 | fd4a04eb | ths | return;
|
699 | fd4a04eb | ths | } |
700 | fd4a04eb | ths | /* set rounding mode */
|
701 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
702 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
703 | ead9360e | ths | if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31)) |
704 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
705 | fd4a04eb | ths | } |
706 | fd4a04eb | ths | |
707 | aa343735 | ths | static always_inline char ieee_ex_to_mips(char xcpt) |
708 | fd4a04eb | ths | { |
709 | fd4a04eb | ths | return (xcpt & float_flag_inexact) >> 5 | |
710 | fd4a04eb | ths | (xcpt & float_flag_underflow) >> 3 |
|
711 | fd4a04eb | ths | (xcpt & float_flag_overflow) >> 1 |
|
712 | fd4a04eb | ths | (xcpt & float_flag_divbyzero) << 1 |
|
713 | fd4a04eb | ths | (xcpt & float_flag_invalid) << 4;
|
714 | fd4a04eb | ths | } |
715 | fd4a04eb | ths | |
716 | aa343735 | ths | static always_inline char mips_ex_to_ieee(char xcpt) |
717 | fd4a04eb | ths | { |
718 | fd4a04eb | ths | return (xcpt & FP_INEXACT) << 5 | |
719 | fd4a04eb | ths | (xcpt & FP_UNDERFLOW) << 3 |
|
720 | fd4a04eb | ths | (xcpt & FP_OVERFLOW) << 1 |
|
721 | fd4a04eb | ths | (xcpt & FP_DIV0) >> 1 |
|
722 | fd4a04eb | ths | (xcpt & FP_INVALID) >> 4;
|
723 | fd4a04eb | ths | } |
724 | fd4a04eb | ths | |
725 | aa343735 | ths | static always_inline void update_fcr31(void) |
726 | fd4a04eb | ths | { |
727 | ead9360e | ths | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
|
728 | fd4a04eb | ths | |
729 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, tmp); |
730 | ead9360e | ths | if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
|
731 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
732 | fd4a04eb | ths | else
|
733 | ead9360e | ths | UPDATE_FP_FLAGS(env->fpu->fcr31, tmp); |
734 | fd4a04eb | ths | } |
735 | fd4a04eb | ths | |
736 | fd4a04eb | ths | #define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
737 | fd4a04eb | ths | |
738 | fd4a04eb | ths | FLOAT_OP(cvtd, s) |
739 | fd4a04eb | ths | { |
740 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
741 | ead9360e | ths | FDT2 = float32_to_float64(FST0, &env->fpu->fp_status); |
742 | fd4a04eb | ths | update_fcr31(); |
743 | fd4a04eb | ths | } |
744 | fd4a04eb | ths | FLOAT_OP(cvtd, w) |
745 | fd4a04eb | ths | { |
746 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
747 | ead9360e | ths | FDT2 = int32_to_float64(WT0, &env->fpu->fp_status); |
748 | fd4a04eb | ths | update_fcr31(); |
749 | fd4a04eb | ths | } |
750 | fd4a04eb | ths | FLOAT_OP(cvtd, l) |
751 | fd4a04eb | ths | { |
752 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
753 | ead9360e | ths | FDT2 = int64_to_float64(DT0, &env->fpu->fp_status); |
754 | fd4a04eb | ths | update_fcr31(); |
755 | fd4a04eb | ths | } |
756 | fd4a04eb | ths | FLOAT_OP(cvtl, d) |
757 | fd4a04eb | ths | { |
758 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
759 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
760 | fd4a04eb | ths | update_fcr31(); |
761 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
762 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
763 | fd4a04eb | ths | } |
764 | fd4a04eb | ths | FLOAT_OP(cvtl, s) |
765 | fd4a04eb | ths | { |
766 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
767 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
768 | fd4a04eb | ths | update_fcr31(); |
769 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
770 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
771 | fd4a04eb | ths | } |
772 | fd4a04eb | ths | |
773 | fd4a04eb | ths | FLOAT_OP(cvtps, pw) |
774 | fd4a04eb | ths | { |
775 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
776 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
777 | ead9360e | ths | FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status); |
778 | fd4a04eb | ths | update_fcr31(); |
779 | fd4a04eb | ths | } |
780 | fd4a04eb | ths | FLOAT_OP(cvtpw, ps) |
781 | fd4a04eb | ths | { |
782 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
783 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
784 | ead9360e | ths | WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status); |
785 | fd4a04eb | ths | update_fcr31(); |
786 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
787 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
788 | fd4a04eb | ths | } |
789 | fd4a04eb | ths | FLOAT_OP(cvts, d) |
790 | fd4a04eb | ths | { |
791 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
792 | ead9360e | ths | FST2 = float64_to_float32(FDT0, &env->fpu->fp_status); |
793 | fd4a04eb | ths | update_fcr31(); |
794 | fd4a04eb | ths | } |
795 | fd4a04eb | ths | FLOAT_OP(cvts, w) |
796 | fd4a04eb | ths | { |
797 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
798 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
799 | fd4a04eb | ths | update_fcr31(); |
800 | fd4a04eb | ths | } |
801 | fd4a04eb | ths | FLOAT_OP(cvts, l) |
802 | fd4a04eb | ths | { |
803 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
804 | ead9360e | ths | FST2 = int64_to_float32(DT0, &env->fpu->fp_status); |
805 | fd4a04eb | ths | update_fcr31(); |
806 | fd4a04eb | ths | } |
807 | fd4a04eb | ths | FLOAT_OP(cvts, pl) |
808 | fd4a04eb | ths | { |
809 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
810 | fd4a04eb | ths | WT2 = WT0; |
811 | fd4a04eb | ths | update_fcr31(); |
812 | fd4a04eb | ths | } |
813 | fd4a04eb | ths | FLOAT_OP(cvts, pu) |
814 | fd4a04eb | ths | { |
815 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
816 | fd4a04eb | ths | WT2 = WTH0; |
817 | fd4a04eb | ths | update_fcr31(); |
818 | fd4a04eb | ths | } |
819 | fd4a04eb | ths | FLOAT_OP(cvtw, s) |
820 | fd4a04eb | ths | { |
821 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
822 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
823 | fd4a04eb | ths | update_fcr31(); |
824 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
825 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
826 | fd4a04eb | ths | } |
827 | fd4a04eb | ths | FLOAT_OP(cvtw, d) |
828 | fd4a04eb | ths | { |
829 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
830 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
831 | fd4a04eb | ths | update_fcr31(); |
832 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
833 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
834 | fd4a04eb | ths | } |
835 | fd4a04eb | ths | |
836 | fd4a04eb | ths | FLOAT_OP(roundl, d) |
837 | fd4a04eb | ths | { |
838 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
839 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
840 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
841 | fd4a04eb | ths | update_fcr31(); |
842 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
843 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
844 | fd4a04eb | ths | } |
845 | fd4a04eb | ths | FLOAT_OP(roundl, s) |
846 | fd4a04eb | ths | { |
847 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
848 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
849 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
850 | fd4a04eb | ths | update_fcr31(); |
851 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
852 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
853 | fd4a04eb | ths | } |
854 | fd4a04eb | ths | FLOAT_OP(roundw, d) |
855 | fd4a04eb | ths | { |
856 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
857 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
858 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
859 | fd4a04eb | ths | update_fcr31(); |
860 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
861 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
862 | fd4a04eb | ths | } |
863 | fd4a04eb | ths | FLOAT_OP(roundw, s) |
864 | fd4a04eb | ths | { |
865 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
866 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
867 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
868 | fd4a04eb | ths | update_fcr31(); |
869 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
870 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
871 | fd4a04eb | ths | } |
872 | fd4a04eb | ths | |
873 | fd4a04eb | ths | FLOAT_OP(truncl, d) |
874 | fd4a04eb | ths | { |
875 | ead9360e | ths | DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status); |
876 | fd4a04eb | ths | update_fcr31(); |
877 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
878 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
879 | fd4a04eb | ths | } |
880 | fd4a04eb | ths | FLOAT_OP(truncl, s) |
881 | fd4a04eb | ths | { |
882 | ead9360e | ths | DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status); |
883 | fd4a04eb | ths | update_fcr31(); |
884 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
885 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
886 | fd4a04eb | ths | } |
887 | fd4a04eb | ths | FLOAT_OP(truncw, d) |
888 | fd4a04eb | ths | { |
889 | ead9360e | ths | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status); |
890 | fd4a04eb | ths | update_fcr31(); |
891 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
892 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
893 | fd4a04eb | ths | } |
894 | fd4a04eb | ths | FLOAT_OP(truncw, s) |
895 | fd4a04eb | ths | { |
896 | ead9360e | ths | WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status); |
897 | fd4a04eb | ths | update_fcr31(); |
898 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
899 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
900 | fd4a04eb | ths | } |
901 | fd4a04eb | ths | |
902 | fd4a04eb | ths | FLOAT_OP(ceill, d) |
903 | fd4a04eb | ths | { |
904 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
905 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
906 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
907 | fd4a04eb | ths | update_fcr31(); |
908 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
909 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
910 | fd4a04eb | ths | } |
911 | fd4a04eb | ths | FLOAT_OP(ceill, s) |
912 | fd4a04eb | ths | { |
913 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
914 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
915 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
916 | fd4a04eb | ths | update_fcr31(); |
917 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
918 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
919 | fd4a04eb | ths | } |
920 | fd4a04eb | ths | FLOAT_OP(ceilw, d) |
921 | fd4a04eb | ths | { |
922 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
923 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
924 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
925 | fd4a04eb | ths | update_fcr31(); |
926 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
927 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
928 | fd4a04eb | ths | } |
929 | fd4a04eb | ths | FLOAT_OP(ceilw, s) |
930 | fd4a04eb | ths | { |
931 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
932 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
933 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
934 | fd4a04eb | ths | update_fcr31(); |
935 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
936 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
937 | fd4a04eb | ths | } |
938 | fd4a04eb | ths | |
939 | fd4a04eb | ths | FLOAT_OP(floorl, d) |
940 | fd4a04eb | ths | { |
941 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
942 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
943 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
944 | fd4a04eb | ths | update_fcr31(); |
945 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
946 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
947 | fd4a04eb | ths | } |
948 | fd4a04eb | ths | FLOAT_OP(floorl, s) |
949 | fd4a04eb | ths | { |
950 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
951 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
952 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
953 | fd4a04eb | ths | update_fcr31(); |
954 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
955 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
956 | fd4a04eb | ths | } |
957 | fd4a04eb | ths | FLOAT_OP(floorw, d) |
958 | fd4a04eb | ths | { |
959 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
960 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
961 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
962 | fd4a04eb | ths | update_fcr31(); |
963 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
964 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
965 | fd4a04eb | ths | } |
966 | fd4a04eb | ths | FLOAT_OP(floorw, s) |
967 | fd4a04eb | ths | { |
968 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
969 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
970 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
971 | fd4a04eb | ths | update_fcr31(); |
972 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
973 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
974 | fd4a04eb | ths | } |
975 | fd4a04eb | ths | |
976 | 8dfdb87c | ths | /* MIPS specific unary operations */
|
977 | 8dfdb87c | ths | FLOAT_OP(recip, d) |
978 | 8dfdb87c | ths | { |
979 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
980 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
981 | 8dfdb87c | ths | update_fcr31(); |
982 | 8dfdb87c | ths | } |
983 | 8dfdb87c | ths | FLOAT_OP(recip, s) |
984 | 8dfdb87c | ths | { |
985 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
986 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
987 | 8dfdb87c | ths | update_fcr31(); |
988 | 57fa1fb3 | ths | } |
989 | 57fa1fb3 | ths | |
990 | 8dfdb87c | ths | FLOAT_OP(rsqrt, d) |
991 | 8dfdb87c | ths | { |
992 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
993 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
994 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
995 | 8dfdb87c | ths | update_fcr31(); |
996 | 8dfdb87c | ths | } |
997 | 8dfdb87c | ths | FLOAT_OP(rsqrt, s) |
998 | 8dfdb87c | ths | { |
999 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1000 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1001 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1002 | 8dfdb87c | ths | update_fcr31(); |
1003 | 8dfdb87c | ths | } |
1004 | 8dfdb87c | ths | |
1005 | 8dfdb87c | ths | FLOAT_OP(recip1, d) |
1006 | 8dfdb87c | ths | { |
1007 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1008 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
1009 | 8dfdb87c | ths | update_fcr31(); |
1010 | 8dfdb87c | ths | } |
1011 | 8dfdb87c | ths | FLOAT_OP(recip1, s) |
1012 | 8dfdb87c | ths | { |
1013 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1014 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1015 | 8dfdb87c | ths | update_fcr31(); |
1016 | 8dfdb87c | ths | } |
1017 | 8dfdb87c | ths | FLOAT_OP(recip1, ps) |
1018 | 8dfdb87c | ths | { |
1019 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1020 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1021 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status); |
1022 | 8dfdb87c | ths | update_fcr31(); |
1023 | 8dfdb87c | ths | } |
1024 | 8dfdb87c | ths | |
1025 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, d) |
1026 | 8dfdb87c | ths | { |
1027 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1028 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
1029 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
1030 | 8dfdb87c | ths | update_fcr31(); |
1031 | 8dfdb87c | ths | } |
1032 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, s) |
1033 | 8dfdb87c | ths | { |
1034 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1035 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1036 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1037 | 8dfdb87c | ths | update_fcr31(); |
1038 | 8dfdb87c | ths | } |
1039 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, ps) |
1040 | 8dfdb87c | ths | { |
1041 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1042 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1043 | ead9360e | ths | FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status); |
1044 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1045 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status); |
1046 | 8dfdb87c | ths | update_fcr31(); |
1047 | 57fa1fb3 | ths | } |
1048 | 57fa1fb3 | ths | |
1049 | fd4a04eb | ths | /* binary operations */
|
1050 | fd4a04eb | ths | #define FLOAT_BINOP(name) \
|
1051 | fd4a04eb | ths | FLOAT_OP(name, d) \ |
1052 | fd4a04eb | ths | { \ |
1053 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1054 | ead9360e | ths | FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \ |
1055 | ead9360e | ths | update_fcr31(); \ |
1056 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1057 | 54454097 | ths | FDT2 = FLOAT_QNAN64; \ |
1058 | fd4a04eb | ths | } \ |
1059 | fd4a04eb | ths | FLOAT_OP(name, s) \ |
1060 | fd4a04eb | ths | { \ |
1061 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1062 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1063 | ead9360e | ths | update_fcr31(); \ |
1064 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1065 | 54454097 | ths | FST2 = FLOAT_QNAN32; \ |
1066 | fd4a04eb | ths | } \ |
1067 | fd4a04eb | ths | FLOAT_OP(name, ps) \ |
1068 | fd4a04eb | ths | { \ |
1069 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1070 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1071 | ead9360e | ths | FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \ |
1072 | fd4a04eb | ths | update_fcr31(); \ |
1073 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
1074 | 54454097 | ths | FST2 = FLOAT_QNAN32; \ |
1075 | 54454097 | ths | FSTH2 = FLOAT_QNAN32; \ |
1076 | 3a5b360d | ths | } \ |
1077 | fd4a04eb | ths | } |
1078 | fd4a04eb | ths | FLOAT_BINOP(add) |
1079 | fd4a04eb | ths | FLOAT_BINOP(sub) |
1080 | fd4a04eb | ths | FLOAT_BINOP(mul) |
1081 | fd4a04eb | ths | FLOAT_BINOP(div) |
1082 | fd4a04eb | ths | #undef FLOAT_BINOP
|
1083 | fd4a04eb | ths | |
1084 | 8dfdb87c | ths | /* MIPS specific binary operations */
|
1085 | 8dfdb87c | ths | FLOAT_OP(recip2, d) |
1086 | 8dfdb87c | ths | { |
1087 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1088 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1089 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64; |
1090 | 8dfdb87c | ths | update_fcr31(); |
1091 | 8dfdb87c | ths | } |
1092 | 8dfdb87c | ths | FLOAT_OP(recip2, s) |
1093 | 8dfdb87c | ths | { |
1094 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1095 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1096 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1097 | 8dfdb87c | ths | update_fcr31(); |
1098 | 8dfdb87c | ths | } |
1099 | 8dfdb87c | ths | FLOAT_OP(recip2, ps) |
1100 | 8dfdb87c | ths | { |
1101 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1102 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1103 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1104 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1105 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1106 | 8dfdb87c | ths | update_fcr31(); |
1107 | 8dfdb87c | ths | } |
1108 | 8dfdb87c | ths | |
1109 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, d) |
1110 | 8dfdb87c | ths | { |
1111 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1112 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1113 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status); |
1114 | ead9360e | ths | FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64; |
1115 | 8dfdb87c | ths | update_fcr31(); |
1116 | 8dfdb87c | ths | } |
1117 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, s) |
1118 | 8dfdb87c | ths | { |
1119 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1120 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1121 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1122 | ead9360e | ths | FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1123 | 8dfdb87c | ths | update_fcr31(); |
1124 | 8dfdb87c | ths | } |
1125 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, ps) |
1126 | 8dfdb87c | ths | { |
1127 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1128 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1129 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1130 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1131 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status); |
1132 | ead9360e | ths | FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1133 | ead9360e | ths | FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32; |
1134 | 8dfdb87c | ths | update_fcr31(); |
1135 | 57fa1fb3 | ths | } |
1136 | 57fa1fb3 | ths | |
1137 | fd4a04eb | ths | FLOAT_OP(addr, ps) |
1138 | fd4a04eb | ths | { |
1139 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1140 | ead9360e | ths | FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status); |
1141 | ead9360e | ths | FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status); |
1142 | fd4a04eb | ths | update_fcr31(); |
1143 | fd4a04eb | ths | } |
1144 | fd4a04eb | ths | |
1145 | 57fa1fb3 | ths | FLOAT_OP(mulr, ps) |
1146 | 57fa1fb3 | ths | { |
1147 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1148 | ead9360e | ths | FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status); |
1149 | ead9360e | ths | FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status); |
1150 | 57fa1fb3 | ths | update_fcr31(); |
1151 | 57fa1fb3 | ths | } |
1152 | 57fa1fb3 | ths | |
1153 | 8dfdb87c | ths | /* compare operations */
|
1154 | fd4a04eb | ths | #define FOP_COND_D(op, cond) \
|
1155 | fd4a04eb | ths | void do_cmp_d_ ## op (long cc) \ |
1156 | fd4a04eb | ths | { \ |
1157 | fd4a04eb | ths | int c = cond; \
|
1158 | fd4a04eb | ths | update_fcr31(); \ |
1159 | fd4a04eb | ths | if (c) \
|
1160 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1161 | fd4a04eb | ths | else \
|
1162 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1163 | fd4a04eb | ths | } \ |
1164 | fd4a04eb | ths | void do_cmpabs_d_ ## op (long cc) \ |
1165 | fd4a04eb | ths | { \ |
1166 | fd4a04eb | ths | int c; \
|
1167 | 8dfdb87c | ths | FDT0 &= ~FLOAT_SIGN64; \ |
1168 | 8dfdb87c | ths | FDT1 &= ~FLOAT_SIGN64; \ |
1169 | fd4a04eb | ths | c = cond; \ |
1170 | fd4a04eb | ths | update_fcr31(); \ |
1171 | fd4a04eb | ths | if (c) \
|
1172 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1173 | fd4a04eb | ths | else \
|
1174 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1175 | fd4a04eb | ths | } |
1176 | fd4a04eb | ths | |
1177 | fd4a04eb | ths | int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
1178 | fd4a04eb | ths | { |
1179 | fd4a04eb | ths | if (float64_is_signaling_nan(a) ||
|
1180 | fd4a04eb | ths | float64_is_signaling_nan(b) || |
1181 | fd4a04eb | ths | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
1182 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1183 | fd4a04eb | ths | return 1; |
1184 | fd4a04eb | ths | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
1185 | fd4a04eb | ths | return 1; |
1186 | fd4a04eb | ths | } else {
|
1187 | fd4a04eb | ths | return 0; |
1188 | fd4a04eb | ths | } |
1189 | fd4a04eb | ths | } |
1190 | fd4a04eb | ths | |
1191 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1192 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1193 | ead9360e | ths | FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1194 | ead9360e | ths | FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
|
1195 | ead9360e | ths | FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1196 | ead9360e | ths | FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1197 | ead9360e | ths | FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1198 | ead9360e | ths | FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1199 | ead9360e | ths | FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1200 | ead9360e | ths | FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1201 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1202 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1203 | ead9360e | ths | FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1204 | ead9360e | ths | FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
|
1205 | ead9360e | ths | FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1206 | ead9360e | ths | FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1207 | ead9360e | ths | FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1208 | ead9360e | ths | FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1209 | ead9360e | ths | FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1210 | ead9360e | ths | FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1211 | fd4a04eb | ths | |
1212 | fd4a04eb | ths | #define FOP_COND_S(op, cond) \
|
1213 | fd4a04eb | ths | void do_cmp_s_ ## op (long cc) \ |
1214 | fd4a04eb | ths | { \ |
1215 | fd4a04eb | ths | int c = cond; \
|
1216 | fd4a04eb | ths | update_fcr31(); \ |
1217 | fd4a04eb | ths | if (c) \
|
1218 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1219 | fd4a04eb | ths | else \
|
1220 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1221 | fd4a04eb | ths | } \ |
1222 | fd4a04eb | ths | void do_cmpabs_s_ ## op (long cc) \ |
1223 | fd4a04eb | ths | { \ |
1224 | fd4a04eb | ths | int c; \
|
1225 | 8dfdb87c | ths | FST0 &= ~FLOAT_SIGN32; \ |
1226 | 8dfdb87c | ths | FST1 &= ~FLOAT_SIGN32; \ |
1227 | fd4a04eb | ths | c = cond; \ |
1228 | fd4a04eb | ths | update_fcr31(); \ |
1229 | fd4a04eb | ths | if (c) \
|
1230 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1231 | fd4a04eb | ths | else \
|
1232 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1233 | fd4a04eb | ths | } |
1234 | fd4a04eb | ths | |
1235 | fd4a04eb | ths | flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
1236 | fd4a04eb | ths | { |
1237 | fd4a04eb | ths | if (float32_is_signaling_nan(a) ||
|
1238 | fd4a04eb | ths | float32_is_signaling_nan(b) || |
1239 | fd4a04eb | ths | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
1240 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1241 | fd4a04eb | ths | return 1; |
1242 | fd4a04eb | ths | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
1243 | fd4a04eb | ths | return 1; |
1244 | fd4a04eb | ths | } else {
|
1245 | fd4a04eb | ths | return 0; |
1246 | fd4a04eb | ths | } |
1247 | fd4a04eb | ths | } |
1248 | fd4a04eb | ths | |
1249 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1250 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1251 | ead9360e | ths | FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0)) |
1252 | ead9360e | ths | FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
|
1253 | ead9360e | ths | FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1254 | ead9360e | ths | FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1255 | ead9360e | ths | FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1256 | ead9360e | ths | FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1257 | ead9360e | ths | FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1258 | ead9360e | ths | FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1259 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1260 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1261 | ead9360e | ths | FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0)) |
1262 | ead9360e | ths | FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
|
1263 | ead9360e | ths | FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1264 | ead9360e | ths | FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1265 | ead9360e | ths | FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1266 | ead9360e | ths | FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1267 | ead9360e | ths | FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1268 | ead9360e | ths | FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1269 | fd4a04eb | ths | |
1270 | fd4a04eb | ths | #define FOP_COND_PS(op, condl, condh) \
|
1271 | fd4a04eb | ths | void do_cmp_ps_ ## op (long cc) \ |
1272 | fd4a04eb | ths | { \ |
1273 | fd4a04eb | ths | int cl = condl; \
|
1274 | fd4a04eb | ths | int ch = condh; \
|
1275 | fd4a04eb | ths | update_fcr31(); \ |
1276 | fd4a04eb | ths | if (cl) \
|
1277 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1278 | fd4a04eb | ths | else \
|
1279 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1280 | fd4a04eb | ths | if (ch) \
|
1281 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1282 | fd4a04eb | ths | else \
|
1283 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1284 | fd4a04eb | ths | } \ |
1285 | fd4a04eb | ths | void do_cmpabs_ps_ ## op (long cc) \ |
1286 | fd4a04eb | ths | { \ |
1287 | fd4a04eb | ths | int cl, ch; \
|
1288 | 8dfdb87c | ths | FST0 &= ~FLOAT_SIGN32; \ |
1289 | 8dfdb87c | ths | FSTH0 &= ~FLOAT_SIGN32; \ |
1290 | 8dfdb87c | ths | FST1 &= ~FLOAT_SIGN32; \ |
1291 | 8dfdb87c | ths | FSTH1 &= ~FLOAT_SIGN32; \ |
1292 | fd4a04eb | ths | cl = condl; \ |
1293 | fd4a04eb | ths | ch = condh; \ |
1294 | fd4a04eb | ths | update_fcr31(); \ |
1295 | fd4a04eb | ths | if (cl) \
|
1296 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1297 | fd4a04eb | ths | else \
|
1298 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1299 | fd4a04eb | ths | if (ch) \
|
1300 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1301 | fd4a04eb | ths | else \
|
1302 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1303 | fd4a04eb | ths | } |
1304 | fd4a04eb | ths | |
1305 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1306 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1307 | ead9360e | ths | FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0), |
1308 | ead9360e | ths | (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1309 | ead9360e | ths | FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
|
1310 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
|
1311 | ead9360e | ths | FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1312 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1313 | ead9360e | ths | FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1314 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1315 | ead9360e | ths | FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1316 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1317 | ead9360e | ths | FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1318 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1319 | ead9360e | ths | FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1320 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1321 | ead9360e | ths | FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1322 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1323 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1324 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1325 | ead9360e | ths | FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0), |
1326 | ead9360e | ths | (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1327 | ead9360e | ths | FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
|
1328 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
|
1329 | ead9360e | ths | FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1330 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1331 | ead9360e | ths | FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1332 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1333 | ead9360e | ths | FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1334 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1335 | ead9360e | ths | FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1336 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1337 | ead9360e | ths | FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1338 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1339 | ead9360e | ths | FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1340 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status)) |