root / target-microblaze / mmu.c @ 283c7c63
History | View | Annotate | Download (9.1 kB)
1 | afeeceb0 | Edgar E. Iglesias | /*
|
---|---|---|---|
2 | afeeceb0 | Edgar E. Iglesias | * Microblaze MMU emulation for qemu.
|
3 | afeeceb0 | Edgar E. Iglesias | *
|
4 | afeeceb0 | Edgar E. Iglesias | * Copyright (c) 2009 Edgar E. Iglesias
|
5 | afeeceb0 | Edgar E. Iglesias | *
|
6 | afeeceb0 | Edgar E. Iglesias | * This library is free software; you can redistribute it and/or
|
7 | afeeceb0 | Edgar E. Iglesias | * modify it under the terms of the GNU Lesser General Public
|
8 | afeeceb0 | Edgar E. Iglesias | * License as published by the Free Software Foundation; either
|
9 | afeeceb0 | Edgar E. Iglesias | * version 2 of the License, or (at your option) any later version.
|
10 | afeeceb0 | Edgar E. Iglesias | *
|
11 | afeeceb0 | Edgar E. Iglesias | * This library is distributed in the hope that it will be useful,
|
12 | afeeceb0 | Edgar E. Iglesias | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | afeeceb0 | Edgar E. Iglesias | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | afeeceb0 | Edgar E. Iglesias | * Lesser General Public License for more details.
|
15 | afeeceb0 | Edgar E. Iglesias | *
|
16 | afeeceb0 | Edgar E. Iglesias | * You should have received a copy of the GNU Lesser General Public
|
17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 | afeeceb0 | Edgar E. Iglesias | */
|
19 | afeeceb0 | Edgar E. Iglesias | #include <stdio.h> |
20 | afeeceb0 | Edgar E. Iglesias | #include <stdlib.h> |
21 | afeeceb0 | Edgar E. Iglesias | #include <assert.h> |
22 | afeeceb0 | Edgar E. Iglesias | |
23 | afeeceb0 | Edgar E. Iglesias | #include "config.h" |
24 | afeeceb0 | Edgar E. Iglesias | #include "cpu.h" |
25 | afeeceb0 | Edgar E. Iglesias | #include "exec-all.h" |
26 | afeeceb0 | Edgar E. Iglesias | |
27 | afeeceb0 | Edgar E. Iglesias | #define D(x)
|
28 | afeeceb0 | Edgar E. Iglesias | |
29 | afeeceb0 | Edgar E. Iglesias | static unsigned int tlb_decode_size(unsigned int f) |
30 | afeeceb0 | Edgar E. Iglesias | { |
31 | afeeceb0 | Edgar E. Iglesias | static const unsigned int sizes[] = { |
32 | afeeceb0 | Edgar E. Iglesias | 1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024, |
33 | afeeceb0 | Edgar E. Iglesias | 1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024 |
34 | afeeceb0 | Edgar E. Iglesias | }; |
35 | afeeceb0 | Edgar E. Iglesias | assert(f < ARRAY_SIZE(sizes)); |
36 | afeeceb0 | Edgar E. Iglesias | return sizes[f];
|
37 | afeeceb0 | Edgar E. Iglesias | } |
38 | afeeceb0 | Edgar E. Iglesias | |
39 | 6b2fce90 | Edgar E. Iglesias | static void mmu_flush_idx(CPUState *env, unsigned int idx) |
40 | afeeceb0 | Edgar E. Iglesias | { |
41 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu *mmu = &env->mmu;
|
42 | afeeceb0 | Edgar E. Iglesias | unsigned int tlb_size; |
43 | afeeceb0 | Edgar E. Iglesias | uint32_t tlb_tag, end, t; |
44 | afeeceb0 | Edgar E. Iglesias | |
45 | afeeceb0 | Edgar E. Iglesias | t = mmu->rams[RAM_TAG][idx]; |
46 | afeeceb0 | Edgar E. Iglesias | if (!(t & TLB_VALID))
|
47 | afeeceb0 | Edgar E. Iglesias | return;
|
48 | afeeceb0 | Edgar E. Iglesias | |
49 | afeeceb0 | Edgar E. Iglesias | tlb_tag = t & TLB_EPN_MASK; |
50 | afeeceb0 | Edgar E. Iglesias | tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
|
51 | afeeceb0 | Edgar E. Iglesias | end = tlb_tag + tlb_size; |
52 | afeeceb0 | Edgar E. Iglesias | |
53 | afeeceb0 | Edgar E. Iglesias | while (tlb_tag < end) {
|
54 | afeeceb0 | Edgar E. Iglesias | tlb_flush_page(env, tlb_tag); |
55 | afeeceb0 | Edgar E. Iglesias | tlb_tag += TARGET_PAGE_SIZE; |
56 | afeeceb0 | Edgar E. Iglesias | } |
57 | afeeceb0 | Edgar E. Iglesias | } |
58 | afeeceb0 | Edgar E. Iglesias | |
59 | afeeceb0 | Edgar E. Iglesias | static void mmu_change_pid(CPUState *env, unsigned int newpid) |
60 | afeeceb0 | Edgar E. Iglesias | { |
61 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu *mmu = &env->mmu;
|
62 | afeeceb0 | Edgar E. Iglesias | unsigned int i; |
63 | afeeceb0 | Edgar E. Iglesias | unsigned int tlb_size; |
64 | afeeceb0 | Edgar E. Iglesias | uint32_t tlb_tag, mask, t; |
65 | afeeceb0 | Edgar E. Iglesias | |
66 | afeeceb0 | Edgar E. Iglesias | if (newpid & ~0xff) |
67 | afeeceb0 | Edgar E. Iglesias | qemu_log("Illegal rpid=%x\n", newpid);
|
68 | afeeceb0 | Edgar E. Iglesias | |
69 | afeeceb0 | Edgar E. Iglesias | for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { |
70 | afeeceb0 | Edgar E. Iglesias | /* Lookup and decode. */
|
71 | afeeceb0 | Edgar E. Iglesias | t = mmu->rams[RAM_TAG][i]; |
72 | afeeceb0 | Edgar E. Iglesias | if (t & TLB_VALID) {
|
73 | afeeceb0 | Edgar E. Iglesias | tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
|
74 | afeeceb0 | Edgar E. Iglesias | mask = ~(tlb_size - 1);
|
75 | afeeceb0 | Edgar E. Iglesias | |
76 | afeeceb0 | Edgar E. Iglesias | tlb_tag = t & TLB_EPN_MASK; |
77 | afeeceb0 | Edgar E. Iglesias | if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i])) |
78 | afeeceb0 | Edgar E. Iglesias | mmu_flush_idx(env, i); |
79 | afeeceb0 | Edgar E. Iglesias | } |
80 | afeeceb0 | Edgar E. Iglesias | } |
81 | afeeceb0 | Edgar E. Iglesias | } |
82 | afeeceb0 | Edgar E. Iglesias | |
83 | afeeceb0 | Edgar E. Iglesias | /* rw - 0 = read, 1 = write, 2 = fetch. */
|
84 | afeeceb0 | Edgar E. Iglesias | unsigned int mmu_translate(struct microblaze_mmu *mmu, |
85 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu_lookup *lu,
|
86 | afeeceb0 | Edgar E. Iglesias | target_ulong vaddr, int rw, int mmu_idx) |
87 | afeeceb0 | Edgar E. Iglesias | { |
88 | afeeceb0 | Edgar E. Iglesias | unsigned int i, hit = 0; |
89 | afeeceb0 | Edgar E. Iglesias | unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel; |
90 | afeeceb0 | Edgar E. Iglesias | unsigned int tlb_size; |
91 | afeeceb0 | Edgar E. Iglesias | uint32_t tlb_tag, tlb_rpn, mask, t0; |
92 | afeeceb0 | Edgar E. Iglesias | |
93 | afeeceb0 | Edgar E. Iglesias | lu->err = ERR_MISS; |
94 | afeeceb0 | Edgar E. Iglesias | for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { |
95 | afeeceb0 | Edgar E. Iglesias | uint32_t t, d; |
96 | afeeceb0 | Edgar E. Iglesias | |
97 | afeeceb0 | Edgar E. Iglesias | /* Lookup and decode. */
|
98 | afeeceb0 | Edgar E. Iglesias | t = mmu->rams[RAM_TAG][i]; |
99 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
|
100 | afeeceb0 | Edgar E. Iglesias | if (t & TLB_VALID) {
|
101 | afeeceb0 | Edgar E. Iglesias | tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
|
102 | afeeceb0 | Edgar E. Iglesias | if (tlb_size < TARGET_PAGE_SIZE) {
|
103 | afeeceb0 | Edgar E. Iglesias | qemu_log("%d pages not supported\n", tlb_size);
|
104 | afeeceb0 | Edgar E. Iglesias | abort(); |
105 | afeeceb0 | Edgar E. Iglesias | } |
106 | afeeceb0 | Edgar E. Iglesias | |
107 | afeeceb0 | Edgar E. Iglesias | mask = ~(tlb_size - 1);
|
108 | afeeceb0 | Edgar E. Iglesias | tlb_tag = t & TLB_EPN_MASK; |
109 | afeeceb0 | Edgar E. Iglesias | if ((vaddr & mask) != (tlb_tag & mask)) {
|
110 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
|
111 | afeeceb0 | Edgar E. Iglesias | i, vaddr & mask, tlb_tag & mask)); |
112 | afeeceb0 | Edgar E. Iglesias | continue;
|
113 | afeeceb0 | Edgar E. Iglesias | } |
114 | afeeceb0 | Edgar E. Iglesias | if (mmu->tids[i]
|
115 | afeeceb0 | Edgar E. Iglesias | && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
|
116 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("TLB %d pid=%x != tid=%x\n",
|
117 | afeeceb0 | Edgar E. Iglesias | i, mmu->regs[MMU_R_PID], mmu->tids[i])); |
118 | afeeceb0 | Edgar E. Iglesias | continue;
|
119 | afeeceb0 | Edgar E. Iglesias | } |
120 | afeeceb0 | Edgar E. Iglesias | |
121 | afeeceb0 | Edgar E. Iglesias | /* Bring in the data part. */
|
122 | afeeceb0 | Edgar E. Iglesias | d = mmu->rams[RAM_DATA][i]; |
123 | afeeceb0 | Edgar E. Iglesias | tlb_ex = d & TLB_EX; |
124 | afeeceb0 | Edgar E. Iglesias | tlb_wr = d & TLB_WR; |
125 | afeeceb0 | Edgar E. Iglesias | |
126 | afeeceb0 | Edgar E. Iglesias | /* Now lets see if there is a zone that overrides the protbits. */
|
127 | afeeceb0 | Edgar E. Iglesias | tlb_zsel = (d >> 4) & 0xf; |
128 | afeeceb0 | Edgar E. Iglesias | t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2)); |
129 | afeeceb0 | Edgar E. Iglesias | t0 &= 0x3;
|
130 | 3c50a71f | Edgar E. Iglesias | |
131 | 3c50a71f | Edgar E. Iglesias | if (tlb_zsel > mmu->c_mmu_zones) {
|
132 | 3c50a71f | Edgar E. Iglesias | qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
|
133 | 3c50a71f | Edgar E. Iglesias | t0 = 1; /* Ignore. */ |
134 | 3c50a71f | Edgar E. Iglesias | } |
135 | 3c50a71f | Edgar E. Iglesias | |
136 | 3c50a71f | Edgar E. Iglesias | if (mmu->c_mmu == 1) { |
137 | 3c50a71f | Edgar E. Iglesias | t0 = 1; /* Zones are disabled. */ |
138 | 3c50a71f | Edgar E. Iglesias | } |
139 | 3c50a71f | Edgar E. Iglesias | |
140 | afeeceb0 | Edgar E. Iglesias | switch (t0) {
|
141 | afeeceb0 | Edgar E. Iglesias | case 0: |
142 | afeeceb0 | Edgar E. Iglesias | if (mmu_idx == MMU_USER_IDX)
|
143 | afeeceb0 | Edgar E. Iglesias | continue;
|
144 | afeeceb0 | Edgar E. Iglesias | break;
|
145 | afeeceb0 | Edgar E. Iglesias | case 2: |
146 | afeeceb0 | Edgar E. Iglesias | if (mmu_idx != MMU_USER_IDX) {
|
147 | afeeceb0 | Edgar E. Iglesias | tlb_ex = 1;
|
148 | afeeceb0 | Edgar E. Iglesias | tlb_wr = 1;
|
149 | afeeceb0 | Edgar E. Iglesias | } |
150 | afeeceb0 | Edgar E. Iglesias | break;
|
151 | afeeceb0 | Edgar E. Iglesias | case 3: |
152 | afeeceb0 | Edgar E. Iglesias | tlb_ex = 1;
|
153 | afeeceb0 | Edgar E. Iglesias | tlb_wr = 1;
|
154 | afeeceb0 | Edgar E. Iglesias | break;
|
155 | 3c50a71f | Edgar E. Iglesias | default: break; |
156 | afeeceb0 | Edgar E. Iglesias | } |
157 | afeeceb0 | Edgar E. Iglesias | |
158 | afeeceb0 | Edgar E. Iglesias | lu->err = ERR_PROT; |
159 | afeeceb0 | Edgar E. Iglesias | lu->prot = PAGE_READ; |
160 | afeeceb0 | Edgar E. Iglesias | if (tlb_wr)
|
161 | afeeceb0 | Edgar E. Iglesias | lu->prot |= PAGE_WRITE; |
162 | afeeceb0 | Edgar E. Iglesias | else if (rw == 1) |
163 | afeeceb0 | Edgar E. Iglesias | goto done;
|
164 | afeeceb0 | Edgar E. Iglesias | if (tlb_ex)
|
165 | afeeceb0 | Edgar E. Iglesias | lu->prot |=PAGE_EXEC; |
166 | afeeceb0 | Edgar E. Iglesias | else if (rw == 2) { |
167 | afeeceb0 | Edgar E. Iglesias | goto done;
|
168 | afeeceb0 | Edgar E. Iglesias | } |
169 | afeeceb0 | Edgar E. Iglesias | |
170 | afeeceb0 | Edgar E. Iglesias | tlb_rpn = d & TLB_RPN_MASK; |
171 | afeeceb0 | Edgar E. Iglesias | |
172 | afeeceb0 | Edgar E. Iglesias | lu->vaddr = tlb_tag; |
173 | afeeceb0 | Edgar E. Iglesias | lu->paddr = tlb_rpn; |
174 | afeeceb0 | Edgar E. Iglesias | lu->size = tlb_size; |
175 | afeeceb0 | Edgar E. Iglesias | lu->err = ERR_HIT; |
176 | afeeceb0 | Edgar E. Iglesias | lu->idx = i; |
177 | afeeceb0 | Edgar E. Iglesias | hit = 1;
|
178 | afeeceb0 | Edgar E. Iglesias | goto done;
|
179 | afeeceb0 | Edgar E. Iglesias | } |
180 | afeeceb0 | Edgar E. Iglesias | } |
181 | afeeceb0 | Edgar E. Iglesias | done:
|
182 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
|
183 | afeeceb0 | Edgar E. Iglesias | vaddr, rw, tlb_wr, tlb_ex, hit)); |
184 | afeeceb0 | Edgar E. Iglesias | return hit;
|
185 | afeeceb0 | Edgar E. Iglesias | } |
186 | afeeceb0 | Edgar E. Iglesias | |
187 | afeeceb0 | Edgar E. Iglesias | /* Writes/reads to the MMU's special regs end up here. */
|
188 | afeeceb0 | Edgar E. Iglesias | uint32_t mmu_read(CPUState *env, uint32_t rn) |
189 | afeeceb0 | Edgar E. Iglesias | { |
190 | afeeceb0 | Edgar E. Iglesias | unsigned int i; |
191 | afeeceb0 | Edgar E. Iglesias | uint32_t r; |
192 | afeeceb0 | Edgar E. Iglesias | |
193 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { |
194 | 3c50a71f | Edgar E. Iglesias | qemu_log("MMU access on MMU-less system\n");
|
195 | 3c50a71f | Edgar E. Iglesias | return 0; |
196 | 3c50a71f | Edgar E. Iglesias | } |
197 | 3c50a71f | Edgar E. Iglesias | |
198 | afeeceb0 | Edgar E. Iglesias | switch (rn) {
|
199 | afeeceb0 | Edgar E. Iglesias | /* Reads to HI/LO trig reads from the mmu rams. */
|
200 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBLO:
|
201 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBHI:
|
202 | 3c50a71f | Edgar E. Iglesias | if (!(env->mmu.c_mmu_tlb_access & 1)) { |
203 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
|
204 | 3c50a71f | Edgar E. Iglesias | return 0; |
205 | 3c50a71f | Edgar E. Iglesias | } |
206 | 3c50a71f | Edgar E. Iglesias | |
207 | afeeceb0 | Edgar E. Iglesias | i = env->mmu.regs[MMU_R_TLBX] & 0xff;
|
208 | afeeceb0 | Edgar E. Iglesias | r = env->mmu.rams[rn & 1][i];
|
209 | afeeceb0 | Edgar E. Iglesias | if (rn == MMU_R_TLBHI)
|
210 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[MMU_R_PID] = env->mmu.tids[i]; |
211 | afeeceb0 | Edgar E. Iglesias | break;
|
212 | 3c50a71f | Edgar E. Iglesias | case MMU_R_PID:
|
213 | 3c50a71f | Edgar E. Iglesias | case MMU_R_ZPR:
|
214 | 3c50a71f | Edgar E. Iglesias | if (!(env->mmu.c_mmu_tlb_access & 1)) { |
215 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
|
216 | 3c50a71f | Edgar E. Iglesias | return 0; |
217 | 3c50a71f | Edgar E. Iglesias | } |
218 | 3c50a71f | Edgar E. Iglesias | r = env->mmu.regs[rn]; |
219 | 3c50a71f | Edgar E. Iglesias | break;
|
220 | afeeceb0 | Edgar E. Iglesias | default:
|
221 | afeeceb0 | Edgar E. Iglesias | r = env->mmu.regs[rn]; |
222 | afeeceb0 | Edgar E. Iglesias | break;
|
223 | afeeceb0 | Edgar E. Iglesias | } |
224 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
|
225 | afeeceb0 | Edgar E. Iglesias | return r;
|
226 | afeeceb0 | Edgar E. Iglesias | } |
227 | afeeceb0 | Edgar E. Iglesias | |
228 | afeeceb0 | Edgar E. Iglesias | void mmu_write(CPUState *env, uint32_t rn, uint32_t v)
|
229 | afeeceb0 | Edgar E. Iglesias | { |
230 | afeeceb0 | Edgar E. Iglesias | unsigned int i; |
231 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
|
232 | afeeceb0 | Edgar E. Iglesias | |
233 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { |
234 | 3c50a71f | Edgar E. Iglesias | qemu_log("MMU access on MMU-less system\n");
|
235 | 3c50a71f | Edgar E. Iglesias | return;
|
236 | 3c50a71f | Edgar E. Iglesias | } |
237 | 3c50a71f | Edgar E. Iglesias | |
238 | afeeceb0 | Edgar E. Iglesias | switch (rn) {
|
239 | afeeceb0 | Edgar E. Iglesias | /* Writes to HI/LO trig writes to the mmu rams. */
|
240 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBLO:
|
241 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBHI:
|
242 | afeeceb0 | Edgar E. Iglesias | i = env->mmu.regs[MMU_R_TLBX] & 0xff;
|
243 | afeeceb0 | Edgar E. Iglesias | if (rn == MMU_R_TLBHI) {
|
244 | afeeceb0 | Edgar E. Iglesias | if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) |
245 | afeeceb0 | Edgar E. Iglesias | qemu_log("invalidating index %x at pc=%x\n",
|
246 | afeeceb0 | Edgar E. Iglesias | i, env->sregs[SR_PC]); |
247 | afeeceb0 | Edgar E. Iglesias | env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
|
248 | afeeceb0 | Edgar E. Iglesias | mmu_flush_idx(env, i); |
249 | afeeceb0 | Edgar E. Iglesias | } |
250 | afeeceb0 | Edgar E. Iglesias | env->mmu.rams[rn & 1][i] = v;
|
251 | afeeceb0 | Edgar E. Iglesias | |
252 | afeeceb0 | Edgar E. Iglesias | D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v)); |
253 | afeeceb0 | Edgar E. Iglesias | break;
|
254 | afeeceb0 | Edgar E. Iglesias | case MMU_R_ZPR:
|
255 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu_tlb_access <= 1) { |
256 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
|
257 | 3c50a71f | Edgar E. Iglesias | return;
|
258 | 3c50a71f | Edgar E. Iglesias | } |
259 | 3c50a71f | Edgar E. Iglesias | |
260 | d0f3654f | Edgar E. Iglesias | /* Changes to the zone protection reg flush the QEMU TLB.
|
261 | d0f3654f | Edgar E. Iglesias | Fortunately, these are very uncommon. */
|
262 | d0f3654f | Edgar E. Iglesias | if (v != env->mmu.regs[rn]) {
|
263 | d0f3654f | Edgar E. Iglesias | tlb_flush(env, 1);
|
264 | d0f3654f | Edgar E. Iglesias | } |
265 | d0f3654f | Edgar E. Iglesias | env->mmu.regs[rn] = v; |
266 | d0f3654f | Edgar E. Iglesias | break;
|
267 | afeeceb0 | Edgar E. Iglesias | case MMU_R_PID:
|
268 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu_tlb_access <= 1) { |
269 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
|
270 | 3c50a71f | Edgar E. Iglesias | return;
|
271 | 3c50a71f | Edgar E. Iglesias | } |
272 | 3c50a71f | Edgar E. Iglesias | |
273 | afeeceb0 | Edgar E. Iglesias | if (v != env->mmu.regs[rn]) {
|
274 | afeeceb0 | Edgar E. Iglesias | mmu_change_pid(env, v); |
275 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[rn] = v; |
276 | afeeceb0 | Edgar E. Iglesias | } |
277 | afeeceb0 | Edgar E. Iglesias | break;
|
278 | afeeceb0 | Edgar E. Iglesias | case MMU_R_TLBSX:
|
279 | afeeceb0 | Edgar E. Iglesias | { |
280 | afeeceb0 | Edgar E. Iglesias | struct microblaze_mmu_lookup lu;
|
281 | afeeceb0 | Edgar E. Iglesias | int hit;
|
282 | 3c50a71f | Edgar E. Iglesias | |
283 | 3c50a71f | Edgar E. Iglesias | if (env->mmu.c_mmu_tlb_access <= 1) { |
284 | 3c50a71f | Edgar E. Iglesias | qemu_log("Invalid access to MMU reg %d\n", rn);
|
285 | 3c50a71f | Edgar E. Iglesias | return;
|
286 | 3c50a71f | Edgar E. Iglesias | } |
287 | 3c50a71f | Edgar E. Iglesias | |
288 | afeeceb0 | Edgar E. Iglesias | hit = mmu_translate(&env->mmu, &lu, |
289 | afeeceb0 | Edgar E. Iglesias | v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
|
290 | afeeceb0 | Edgar E. Iglesias | if (hit) {
|
291 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[MMU_R_TLBX] = lu.idx; |
292 | afeeceb0 | Edgar E. Iglesias | } else
|
293 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
|
294 | afeeceb0 | Edgar E. Iglesias | break;
|
295 | afeeceb0 | Edgar E. Iglesias | } |
296 | afeeceb0 | Edgar E. Iglesias | default:
|
297 | afeeceb0 | Edgar E. Iglesias | env->mmu.regs[rn] = v; |
298 | afeeceb0 | Edgar E. Iglesias | break;
|
299 | afeeceb0 | Edgar E. Iglesias | } |
300 | afeeceb0 | Edgar E. Iglesias | } |
301 | afeeceb0 | Edgar E. Iglesias | |
302 | afeeceb0 | Edgar E. Iglesias | void mmu_init(struct microblaze_mmu *mmu) |
303 | afeeceb0 | Edgar E. Iglesias | { |
304 | 3c50a71f | Edgar E. Iglesias | int i;
|
305 | 3c50a71f | Edgar E. Iglesias | for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) { |
306 | 3c50a71f | Edgar E. Iglesias | mmu->regs[i] = 0;
|
307 | 3c50a71f | Edgar E. Iglesias | } |
308 | afeeceb0 | Edgar E. Iglesias | } |