root / hw / arm_sysctl.c @ 283c7c63
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/*
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* Status and system control registers for ARM RealView/Versatile boards.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sysbus.h" |
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#include "primecell.h" |
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#include "sysemu.h" |
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#define LOCK_VALUE 0xa05f |
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typedef struct { |
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SysBusDevice busdev; |
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uint32_t sys_id; |
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uint32_t leds; |
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uint16_t lockval; |
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uint32_t cfgdata1; |
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uint32_t cfgdata2; |
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uint32_t flags; |
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uint32_t nvflags; |
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uint32_t resetlevel; |
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} arm_sysctl_state; |
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static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) |
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{
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arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
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switch (offset) {
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case 0x00: /* ID */ |
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return s->sys_id;
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case 0x04: /* SW */ |
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/* General purpose hardware switches.
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We don't have a useful way of exposing these to the user. */
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return 0; |
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case 0x08: /* LED */ |
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return s->leds;
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case 0x20: /* LOCK */ |
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return s->lockval;
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case 0x0c: /* OSC0 */ |
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case 0x10: /* OSC1 */ |
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case 0x14: /* OSC2 */ |
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case 0x18: /* OSC3 */ |
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case 0x1c: /* OSC4 */ |
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case 0x24: /* 100HZ */ |
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/* ??? Implement these. */
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return 0; |
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case 0x28: /* CFGDATA1 */ |
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return s->cfgdata1;
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case 0x2c: /* CFGDATA2 */ |
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return s->cfgdata2;
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case 0x30: /* FLAGS */ |
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return s->flags;
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case 0x38: /* NVFLAGS */ |
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return s->nvflags;
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case 0x40: /* RESETCTL */ |
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return s->resetlevel;
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case 0x44: /* PCICTL */ |
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return 1; |
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case 0x48: /* MCI */ |
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return 0; |
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case 0x4c: /* FLASH */ |
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return 0; |
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case 0x50: /* CLCD */ |
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return 0x1000; |
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case 0x54: /* CLCDSER */ |
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return 0; |
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case 0x58: /* BOOTCS */ |
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return 0; |
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case 0x5c: /* 24MHz */ |
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return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec()); |
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case 0x60: /* MISC */ |
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return 0; |
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case 0x84: /* PROCID0 */ |
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/* ??? Don't know what the proper value for the core tile ID is. */
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return 0x02000000; |
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case 0x88: /* PROCID1 */ |
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return 0xff000000; |
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case 0x64: /* DMAPSR0 */ |
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case 0x68: /* DMAPSR1 */ |
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case 0x6c: /* DMAPSR2 */ |
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case 0x70: /* IOSEL */ |
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case 0x74: /* PLDCTL */ |
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case 0x80: /* BUSID */ |
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case 0x8c: /* OSCRESET0 */ |
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case 0x90: /* OSCRESET1 */ |
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case 0x94: /* OSCRESET2 */ |
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case 0x98: /* OSCRESET3 */ |
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case 0x9c: /* OSCRESET4 */ |
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case 0xc0: /* SYS_TEST_OSC0 */ |
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case 0xc4: /* SYS_TEST_OSC1 */ |
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case 0xc8: /* SYS_TEST_OSC2 */ |
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case 0xcc: /* SYS_TEST_OSC3 */ |
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case 0xd0: /* SYS_TEST_OSC4 */ |
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return 0; |
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default:
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printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset); |
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return 0; |
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} |
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} |
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static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, |
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uint32_t val) |
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{
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arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
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switch (offset) {
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case 0x08: /* LED */ |
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s->leds = val; |
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case 0x0c: /* OSC0 */ |
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case 0x10: /* OSC1 */ |
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case 0x14: /* OSC2 */ |
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case 0x18: /* OSC3 */ |
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case 0x1c: /* OSC4 */ |
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/* ??? */
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break;
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case 0x20: /* LOCK */ |
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if (val == LOCK_VALUE)
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s->lockval = val; |
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else
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s->lockval = val & 0x7fff;
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break;
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case 0x28: /* CFGDATA1 */ |
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/* ??? Need to implement this. */
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s->cfgdata1 = val; |
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break;
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case 0x2c: /* CFGDATA2 */ |
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/* ??? Need to implement this. */
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s->cfgdata2 = val; |
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break;
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case 0x30: /* FLAGSSET */ |
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s->flags |= val; |
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break;
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case 0x34: /* FLAGSCLR */ |
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s->flags &= ~val; |
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break;
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case 0x38: /* NVFLAGSSET */ |
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s->nvflags |= val; |
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break;
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case 0x3c: /* NVFLAGSCLR */ |
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s->nvflags &= ~val; |
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break;
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case 0x40: /* RESETCTL */ |
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if (s->lockval == LOCK_VALUE) {
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s->resetlevel = val; |
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if (val & 0x100) |
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qemu_system_reset_request (); |
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} |
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break;
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case 0x44: /* PCICTL */ |
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/* nothing to do. */
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break;
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case 0x4c: /* FLASH */ |
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case 0x50: /* CLCD */ |
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case 0x54: /* CLCDSER */ |
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case 0x64: /* DMAPSR0 */ |
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case 0x68: /* DMAPSR1 */ |
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case 0x6c: /* DMAPSR2 */ |
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case 0x70: /* IOSEL */ |
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case 0x74: /* PLDCTL */ |
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case 0x80: /* BUSID */ |
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case 0x84: /* PROCID0 */ |
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case 0x88: /* PROCID1 */ |
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case 0x8c: /* OSCRESET0 */ |
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case 0x90: /* OSCRESET1 */ |
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case 0x94: /* OSCRESET2 */ |
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case 0x98: /* OSCRESET3 */ |
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case 0x9c: /* OSCRESET4 */ |
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break;
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default:
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printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); |
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return;
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} |
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} |
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static CPUReadMemoryFunc * const arm_sysctl_readfn[] = { |
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arm_sysctl_read, |
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arm_sysctl_read, |
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arm_sysctl_read |
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}; |
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static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = { |
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arm_sysctl_write, |
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arm_sysctl_write, |
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arm_sysctl_write |
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}; |
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static int arm_sysctl_init1(SysBusDevice *dev) |
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{
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arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); |
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int iomemtype;
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/* The MPcore bootloader uses these flags to start secondary CPUs.
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We don't use a bootloader, so do this here. */
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s->flags = 3;
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iomemtype = cpu_register_io_memory(arm_sysctl_readfn, |
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arm_sysctl_writefn, s); |
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sysbus_init_mmio(dev, 0x1000, iomemtype);
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/* ??? Save/restore. */
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return 0; |
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} |
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/* Legacy helper function. */
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void arm_sysctl_init(uint32_t base, uint32_t sys_id)
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{
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DeviceState *dev; |
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dev = qdev_create(NULL, "realview_sysctl"); |
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qdev_prop_set_uint32(dev, "sys_id", sys_id);
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qdev_init_nofail(dev); |
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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} |
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static SysBusDeviceInfo arm_sysctl_info = {
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.init = arm_sysctl_init1, |
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.qdev.name = "realview_sysctl",
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.qdev.size = sizeof(arm_sysctl_state),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), |
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DEFINE_PROP_END_OF_LIST(), |
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} |
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}; |
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static void arm_sysctl_register_devices(void) |
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{
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sysbus_register_withprop(&arm_sysctl_info); |
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} |
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device_init(arm_sysctl_register_devices) |