root / hw / usb-xhci.c @ 2850ca9e
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/*
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* USB xHCI controller emulation
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*
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* Copyright (c) 2011 Securiforest
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* Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
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* Based on usb-ohci.c, emulates Renesas NEC USB 3.0
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "usb.h" |
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#include "pci.h" |
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#include "qdev-addr.h" |
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#include "msi.h" |
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//#define DEBUG_XHCI
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//#define DEBUG_DATA
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#ifdef DEBUG_XHCI
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#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
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#else
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#define DPRINTF(...) do {} while (0) |
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#endif
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#define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ |
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__func__, __LINE__); abort(); } while (0) |
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#define MAXSLOTS 8 |
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#define MAXINTRS 1 |
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#define USB2_PORTS 4 |
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#define USB3_PORTS 4 |
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#define MAXPORTS (USB2_PORTS+USB3_PORTS)
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#define TD_QUEUE 24 |
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#define BG_XFERS 8 |
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#define BG_PKTS 8 |
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/* Very pessimistic, let's hope it's enough for all cases */
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#define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) |
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/* Do not deliver ER Full events. NEC's driver does some things not bound
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* to the specs when it gets them */
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#define ER_FULL_HACK
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#define LEN_CAP 0x40 |
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#define OFF_OPER LEN_CAP
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#define LEN_OPER (0x400 + 0x10 * MAXPORTS) |
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#define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f) |
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#define LEN_RUNTIME (0x20 + MAXINTRS * 0x20) |
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#define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
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#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) |
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/* must be power of 2 */
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#define LEN_REGS 0x2000 |
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#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
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# error Increase LEN_REGS
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#endif
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#if MAXINTRS > 1 |
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# error TODO: only one interrupter supported
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#endif
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/* bit definitions */
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#define USBCMD_RS (1<<0) |
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#define USBCMD_HCRST (1<<1) |
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#define USBCMD_INTE (1<<2) |
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#define USBCMD_HSEE (1<<3) |
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#define USBCMD_LHCRST (1<<7) |
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#define USBCMD_CSS (1<<8) |
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#define USBCMD_CRS (1<<9) |
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#define USBCMD_EWE (1<<10) |
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#define USBCMD_EU3S (1<<11) |
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#define USBSTS_HCH (1<<0) |
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#define USBSTS_HSE (1<<2) |
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#define USBSTS_EINT (1<<3) |
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#define USBSTS_PCD (1<<4) |
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#define USBSTS_SSS (1<<8) |
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#define USBSTS_RSS (1<<9) |
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#define USBSTS_SRE (1<<10) |
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#define USBSTS_CNR (1<<11) |
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#define USBSTS_HCE (1<<12) |
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#define PORTSC_CCS (1<<0) |
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#define PORTSC_PED (1<<1) |
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#define PORTSC_OCA (1<<3) |
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#define PORTSC_PR (1<<4) |
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#define PORTSC_PLS_SHIFT 5 |
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#define PORTSC_PLS_MASK 0xf |
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#define PORTSC_PP (1<<9) |
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#define PORTSC_SPEED_SHIFT 10 |
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#define PORTSC_SPEED_MASK 0xf |
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#define PORTSC_SPEED_FULL (1<<10) |
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#define PORTSC_SPEED_LOW (2<<10) |
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#define PORTSC_SPEED_HIGH (3<<10) |
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#define PORTSC_SPEED_SUPER (4<<10) |
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#define PORTSC_PIC_SHIFT 14 |
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#define PORTSC_PIC_MASK 0x3 |
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#define PORTSC_LWS (1<<16) |
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#define PORTSC_CSC (1<<17) |
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#define PORTSC_PEC (1<<18) |
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#define PORTSC_WRC (1<<19) |
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#define PORTSC_OCC (1<<20) |
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#define PORTSC_PRC (1<<21) |
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#define PORTSC_PLC (1<<22) |
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#define PORTSC_CEC (1<<23) |
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#define PORTSC_CAS (1<<24) |
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#define PORTSC_WCE (1<<25) |
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#define PORTSC_WDE (1<<26) |
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#define PORTSC_WOE (1<<27) |
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#define PORTSC_DR (1<<30) |
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#define PORTSC_WPR (1<<31) |
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#define CRCR_RCS (1<<0) |
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#define CRCR_CS (1<<1) |
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#define CRCR_CA (1<<2) |
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#define CRCR_CRR (1<<3) |
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#define IMAN_IP (1<<0) |
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#define IMAN_IE (1<<1) |
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#define ERDP_EHB (1<<3) |
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#define TRB_SIZE 16 |
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typedef struct XHCITRB { |
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uint64_t parameter; |
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uint32_t status; |
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uint32_t control; |
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target_phys_addr_t addr; |
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bool ccs;
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} XHCITRB; |
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typedef enum TRBType { |
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TRB_RESERVED = 0,
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TR_NORMAL, |
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TR_SETUP, |
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TR_DATA, |
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TR_STATUS, |
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TR_ISOCH, |
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TR_LINK, |
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TR_EVDATA, |
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TR_NOOP, |
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CR_ENABLE_SLOT, |
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CR_DISABLE_SLOT, |
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CR_ADDRESS_DEVICE, |
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CR_CONFIGURE_ENDPOINT, |
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CR_EVALUATE_CONTEXT, |
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CR_RESET_ENDPOINT, |
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CR_STOP_ENDPOINT, |
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CR_SET_TR_DEQUEUE, |
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CR_RESET_DEVICE, |
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CR_FORCE_EVENT, |
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CR_NEGOTIATE_BW, |
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CR_SET_LATENCY_TOLERANCE, |
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CR_GET_PORT_BANDWIDTH, |
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CR_FORCE_HEADER, |
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CR_NOOP, |
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ER_TRANSFER = 32,
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ER_COMMAND_COMPLETE, |
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ER_PORT_STATUS_CHANGE, |
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ER_BANDWIDTH_REQUEST, |
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ER_DOORBELL, |
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ER_HOST_CONTROLLER, |
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ER_DEVICE_NOTIFICATION, |
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ER_MFINDEX_WRAP, |
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/* vendor specific bits */
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CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
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CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
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CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
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} TRBType; |
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#define CR_LINK TR_LINK
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typedef enum TRBCCode { |
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CC_INVALID = 0,
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CC_SUCCESS, |
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CC_DATA_BUFFER_ERROR, |
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CC_BABBLE_DETECTED, |
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CC_USB_TRANSACTION_ERROR, |
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CC_TRB_ERROR, |
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CC_STALL_ERROR, |
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CC_RESOURCE_ERROR, |
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CC_BANDWIDTH_ERROR, |
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CC_NO_SLOTS_ERROR, |
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CC_INVALID_STREAM_TYPE_ERROR, |
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CC_SLOT_NOT_ENABLED_ERROR, |
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CC_EP_NOT_ENABLED_ERROR, |
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CC_SHORT_PACKET, |
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CC_RING_UNDERRUN, |
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CC_RING_OVERRUN, |
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CC_VF_ER_FULL, |
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CC_PARAMETER_ERROR, |
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CC_BANDWIDTH_OVERRUN, |
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CC_CONTEXT_STATE_ERROR, |
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CC_NO_PING_RESPONSE_ERROR, |
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CC_EVENT_RING_FULL_ERROR, |
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CC_INCOMPATIBLE_DEVICE_ERROR, |
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CC_MISSED_SERVICE_ERROR, |
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CC_COMMAND_RING_STOPPED, |
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CC_COMMAND_ABORTED, |
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CC_STOPPED, |
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CC_STOPPED_LENGTH_INVALID, |
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CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
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CC_ISOCH_BUFFER_OVERRUN = 31,
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CC_EVENT_LOST_ERROR, |
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CC_UNDEFINED_ERROR, |
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CC_INVALID_STREAM_ID_ERROR, |
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CC_SECONDARY_BANDWIDTH_ERROR, |
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CC_SPLIT_TRANSACTION_ERROR |
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} TRBCCode; |
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#define TRB_C (1<<0) |
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#define TRB_TYPE_SHIFT 10 |
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#define TRB_TYPE_MASK 0x3f |
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#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
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#define TRB_EV_ED (1<<2) |
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#define TRB_TR_ENT (1<<1) |
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#define TRB_TR_ISP (1<<2) |
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#define TRB_TR_NS (1<<3) |
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#define TRB_TR_CH (1<<4) |
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#define TRB_TR_IOC (1<<5) |
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#define TRB_TR_IDT (1<<6) |
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#define TRB_TR_TBC_SHIFT 7 |
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#define TRB_TR_TBC_MASK 0x3 |
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#define TRB_TR_BEI (1<<9) |
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#define TRB_TR_TLBPC_SHIFT 16 |
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#define TRB_TR_TLBPC_MASK 0xf |
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#define TRB_TR_FRAMEID_SHIFT 20 |
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#define TRB_TR_FRAMEID_MASK 0x7ff |
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#define TRB_TR_SIA (1<<31) |
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#define TRB_TR_DIR (1<<16) |
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#define TRB_CR_SLOTID_SHIFT 24 |
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#define TRB_CR_SLOTID_MASK 0xff |
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#define TRB_CR_EPID_SHIFT 16 |
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#define TRB_CR_EPID_MASK 0x1f |
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#define TRB_CR_BSR (1<<9) |
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#define TRB_CR_DC (1<<9) |
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#define TRB_LK_TC (1<<1) |
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#define EP_TYPE_MASK 0x7 |
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#define EP_TYPE_SHIFT 3 |
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#define EP_STATE_MASK 0x7 |
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#define EP_DISABLED (0<<0) |
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#define EP_RUNNING (1<<0) |
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#define EP_HALTED (2<<0) |
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#define EP_STOPPED (3<<0) |
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#define EP_ERROR (4<<0) |
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#define SLOT_STATE_MASK 0x1f |
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#define SLOT_STATE_SHIFT 27 |
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#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
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#define SLOT_ENABLED 0 |
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#define SLOT_DEFAULT 1 |
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#define SLOT_ADDRESSED 2 |
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#define SLOT_CONFIGURED 3 |
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#define SLOT_CONTEXT_ENTRIES_MASK 0x1f |
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#define SLOT_CONTEXT_ENTRIES_SHIFT 27 |
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typedef enum EPType { |
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ET_INVALID = 0,
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ET_ISO_OUT, |
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ET_BULK_OUT, |
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ET_INTR_OUT, |
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ET_CONTROL, |
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ET_ISO_IN, |
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ET_BULK_IN, |
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ET_INTR_IN, |
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} EPType; |
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typedef struct XHCIRing { |
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target_phys_addr_t base; |
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target_phys_addr_t dequeue; |
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bool ccs;
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} XHCIRing; |
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typedef struct XHCIPort { |
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USBPort port; |
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uint32_t portsc; |
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} XHCIPort; |
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struct XHCIState;
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typedef struct XHCIState XHCIState; |
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typedef struct XHCITransfer { |
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XHCIState *xhci; |
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USBPacket packet; |
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bool running_async;
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bool running_retry;
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bool cancelled;
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bool complete;
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bool backgrounded;
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unsigned int iso_pkts; |
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unsigned int slotid; |
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unsigned int epid; |
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bool in_xfer;
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bool iso_xfer;
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bool bg_xfer;
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unsigned int trb_count; |
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unsigned int trb_alloced; |
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XHCITRB *trbs; |
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unsigned int data_length; |
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unsigned int data_alloced; |
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uint8_t *data; |
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TRBCCode status; |
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unsigned int pkts; |
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unsigned int pktsize; |
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unsigned int cur_pkt; |
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} XHCITransfer; |
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typedef struct XHCIEPContext { |
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XHCIRing ring; |
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unsigned int next_xfer; |
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unsigned int comp_xfer; |
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XHCITransfer transfers[TD_QUEUE]; |
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XHCITransfer *retry; |
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bool bg_running;
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bool bg_updating;
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unsigned int next_bg; |
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XHCITransfer bg_transfers[BG_XFERS]; |
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EPType type; |
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target_phys_addr_t pctx; |
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unsigned int max_psize; |
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bool has_bg;
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uint32_t state; |
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} XHCIEPContext; |
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typedef struct XHCISlot { |
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bool enabled;
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target_phys_addr_t ctx; |
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unsigned int port; |
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unsigned int devaddr; |
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XHCIEPContext * eps[31];
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} XHCISlot; |
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typedef struct XHCIEvent { |
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TRBType type; |
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TRBCCode ccode; |
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uint64_t ptr; |
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uint32_t length; |
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uint32_t flags; |
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uint8_t slotid; |
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uint8_t epid; |
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} XHCIEvent; |
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struct XHCIState {
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PCIDevice pci_dev; |
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USBBus bus; |
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qemu_irq irq; |
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MemoryRegion mem; |
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const char *name; |
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uint32_t msi; |
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unsigned int devaddr; |
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/* Operational Registers */
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uint32_t usbcmd; |
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uint32_t usbsts; |
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uint32_t dnctrl; |
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uint32_t crcr_low; |
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uint32_t crcr_high; |
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uint32_t dcbaap_low; |
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uint32_t dcbaap_high; |
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uint32_t config; |
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XHCIPort ports[MAXPORTS]; |
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XHCISlot slots[MAXSLOTS]; |
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/* Runtime Registers */
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uint32_t mfindex; |
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/* note: we only support one interrupter */
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uint32_t iman; |
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uint32_t imod; |
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uint32_t erstsz; |
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uint32_t erstba_low; |
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uint32_t erstba_high; |
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uint32_t erdp_low; |
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uint32_t erdp_high; |
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target_phys_addr_t er_start; |
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uint32_t er_size; |
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bool er_pcs;
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unsigned int er_ep_idx; |
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bool er_full;
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XHCIEvent ev_buffer[EV_QUEUE]; |
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unsigned int ev_buffer_put; |
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unsigned int ev_buffer_get; |
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|
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XHCIRing cmd_ring; |
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}; |
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|
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typedef struct XHCIEvRingSeg { |
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uint32_t addr_low; |
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uint32_t addr_high; |
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uint32_t size; |
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uint32_t rsvd; |
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} XHCIEvRingSeg; |
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|
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#ifdef DEBUG_XHCI
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static const char *TRBType_names[] = { |
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[TRB_RESERVED] = "TRB_RESERVED",
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[TR_NORMAL] = "TR_NORMAL",
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[TR_SETUP] = "TR_SETUP",
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[TR_DATA] = "TR_DATA",
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[TR_STATUS] = "TR_STATUS",
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[TR_ISOCH] = "TR_ISOCH",
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[TR_LINK] = "TR_LINK",
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[TR_EVDATA] = "TR_EVDATA",
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[TR_NOOP] = "TR_NOOP",
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[CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
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[CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
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[CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
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[CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
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[CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
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[CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
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[CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
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[CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
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[CR_RESET_DEVICE] = "CR_RESET_DEVICE",
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[CR_FORCE_EVENT] = "CR_FORCE_EVENT",
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[CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
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[CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
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[CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
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[CR_FORCE_HEADER] = "CR_FORCE_HEADER",
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[CR_NOOP] = "CR_NOOP",
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[ER_TRANSFER] = "ER_TRANSFER",
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[ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
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[ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
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[ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
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[ER_DOORBELL] = "ER_DOORBELL",
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[ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
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[ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
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[ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
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[CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
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[CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
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[CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
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}; |
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|
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static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) |
465 |
{ |
466 |
if (index >= llen || list[index] == NULL) { |
467 |
return "???"; |
468 |
} |
469 |
return list[index];
|
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} |
471 |
|
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static const char *trb_name(XHCITRB *trb) |
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{ |
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return lookup_name(TRB_TYPE(*trb), TRBType_names,
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ARRAY_SIZE(TRBType_names)); |
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} |
477 |
#endif
|
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|
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static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
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unsigned int epid); |
481 |
|
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static inline target_phys_addr_t xhci_addr64(uint32_t low, uint32_t high) |
483 |
{ |
484 |
#if TARGET_PHYS_ADDR_BITS > 32 |
485 |
return low | ((target_phys_addr_t)high << 32); |
486 |
#else
|
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return low;
|
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#endif
|
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} |
490 |
|
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static inline target_phys_addr_t xhci_mask64(uint64_t addr) |
492 |
{ |
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#if TARGET_PHYS_ADDR_BITS > 32 |
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return addr;
|
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#else
|
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return addr & 0xffffffff; |
497 |
#endif
|
498 |
} |
499 |
|
500 |
static void xhci_irq_update(XHCIState *xhci) |
501 |
{ |
502 |
int level = 0; |
503 |
|
504 |
if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
|
505 |
xhci->usbcmd && USBCMD_INTE) { |
506 |
level = 1;
|
507 |
} |
508 |
|
509 |
DPRINTF("xhci_irq_update(): %d\n", level);
|
510 |
|
511 |
if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
|
512 |
if (level) {
|
513 |
DPRINTF("xhci_irq_update(): MSI signal\n");
|
514 |
msi_notify(&xhci->pci_dev, 0);
|
515 |
} |
516 |
} else {
|
517 |
qemu_set_irq(xhci->irq, level); |
518 |
} |
519 |
} |
520 |
|
521 |
static inline int xhci_running(XHCIState *xhci) |
522 |
{ |
523 |
return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
|
524 |
} |
525 |
|
526 |
static void xhci_die(XHCIState *xhci) |
527 |
{ |
528 |
xhci->usbsts |= USBSTS_HCE; |
529 |
fprintf(stderr, "xhci: asserted controller error\n");
|
530 |
} |
531 |
|
532 |
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event) |
533 |
{ |
534 |
XHCITRB ev_trb; |
535 |
target_phys_addr_t addr; |
536 |
|
537 |
ev_trb.parameter = cpu_to_le64(event->ptr); |
538 |
ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
|
539 |
ev_trb.control = (event->slotid << 24) | (event->epid << 16) | |
540 |
event->flags | (event->type << TRB_TYPE_SHIFT); |
541 |
if (xhci->er_pcs) {
|
542 |
ev_trb.control |= TRB_C; |
543 |
} |
544 |
ev_trb.control = cpu_to_le32(ev_trb.control); |
545 |
|
546 |
DPRINTF("xhci_write_event(): [%d] %016"PRIx64" %08x %08x %s\n", |
547 |
xhci->er_ep_idx, ev_trb.parameter, ev_trb.status, ev_trb.control, |
548 |
trb_name(&ev_trb)); |
549 |
|
550 |
addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx; |
551 |
cpu_physical_memory_write(addr, (uint8_t *) &ev_trb, TRB_SIZE); |
552 |
|
553 |
xhci->er_ep_idx++; |
554 |
if (xhci->er_ep_idx >= xhci->er_size) {
|
555 |
xhci->er_ep_idx = 0;
|
556 |
xhci->er_pcs = !xhci->er_pcs; |
557 |
} |
558 |
} |
559 |
|
560 |
static void xhci_events_update(XHCIState *xhci) |
561 |
{ |
562 |
target_phys_addr_t erdp; |
563 |
unsigned int dp_idx; |
564 |
bool do_irq = 0; |
565 |
|
566 |
if (xhci->usbsts & USBSTS_HCH) {
|
567 |
return;
|
568 |
} |
569 |
|
570 |
erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high); |
571 |
if (erdp < xhci->er_start ||
|
572 |
erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) { |
573 |
fprintf(stderr, "xhci: ERDP out of bounds: "TARGET_FMT_plx"\n", erdp); |
574 |
fprintf(stderr, "xhci: ER at "TARGET_FMT_plx" len %d\n", |
575 |
xhci->er_start, xhci->er_size); |
576 |
xhci_die(xhci); |
577 |
return;
|
578 |
} |
579 |
dp_idx = (erdp - xhci->er_start) / TRB_SIZE; |
580 |
assert(dp_idx < xhci->er_size); |
581 |
|
582 |
/* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
|
583 |
* deadlocks when the ER is full. Hack it by holding off events until
|
584 |
* the driver decides to free at least half of the ring */
|
585 |
if (xhci->er_full) {
|
586 |
int er_free = dp_idx - xhci->er_ep_idx;
|
587 |
if (er_free <= 0) { |
588 |
er_free += xhci->er_size; |
589 |
} |
590 |
if (er_free < (xhci->er_size/2)) { |
591 |
DPRINTF("xhci_events_update(): event ring still "
|
592 |
"more than half full (hack)\n");
|
593 |
return;
|
594 |
} |
595 |
} |
596 |
|
597 |
while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
|
598 |
assert(xhci->er_full); |
599 |
if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) { |
600 |
DPRINTF("xhci_events_update(): event ring full again\n");
|
601 |
#ifndef ER_FULL_HACK
|
602 |
XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; |
603 |
xhci_write_event(xhci, &full); |
604 |
#endif
|
605 |
do_irq = 1;
|
606 |
break;
|
607 |
} |
608 |
XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get]; |
609 |
xhci_write_event(xhci, event); |
610 |
xhci->ev_buffer_get++; |
611 |
do_irq = 1;
|
612 |
if (xhci->ev_buffer_get == EV_QUEUE) {
|
613 |
xhci->ev_buffer_get = 0;
|
614 |
} |
615 |
} |
616 |
|
617 |
if (do_irq) {
|
618 |
xhci->erdp_low |= ERDP_EHB; |
619 |
xhci->iman |= IMAN_IP; |
620 |
xhci->usbsts |= USBSTS_EINT; |
621 |
xhci_irq_update(xhci); |
622 |
} |
623 |
|
624 |
if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
|
625 |
DPRINTF("xhci_events_update(): event ring no longer full\n");
|
626 |
xhci->er_full = 0;
|
627 |
} |
628 |
return;
|
629 |
} |
630 |
|
631 |
static void xhci_event(XHCIState *xhci, XHCIEvent *event) |
632 |
{ |
633 |
target_phys_addr_t erdp; |
634 |
unsigned int dp_idx; |
635 |
|
636 |
if (xhci->er_full) {
|
637 |
DPRINTF("xhci_event(): ER full, queueing\n");
|
638 |
if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) { |
639 |
fprintf(stderr, "xhci: event queue full, dropping event!\n");
|
640 |
return;
|
641 |
} |
642 |
xhci->ev_buffer[xhci->ev_buffer_put++] = *event; |
643 |
if (xhci->ev_buffer_put == EV_QUEUE) {
|
644 |
xhci->ev_buffer_put = 0;
|
645 |
} |
646 |
return;
|
647 |
} |
648 |
|
649 |
erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high); |
650 |
if (erdp < xhci->er_start ||
|
651 |
erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) { |
652 |
fprintf(stderr, "xhci: ERDP out of bounds: "TARGET_FMT_plx"\n", erdp); |
653 |
fprintf(stderr, "xhci: ER at "TARGET_FMT_plx" len %d\n", |
654 |
xhci->er_start, xhci->er_size); |
655 |
xhci_die(xhci); |
656 |
return;
|
657 |
} |
658 |
|
659 |
dp_idx = (erdp - xhci->er_start) / TRB_SIZE; |
660 |
assert(dp_idx < xhci->er_size); |
661 |
|
662 |
if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) { |
663 |
DPRINTF("xhci_event(): ER full, queueing\n");
|
664 |
#ifndef ER_FULL_HACK
|
665 |
XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; |
666 |
xhci_write_event(xhci, &full); |
667 |
#endif
|
668 |
xhci->er_full = 1;
|
669 |
if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) { |
670 |
fprintf(stderr, "xhci: event queue full, dropping event!\n");
|
671 |
return;
|
672 |
} |
673 |
xhci->ev_buffer[xhci->ev_buffer_put++] = *event; |
674 |
if (xhci->ev_buffer_put == EV_QUEUE) {
|
675 |
xhci->ev_buffer_put = 0;
|
676 |
} |
677 |
} else {
|
678 |
xhci_write_event(xhci, event); |
679 |
} |
680 |
|
681 |
xhci->erdp_low |= ERDP_EHB; |
682 |
xhci->iman |= IMAN_IP; |
683 |
xhci->usbsts |= USBSTS_EINT; |
684 |
|
685 |
xhci_irq_update(xhci); |
686 |
} |
687 |
|
688 |
static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, |
689 |
target_phys_addr_t base) |
690 |
{ |
691 |
ring->base = base; |
692 |
ring->dequeue = base; |
693 |
ring->ccs = 1;
|
694 |
} |
695 |
|
696 |
static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
|
697 |
target_phys_addr_t *addr) |
698 |
{ |
699 |
while (1) { |
700 |
TRBType type; |
701 |
cpu_physical_memory_read(ring->dequeue, (uint8_t *) trb, TRB_SIZE); |
702 |
trb->addr = ring->dequeue; |
703 |
trb->ccs = ring->ccs; |
704 |
le64_to_cpus(&trb->parameter); |
705 |
le32_to_cpus(&trb->status); |
706 |
le32_to_cpus(&trb->control); |
707 |
|
708 |
DPRINTF("xhci: TRB fetched [" TARGET_FMT_plx "]: " |
709 |
"%016" PRIx64 " %08x %08x %s\n", |
710 |
ring->dequeue, trb->parameter, trb->status, trb->control, |
711 |
trb_name(trb)); |
712 |
|
713 |
if ((trb->control & TRB_C) != ring->ccs) {
|
714 |
return 0; |
715 |
} |
716 |
|
717 |
type = TRB_TYPE(*trb); |
718 |
|
719 |
if (type != TR_LINK) {
|
720 |
if (addr) {
|
721 |
*addr = ring->dequeue; |
722 |
} |
723 |
ring->dequeue += TRB_SIZE; |
724 |
return type;
|
725 |
} else {
|
726 |
ring->dequeue = xhci_mask64(trb->parameter); |
727 |
if (trb->control & TRB_LK_TC) {
|
728 |
ring->ccs = !ring->ccs; |
729 |
} |
730 |
} |
731 |
} |
732 |
} |
733 |
|
734 |
static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) |
735 |
{ |
736 |
XHCITRB trb; |
737 |
int length = 0; |
738 |
target_phys_addr_t dequeue = ring->dequeue; |
739 |
bool ccs = ring->ccs;
|
740 |
/* hack to bundle together the two/three TDs that make a setup transfer */
|
741 |
bool control_td_set = 0; |
742 |
|
743 |
while (1) { |
744 |
TRBType type; |
745 |
cpu_physical_memory_read(dequeue, (uint8_t *) &trb, TRB_SIZE); |
746 |
le64_to_cpus(&trb.parameter); |
747 |
le32_to_cpus(&trb.status); |
748 |
le32_to_cpus(&trb.control); |
749 |
|
750 |
DPRINTF("xhci: TRB peeked [" TARGET_FMT_plx "]: " |
751 |
"%016" PRIx64 " %08x %08x\n", |
752 |
dequeue, trb.parameter, trb.status, trb.control); |
753 |
|
754 |
if ((trb.control & TRB_C) != ccs) {
|
755 |
return -length;
|
756 |
} |
757 |
|
758 |
type = TRB_TYPE(trb); |
759 |
|
760 |
if (type == TR_LINK) {
|
761 |
dequeue = xhci_mask64(trb.parameter); |
762 |
if (trb.control & TRB_LK_TC) {
|
763 |
ccs = !ccs; |
764 |
} |
765 |
continue;
|
766 |
} |
767 |
|
768 |
length += 1;
|
769 |
dequeue += TRB_SIZE; |
770 |
|
771 |
if (type == TR_SETUP) {
|
772 |
control_td_set = 1;
|
773 |
} else if (type == TR_STATUS) { |
774 |
control_td_set = 0;
|
775 |
} |
776 |
|
777 |
if (!control_td_set && !(trb.control & TRB_TR_CH)) {
|
778 |
return length;
|
779 |
} |
780 |
} |
781 |
} |
782 |
|
783 |
static void xhci_er_reset(XHCIState *xhci) |
784 |
{ |
785 |
XHCIEvRingSeg seg; |
786 |
|
787 |
/* cache the (sole) event ring segment location */
|
788 |
if (xhci->erstsz != 1) { |
789 |
fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
|
790 |
xhci_die(xhci); |
791 |
return;
|
792 |
} |
793 |
target_phys_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high); |
794 |
cpu_physical_memory_read(erstba, (uint8_t *) &seg, sizeof(seg));
|
795 |
le32_to_cpus(&seg.addr_low); |
796 |
le32_to_cpus(&seg.addr_high); |
797 |
le32_to_cpus(&seg.size); |
798 |
if (seg.size < 16 || seg.size > 4096) { |
799 |
fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
|
800 |
xhci_die(xhci); |
801 |
return;
|
802 |
} |
803 |
xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high); |
804 |
xhci->er_size = seg.size; |
805 |
|
806 |
xhci->er_ep_idx = 0;
|
807 |
xhci->er_pcs = 1;
|
808 |
xhci->er_full = 0;
|
809 |
|
810 |
DPRINTF("xhci: event ring:" TARGET_FMT_plx " [%d]\n", |
811 |
xhci->er_start, xhci->er_size); |
812 |
} |
813 |
|
814 |
static void xhci_run(XHCIState *xhci) |
815 |
{ |
816 |
DPRINTF("xhci_run()\n");
|
817 |
|
818 |
xhci->usbsts &= ~USBSTS_HCH; |
819 |
} |
820 |
|
821 |
static void xhci_stop(XHCIState *xhci) |
822 |
{ |
823 |
DPRINTF("xhci_stop()\n");
|
824 |
xhci->usbsts |= USBSTS_HCH; |
825 |
xhci->crcr_low &= ~CRCR_CRR; |
826 |
} |
827 |
|
828 |
static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, |
829 |
uint32_t state) |
830 |
{ |
831 |
uint32_t ctx[5];
|
832 |
if (epctx->state == state) {
|
833 |
return;
|
834 |
} |
835 |
|
836 |
cpu_physical_memory_read(epctx->pctx, (uint8_t *) ctx, sizeof(ctx));
|
837 |
ctx[0] &= ~EP_STATE_MASK;
|
838 |
ctx[0] |= state;
|
839 |
ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
|
840 |
ctx[3] = (epctx->ring.dequeue >> 16) >> 16; |
841 |
DPRINTF("xhci: set epctx: " TARGET_FMT_plx " state=%d dequeue=%08x%08x\n", |
842 |
epctx->pctx, state, ctx[3], ctx[2]); |
843 |
cpu_physical_memory_write(epctx->pctx, (uint8_t *) ctx, sizeof(ctx));
|
844 |
epctx->state = state; |
845 |
} |
846 |
|
847 |
static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, |
848 |
unsigned int epid, target_phys_addr_t pctx, |
849 |
uint32_t *ctx) |
850 |
{ |
851 |
XHCISlot *slot; |
852 |
XHCIEPContext *epctx; |
853 |
target_phys_addr_t dequeue; |
854 |
int i;
|
855 |
|
856 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
857 |
assert(epid >= 1 && epid <= 31); |
858 |
|
859 |
DPRINTF("xhci_enable_ep(%d, %d)\n", slotid, epid);
|
860 |
|
861 |
slot = &xhci->slots[slotid-1];
|
862 |
if (slot->eps[epid-1]) { |
863 |
fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
|
864 |
return CC_TRB_ERROR;
|
865 |
} |
866 |
|
867 |
epctx = g_malloc(sizeof(XHCIEPContext));
|
868 |
memset(epctx, 0, sizeof(XHCIEPContext)); |
869 |
|
870 |
slot->eps[epid-1] = epctx;
|
871 |
|
872 |
dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); |
873 |
xhci_ring_init(xhci, &epctx->ring, dequeue); |
874 |
epctx->ring.ccs = ctx[2] & 1; |
875 |
|
876 |
epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
|
877 |
DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); |
878 |
epctx->pctx = pctx; |
879 |
epctx->max_psize = ctx[1]>>16; |
880 |
epctx->max_psize *= 1+((ctx[1]>>8)&0xff); |
881 |
epctx->has_bg = false;
|
882 |
if (epctx->type == ET_ISO_IN) {
|
883 |
epctx->has_bg = true;
|
884 |
} |
885 |
DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
|
886 |
epid/2, epid%2, epctx->max_psize); |
887 |
for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { |
888 |
usb_packet_init(&epctx->transfers[i].packet); |
889 |
} |
890 |
|
891 |
epctx->state = EP_RUNNING; |
892 |
ctx[0] &= ~EP_STATE_MASK;
|
893 |
ctx[0] |= EP_RUNNING;
|
894 |
|
895 |
return CC_SUCCESS;
|
896 |
} |
897 |
|
898 |
static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, |
899 |
unsigned int epid) |
900 |
{ |
901 |
XHCISlot *slot; |
902 |
XHCIEPContext *epctx; |
903 |
int i, xferi, killed = 0; |
904 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
905 |
assert(epid >= 1 && epid <= 31); |
906 |
|
907 |
DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
|
908 |
|
909 |
slot = &xhci->slots[slotid-1];
|
910 |
|
911 |
if (!slot->eps[epid-1]) { |
912 |
return 0; |
913 |
} |
914 |
|
915 |
epctx = slot->eps[epid-1];
|
916 |
|
917 |
xferi = epctx->next_xfer; |
918 |
for (i = 0; i < TD_QUEUE; i++) { |
919 |
XHCITransfer *t = &epctx->transfers[xferi]; |
920 |
if (t->running_async) {
|
921 |
usb_cancel_packet(&t->packet); |
922 |
t->running_async = 0;
|
923 |
t->cancelled = 1;
|
924 |
DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
|
925 |
killed++; |
926 |
} |
927 |
if (t->running_retry) {
|
928 |
t->running_retry = 0;
|
929 |
epctx->retry = NULL;
|
930 |
} |
931 |
if (t->backgrounded) {
|
932 |
t->backgrounded = 0;
|
933 |
} |
934 |
if (t->trbs) {
|
935 |
g_free(t->trbs); |
936 |
} |
937 |
if (t->data) {
|
938 |
g_free(t->data); |
939 |
} |
940 |
|
941 |
t->trbs = NULL;
|
942 |
t->data = NULL;
|
943 |
t->trb_count = t->trb_alloced = 0;
|
944 |
t->data_length = t->data_alloced = 0;
|
945 |
xferi = (xferi + 1) % TD_QUEUE;
|
946 |
} |
947 |
if (epctx->has_bg) {
|
948 |
xferi = epctx->next_bg; |
949 |
for (i = 0; i < BG_XFERS; i++) { |
950 |
XHCITransfer *t = &epctx->bg_transfers[xferi]; |
951 |
if (t->running_async) {
|
952 |
usb_cancel_packet(&t->packet); |
953 |
t->running_async = 0;
|
954 |
t->cancelled = 1;
|
955 |
DPRINTF("xhci: cancelling bg transfer %d, waiting for it to complete...\n", i);
|
956 |
killed++; |
957 |
} |
958 |
if (t->data) {
|
959 |
g_free(t->data); |
960 |
} |
961 |
|
962 |
t->data = NULL;
|
963 |
xferi = (xferi + 1) % BG_XFERS;
|
964 |
} |
965 |
} |
966 |
return killed;
|
967 |
} |
968 |
|
969 |
static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, |
970 |
unsigned int epid) |
971 |
{ |
972 |
XHCISlot *slot; |
973 |
XHCIEPContext *epctx; |
974 |
|
975 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
976 |
assert(epid >= 1 && epid <= 31); |
977 |
|
978 |
DPRINTF("xhci_disable_ep(%d, %d)\n", slotid, epid);
|
979 |
|
980 |
slot = &xhci->slots[slotid-1];
|
981 |
|
982 |
if (!slot->eps[epid-1]) { |
983 |
DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
|
984 |
return CC_SUCCESS;
|
985 |
} |
986 |
|
987 |
xhci_ep_nuke_xfers(xhci, slotid, epid); |
988 |
|
989 |
epctx = slot->eps[epid-1];
|
990 |
|
991 |
xhci_set_ep_state(xhci, epctx, EP_DISABLED); |
992 |
|
993 |
g_free(epctx); |
994 |
slot->eps[epid-1] = NULL; |
995 |
|
996 |
return CC_SUCCESS;
|
997 |
} |
998 |
|
999 |
static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, |
1000 |
unsigned int epid) |
1001 |
{ |
1002 |
XHCISlot *slot; |
1003 |
XHCIEPContext *epctx; |
1004 |
|
1005 |
DPRINTF("xhci_stop_ep(%d, %d)\n", slotid, epid);
|
1006 |
|
1007 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1008 |
|
1009 |
if (epid < 1 || epid > 31) { |
1010 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
1011 |
return CC_TRB_ERROR;
|
1012 |
} |
1013 |
|
1014 |
slot = &xhci->slots[slotid-1];
|
1015 |
|
1016 |
if (!slot->eps[epid-1]) { |
1017 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
1018 |
return CC_EP_NOT_ENABLED_ERROR;
|
1019 |
} |
1020 |
|
1021 |
if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { |
1022 |
fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
|
1023 |
"data might be lost\n");
|
1024 |
} |
1025 |
|
1026 |
epctx = slot->eps[epid-1];
|
1027 |
|
1028 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
1029 |
|
1030 |
return CC_SUCCESS;
|
1031 |
} |
1032 |
|
1033 |
static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, |
1034 |
unsigned int epid) |
1035 |
{ |
1036 |
XHCISlot *slot; |
1037 |
XHCIEPContext *epctx; |
1038 |
USBDevice *dev; |
1039 |
|
1040 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1041 |
|
1042 |
DPRINTF("xhci_reset_ep(%d, %d)\n", slotid, epid);
|
1043 |
|
1044 |
if (epid < 1 || epid > 31) { |
1045 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
1046 |
return CC_TRB_ERROR;
|
1047 |
} |
1048 |
|
1049 |
slot = &xhci->slots[slotid-1];
|
1050 |
|
1051 |
if (!slot->eps[epid-1]) { |
1052 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
1053 |
return CC_EP_NOT_ENABLED_ERROR;
|
1054 |
} |
1055 |
|
1056 |
epctx = slot->eps[epid-1];
|
1057 |
|
1058 |
if (epctx->state != EP_HALTED) {
|
1059 |
fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
|
1060 |
epid, epctx->state); |
1061 |
return CC_CONTEXT_STATE_ERROR;
|
1062 |
} |
1063 |
|
1064 |
if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { |
1065 |
fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
|
1066 |
"data might be lost\n");
|
1067 |
} |
1068 |
|
1069 |
uint8_t ep = epid>>1;
|
1070 |
|
1071 |
if (epid & 1) { |
1072 |
ep |= 0x80;
|
1073 |
} |
1074 |
|
1075 |
dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev; |
1076 |
if (!dev) {
|
1077 |
return CC_USB_TRANSACTION_ERROR;
|
1078 |
} |
1079 |
|
1080 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
1081 |
|
1082 |
return CC_SUCCESS;
|
1083 |
} |
1084 |
|
1085 |
static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, |
1086 |
unsigned int epid, uint64_t pdequeue) |
1087 |
{ |
1088 |
XHCISlot *slot; |
1089 |
XHCIEPContext *epctx; |
1090 |
target_phys_addr_t dequeue; |
1091 |
|
1092 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1093 |
|
1094 |
if (epid < 1 || epid > 31) { |
1095 |
fprintf(stderr, "xhci: bad ep %d\n", epid);
|
1096 |
return CC_TRB_ERROR;
|
1097 |
} |
1098 |
|
1099 |
DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64")\n", slotid, epid, pdequeue); |
1100 |
dequeue = xhci_mask64(pdequeue); |
1101 |
|
1102 |
slot = &xhci->slots[slotid-1];
|
1103 |
|
1104 |
if (!slot->eps[epid-1]) { |
1105 |
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
|
1106 |
return CC_EP_NOT_ENABLED_ERROR;
|
1107 |
} |
1108 |
|
1109 |
epctx = slot->eps[epid-1];
|
1110 |
|
1111 |
|
1112 |
if (epctx->state != EP_STOPPED) {
|
1113 |
fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
|
1114 |
return CC_CONTEXT_STATE_ERROR;
|
1115 |
} |
1116 |
|
1117 |
xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
|
1118 |
epctx->ring.ccs = dequeue & 1;
|
1119 |
|
1120 |
xhci_set_ep_state(xhci, epctx, EP_STOPPED); |
1121 |
|
1122 |
return CC_SUCCESS;
|
1123 |
} |
1124 |
|
1125 |
static int xhci_xfer_data(XHCITransfer *xfer, uint8_t *data, |
1126 |
unsigned int length, bool in_xfer, bool out_xfer, |
1127 |
bool report)
|
1128 |
{ |
1129 |
int i;
|
1130 |
uint32_t edtla = 0;
|
1131 |
unsigned int transferred = 0; |
1132 |
unsigned int left = length; |
1133 |
bool reported = 0; |
1134 |
bool shortpkt = 0; |
1135 |
XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; |
1136 |
XHCIState *xhci = xfer->xhci; |
1137 |
|
1138 |
DPRINTF("xhci_xfer_data(len=%d, in_xfer=%d, out_xfer=%d, report=%d)\n",
|
1139 |
length, in_xfer, out_xfer, report); |
1140 |
|
1141 |
assert(!(in_xfer && out_xfer)); |
1142 |
|
1143 |
for (i = 0; i < xfer->trb_count; i++) { |
1144 |
XHCITRB *trb = &xfer->trbs[i]; |
1145 |
target_phys_addr_t addr; |
1146 |
unsigned int chunk = 0; |
1147 |
|
1148 |
switch (TRB_TYPE(*trb)) {
|
1149 |
case TR_DATA:
|
1150 |
if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
|
1151 |
fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
|
1152 |
xhci_die(xhci); |
1153 |
return transferred;
|
1154 |
} |
1155 |
/* fallthrough */
|
1156 |
case TR_NORMAL:
|
1157 |
case TR_ISOCH:
|
1158 |
addr = xhci_mask64(trb->parameter); |
1159 |
chunk = trb->status & 0x1ffff;
|
1160 |
if (chunk > left) {
|
1161 |
chunk = left; |
1162 |
shortpkt = 1;
|
1163 |
} |
1164 |
if (in_xfer || out_xfer) {
|
1165 |
if (trb->control & TRB_TR_IDT) {
|
1166 |
uint64_t idata; |
1167 |
if (chunk > 8 || in_xfer) { |
1168 |
fprintf(stderr, "xhci: invalid immediate data TRB\n");
|
1169 |
xhci_die(xhci); |
1170 |
return transferred;
|
1171 |
} |
1172 |
idata = le64_to_cpu(trb->parameter); |
1173 |
memcpy(data, &idata, chunk); |
1174 |
} else {
|
1175 |
DPRINTF("xhci_xfer_data: r/w(%d) %d bytes at "
|
1176 |
TARGET_FMT_plx "\n", in_xfer, chunk, addr);
|
1177 |
if (in_xfer) {
|
1178 |
cpu_physical_memory_write(addr, data, chunk); |
1179 |
} else {
|
1180 |
cpu_physical_memory_read(addr, data, chunk); |
1181 |
} |
1182 |
#ifdef DEBUG_DATA
|
1183 |
unsigned int count = chunk; |
1184 |
int i;
|
1185 |
if (count > 16) { |
1186 |
count = 16;
|
1187 |
} |
1188 |
DPRINTF(" ::");
|
1189 |
for (i = 0; i < count; i++) { |
1190 |
DPRINTF(" %02x", data[i]);
|
1191 |
} |
1192 |
DPRINTF("\n");
|
1193 |
#endif
|
1194 |
} |
1195 |
} |
1196 |
left -= chunk; |
1197 |
data += chunk; |
1198 |
edtla += chunk; |
1199 |
transferred += chunk; |
1200 |
break;
|
1201 |
case TR_STATUS:
|
1202 |
reported = 0;
|
1203 |
shortpkt = 0;
|
1204 |
break;
|
1205 |
} |
1206 |
|
1207 |
if (report && !reported && (trb->control & TRB_TR_IOC ||
|
1208 |
(shortpkt && (trb->control & TRB_TR_ISP)))) { |
1209 |
event.slotid = xfer->slotid; |
1210 |
event.epid = xfer->epid; |
1211 |
event.length = (trb->status & 0x1ffff) - chunk;
|
1212 |
event.flags = 0;
|
1213 |
event.ptr = trb->addr; |
1214 |
if (xfer->status == CC_SUCCESS) {
|
1215 |
event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; |
1216 |
} else {
|
1217 |
event.ccode = xfer->status; |
1218 |
} |
1219 |
if (TRB_TYPE(*trb) == TR_EVDATA) {
|
1220 |
event.ptr = trb->parameter; |
1221 |
event.flags |= TRB_EV_ED; |
1222 |
event.length = edtla & 0xffffff;
|
1223 |
DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
|
1224 |
edtla = 0;
|
1225 |
} |
1226 |
xhci_event(xhci, &event); |
1227 |
reported = 1;
|
1228 |
} |
1229 |
} |
1230 |
return transferred;
|
1231 |
} |
1232 |
|
1233 |
static void xhci_stall_ep(XHCITransfer *xfer) |
1234 |
{ |
1235 |
XHCIState *xhci = xfer->xhci; |
1236 |
XHCISlot *slot = &xhci->slots[xfer->slotid-1];
|
1237 |
XHCIEPContext *epctx = slot->eps[xfer->epid-1];
|
1238 |
|
1239 |
epctx->ring.dequeue = xfer->trbs[0].addr;
|
1240 |
epctx->ring.ccs = xfer->trbs[0].ccs;
|
1241 |
xhci_set_ep_state(xhci, epctx, EP_HALTED); |
1242 |
DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
|
1243 |
DPRINTF("xhci: will continue at "TARGET_FMT_plx"\n", epctx->ring.dequeue); |
1244 |
} |
1245 |
|
1246 |
static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, |
1247 |
XHCIEPContext *epctx); |
1248 |
|
1249 |
static void xhci_bg_update(XHCIState *xhci, XHCIEPContext *epctx) |
1250 |
{ |
1251 |
if (epctx->bg_updating) {
|
1252 |
return;
|
1253 |
} |
1254 |
DPRINTF("xhci_bg_update(%p, %p)\n", xhci, epctx);
|
1255 |
assert(epctx->has_bg); |
1256 |
DPRINTF("xhci: fg=%d bg=%d\n", epctx->comp_xfer, epctx->next_bg);
|
1257 |
epctx->bg_updating = 1;
|
1258 |
while (epctx->transfers[epctx->comp_xfer].backgrounded &&
|
1259 |
epctx->bg_transfers[epctx->next_bg].complete) { |
1260 |
XHCITransfer *fg = &epctx->transfers[epctx->comp_xfer]; |
1261 |
XHCITransfer *bg = &epctx->bg_transfers[epctx->next_bg]; |
1262 |
#if 0
|
1263 |
DPRINTF("xhci: completing fg %d from bg %d.%d (stat: %d)\n",
|
1264 |
epctx->comp_xfer, epctx->next_bg, bg->cur_pkt,
|
1265 |
bg->usbxfer->iso_packet_desc[bg->cur_pkt].status
|
1266 |
);
|
1267 |
#endif
|
1268 |
assert(epctx->type == ET_ISO_IN); |
1269 |
assert(bg->iso_xfer); |
1270 |
assert(bg->in_xfer); |
1271 |
uint8_t *p = bg->data + bg->cur_pkt * bg->pktsize; |
1272 |
#if 0
|
1273 |
int len = bg->usbxfer->iso_packet_desc[bg->cur_pkt].actual_length;
|
1274 |
fg->status = libusb_to_ccode(bg->usbxfer->iso_packet_desc[bg->cur_pkt].status);
|
1275 |
#else
|
1276 |
int len = 0; |
1277 |
FIXME(); |
1278 |
#endif
|
1279 |
fg->complete = 1;
|
1280 |
fg->backgrounded = 0;
|
1281 |
|
1282 |
if (fg->status == CC_STALL_ERROR) {
|
1283 |
xhci_stall_ep(fg); |
1284 |
} |
1285 |
|
1286 |
xhci_xfer_data(fg, p, len, 1, 0, 1); |
1287 |
|
1288 |
epctx->comp_xfer++; |
1289 |
if (epctx->comp_xfer == TD_QUEUE) {
|
1290 |
epctx->comp_xfer = 0;
|
1291 |
} |
1292 |
DPRINTF("next fg xfer: %d\n", epctx->comp_xfer);
|
1293 |
bg->cur_pkt++; |
1294 |
if (bg->cur_pkt == bg->pkts) {
|
1295 |
bg->complete = 0;
|
1296 |
if (xhci_submit(xhci, bg, epctx) < 0) { |
1297 |
fprintf(stderr, "xhci: bg resubmit failed\n");
|
1298 |
} |
1299 |
epctx->next_bg++; |
1300 |
if (epctx->next_bg == BG_XFERS) {
|
1301 |
epctx->next_bg = 0;
|
1302 |
} |
1303 |
DPRINTF("next bg xfer: %d\n", epctx->next_bg);
|
1304 |
|
1305 |
xhci_kick_ep(xhci, fg->slotid, fg->epid); |
1306 |
} |
1307 |
} |
1308 |
epctx->bg_updating = 0;
|
1309 |
} |
1310 |
|
1311 |
#if 0
|
1312 |
static void xhci_xfer_cb(struct libusb_transfer *transfer)
|
1313 |
{
|
1314 |
XHCIState *xhci;
|
1315 |
XHCITransfer *xfer;
|
1316 |
|
1317 |
xfer = (XHCITransfer *)transfer->user_data;
|
1318 |
xhci = xfer->xhci;
|
1319 |
|
1320 |
DPRINTF("xhci_xfer_cb(slot=%d, ep=%d, status=%d)\n", xfer->slotid,
|
1321 |
xfer->epid, transfer->status);
|
1322 |
|
1323 |
assert(xfer->slotid >= 1 && xfer->slotid <= MAXSLOTS);
|
1324 |
assert(xfer->epid >= 1 && xfer->epid <= 31);
|
1325 |
|
1326 |
if (xfer->cancelled) {
|
1327 |
DPRINTF("xhci: transfer cancelled, not reporting anything\n");
|
1328 |
xfer->running = 0;
|
1329 |
return;
|
1330 |
}
|
1331 |
|
1332 |
XHCIEPContext *epctx;
|
1333 |
XHCISlot *slot;
|
1334 |
slot = &xhci->slots[xfer->slotid-1];
|
1335 |
assert(slot->eps[xfer->epid-1]);
|
1336 |
epctx = slot->eps[xfer->epid-1];
|
1337 |
|
1338 |
if (xfer->bg_xfer) {
|
1339 |
DPRINTF("xhci: background transfer, updating\n");
|
1340 |
xfer->complete = 1;
|
1341 |
xfer->running = 0;
|
1342 |
xhci_bg_update(xhci, epctx);
|
1343 |
return;
|
1344 |
}
|
1345 |
|
1346 |
if (xfer->iso_xfer) {
|
1347 |
transfer->status = transfer->iso_packet_desc[0].status;
|
1348 |
transfer->actual_length = transfer->iso_packet_desc[0].actual_length;
|
1349 |
}
|
1350 |
|
1351 |
xfer->status = libusb_to_ccode(transfer->status);
|
1352 |
|
1353 |
xfer->complete = 1;
|
1354 |
xfer->running = 0;
|
1355 |
|
1356 |
if (transfer->status == LIBUSB_TRANSFER_STALL)
|
1357 |
xhci_stall_ep(xhci, epctx, xfer);
|
1358 |
|
1359 |
DPRINTF("xhci: transfer actual length = %d\n", transfer->actual_length);
|
1360 |
|
1361 |
if (xfer->in_xfer) {
|
1362 |
if (xfer->epid == 1) {
|
1363 |
xhci_xfer_data(xhci, xfer, xfer->data + 8,
|
1364 |
transfer->actual_length, 1, 0, 1);
|
1365 |
} else {
|
1366 |
xhci_xfer_data(xhci, xfer, xfer->data,
|
1367 |
transfer->actual_length, 1, 0, 1);
|
1368 |
}
|
1369 |
} else {
|
1370 |
xhci_xfer_data(xhci, xfer, NULL, transfer->actual_length, 0, 0, 1);
|
1371 |
}
|
1372 |
|
1373 |
xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
|
1374 |
}
|
1375 |
|
1376 |
static int xhci_hle_control(XHCIState *xhci, XHCITransfer *xfer,
|
1377 |
uint8_t bmRequestType, uint8_t bRequest,
|
1378 |
uint16_t wValue, uint16_t wIndex, uint16_t wLength)
|
1379 |
{
|
1380 |
uint16_t type_req = (bmRequestType << 8) | bRequest;
|
1381 |
|
1382 |
switch (type_req) {
|
1383 |
case 0x0000 | USB_REQ_SET_CONFIGURATION:
|
1384 |
DPRINTF("xhci: HLE switch configuration\n");
|
1385 |
return xhci_switch_config(xhci, xfer->slotid, wValue) == 0;
|
1386 |
case 0x0100 | USB_REQ_SET_INTERFACE:
|
1387 |
DPRINTF("xhci: HLE set interface altsetting\n");
|
1388 |
return xhci_set_iface_alt(xhci, xfer->slotid, wIndex, wValue) == 0;
|
1389 |
case 0x0200 | USB_REQ_CLEAR_FEATURE:
|
1390 |
if (wValue == 0) { // endpoint halt
|
1391 |
DPRINTF("xhci: HLE clear halt\n");
|
1392 |
return xhci_clear_halt(xhci, xfer->slotid, wIndex);
|
1393 |
}
|
1394 |
case 0x0000 | USB_REQ_SET_ADDRESS:
|
1395 |
fprintf(stderr, "xhci: warn: illegal SET_ADDRESS request\n");
|
1396 |
return 0;
|
1397 |
default:
|
1398 |
return 0;
|
1399 |
}
|
1400 |
}
|
1401 |
#endif
|
1402 |
|
1403 |
static int xhci_setup_packet(XHCITransfer *xfer, USBDevice *dev) |
1404 |
{ |
1405 |
USBEndpoint *ep; |
1406 |
int dir;
|
1407 |
|
1408 |
dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; |
1409 |
ep = usb_ep_get(dev, dir, xfer->epid >> 1);
|
1410 |
usb_packet_setup(&xfer->packet, dir, ep); |
1411 |
usb_packet_addbuf(&xfer->packet, xfer->data, xfer->data_length); |
1412 |
DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
|
1413 |
xfer->packet.pid, dev->addr, ep->nr); |
1414 |
return 0; |
1415 |
} |
1416 |
|
1417 |
static int xhci_complete_packet(XHCITransfer *xfer, int ret) |
1418 |
{ |
1419 |
if (ret == USB_RET_ASYNC) {
|
1420 |
xfer->running_async = 1;
|
1421 |
xfer->running_retry = 0;
|
1422 |
xfer->complete = 0;
|
1423 |
xfer->cancelled = 0;
|
1424 |
return 0; |
1425 |
} else if (ret == USB_RET_NAK) { |
1426 |
xfer->running_async = 0;
|
1427 |
xfer->running_retry = 1;
|
1428 |
xfer->complete = 0;
|
1429 |
xfer->cancelled = 0;
|
1430 |
return 0; |
1431 |
} else {
|
1432 |
xfer->running_async = 0;
|
1433 |
xfer->running_retry = 0;
|
1434 |
xfer->complete = 1;
|
1435 |
} |
1436 |
|
1437 |
if (ret >= 0) { |
1438 |
xfer->status = CC_SUCCESS; |
1439 |
xhci_xfer_data(xfer, xfer->data, ret, xfer->in_xfer, 0, 1); |
1440 |
return 0; |
1441 |
} |
1442 |
|
1443 |
/* error */
|
1444 |
switch (ret) {
|
1445 |
case USB_RET_NODEV:
|
1446 |
xfer->status = CC_USB_TRANSACTION_ERROR; |
1447 |
xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1); |
1448 |
xhci_stall_ep(xfer); |
1449 |
break;
|
1450 |
case USB_RET_STALL:
|
1451 |
xfer->status = CC_STALL_ERROR; |
1452 |
xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1); |
1453 |
xhci_stall_ep(xfer); |
1454 |
break;
|
1455 |
default:
|
1456 |
fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
|
1457 |
FIXME(); |
1458 |
} |
1459 |
return 0; |
1460 |
} |
1461 |
|
1462 |
static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
|
1463 |
{ |
1464 |
if (!(port->portsc & PORTSC_PED)) {
|
1465 |
return NULL; |
1466 |
} |
1467 |
return usb_find_device(&port->port, addr);
|
1468 |
} |
1469 |
|
1470 |
static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) |
1471 |
{ |
1472 |
XHCITRB *trb_setup, *trb_status; |
1473 |
uint8_t bmRequestType; |
1474 |
uint16_t wLength; |
1475 |
XHCIPort *port; |
1476 |
USBDevice *dev; |
1477 |
int ret;
|
1478 |
|
1479 |
DPRINTF("xhci_fire_ctl_transfer(slot=%d)\n", xfer->slotid);
|
1480 |
|
1481 |
trb_setup = &xfer->trbs[0];
|
1482 |
trb_status = &xfer->trbs[xfer->trb_count-1];
|
1483 |
|
1484 |
/* at most one Event Data TRB allowed after STATUS */
|
1485 |
if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { |
1486 |
trb_status--; |
1487 |
} |
1488 |
|
1489 |
/* do some sanity checks */
|
1490 |
if (TRB_TYPE(*trb_setup) != TR_SETUP) {
|
1491 |
fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
|
1492 |
TRB_TYPE(*trb_setup)); |
1493 |
return -1; |
1494 |
} |
1495 |
if (TRB_TYPE(*trb_status) != TR_STATUS) {
|
1496 |
fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
|
1497 |
TRB_TYPE(*trb_status)); |
1498 |
return -1; |
1499 |
} |
1500 |
if (!(trb_setup->control & TRB_TR_IDT)) {
|
1501 |
fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
|
1502 |
return -1; |
1503 |
} |
1504 |
if ((trb_setup->status & 0x1ffff) != 8) { |
1505 |
fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
|
1506 |
(trb_setup->status & 0x1ffff));
|
1507 |
return -1; |
1508 |
} |
1509 |
|
1510 |
bmRequestType = trb_setup->parameter; |
1511 |
wLength = trb_setup->parameter >> 48;
|
1512 |
|
1513 |
if (xfer->data && xfer->data_alloced < wLength) {
|
1514 |
xfer->data_alloced = 0;
|
1515 |
g_free(xfer->data); |
1516 |
xfer->data = NULL;
|
1517 |
} |
1518 |
if (!xfer->data) {
|
1519 |
DPRINTF("xhci: alloc %d bytes data\n", wLength);
|
1520 |
xfer->data = g_malloc(wLength+1);
|
1521 |
xfer->data_alloced = wLength; |
1522 |
} |
1523 |
xfer->data_length = wLength; |
1524 |
|
1525 |
port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1]; |
1526 |
dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
|
1527 |
if (!dev) {
|
1528 |
fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
|
1529 |
xhci->slots[xfer->slotid-1].port);
|
1530 |
return -1; |
1531 |
} |
1532 |
|
1533 |
xfer->in_xfer = bmRequestType & USB_DIR_IN; |
1534 |
xfer->iso_xfer = false;
|
1535 |
|
1536 |
xhci_setup_packet(xfer, dev); |
1537 |
xfer->packet.parameter = trb_setup->parameter; |
1538 |
if (!xfer->in_xfer) {
|
1539 |
xhci_xfer_data(xfer, xfer->data, wLength, 0, 1, 0); |
1540 |
} |
1541 |
|
1542 |
ret = usb_handle_packet(dev, &xfer->packet); |
1543 |
|
1544 |
xhci_complete_packet(xfer, ret); |
1545 |
if (!xfer->running_async && !xfer->running_retry) {
|
1546 |
xhci_kick_ep(xhci, xfer->slotid, xfer->epid); |
1547 |
} |
1548 |
return 0; |
1549 |
} |
1550 |
|
1551 |
static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
1552 |
{ |
1553 |
XHCIPort *port; |
1554 |
USBDevice *dev; |
1555 |
int ret;
|
1556 |
|
1557 |
DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
|
1558 |
|
1559 |
xfer->in_xfer = epctx->type>>2;
|
1560 |
|
1561 |
if (xfer->data && xfer->data_alloced < xfer->data_length) {
|
1562 |
xfer->data_alloced = 0;
|
1563 |
g_free(xfer->data); |
1564 |
xfer->data = NULL;
|
1565 |
} |
1566 |
if (!xfer->data && xfer->data_length) {
|
1567 |
DPRINTF("xhci: alloc %d bytes data\n", xfer->data_length);
|
1568 |
xfer->data = g_malloc(xfer->data_length); |
1569 |
xfer->data_alloced = xfer->data_length; |
1570 |
} |
1571 |
if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
|
1572 |
if (!xfer->bg_xfer) {
|
1573 |
xfer->pkts = 1;
|
1574 |
} |
1575 |
} else {
|
1576 |
xfer->pkts = 0;
|
1577 |
} |
1578 |
|
1579 |
port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1]; |
1580 |
dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
|
1581 |
if (!dev) {
|
1582 |
fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
|
1583 |
xhci->slots[xfer->slotid-1].port);
|
1584 |
return -1; |
1585 |
} |
1586 |
|
1587 |
xhci_setup_packet(xfer, dev); |
1588 |
|
1589 |
switch(epctx->type) {
|
1590 |
case ET_INTR_OUT:
|
1591 |
case ET_INTR_IN:
|
1592 |
case ET_BULK_OUT:
|
1593 |
case ET_BULK_IN:
|
1594 |
break;
|
1595 |
case ET_ISO_OUT:
|
1596 |
case ET_ISO_IN:
|
1597 |
FIXME(); |
1598 |
break;
|
1599 |
default:
|
1600 |
fprintf(stderr, "xhci: unknown or unhandled EP "
|
1601 |
"(type %d, in %d, ep %02x)\n",
|
1602 |
epctx->type, xfer->in_xfer, xfer->epid); |
1603 |
return -1; |
1604 |
} |
1605 |
|
1606 |
if (!xfer->in_xfer) {
|
1607 |
xhci_xfer_data(xfer, xfer->data, xfer->data_length, 0, 1, 0); |
1608 |
} |
1609 |
ret = usb_handle_packet(dev, &xfer->packet); |
1610 |
|
1611 |
xhci_complete_packet(xfer, ret); |
1612 |
if (!xfer->running_async && !xfer->running_retry) {
|
1613 |
xhci_kick_ep(xhci, xfer->slotid, xfer->epid); |
1614 |
} |
1615 |
return 0; |
1616 |
} |
1617 |
|
1618 |
static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
1619 |
{ |
1620 |
int i;
|
1621 |
unsigned int length = 0; |
1622 |
XHCITRB *trb; |
1623 |
|
1624 |
DPRINTF("xhci_fire_transfer(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
|
1625 |
|
1626 |
for (i = 0; i < xfer->trb_count; i++) { |
1627 |
trb = &xfer->trbs[i]; |
1628 |
if (TRB_TYPE(*trb) == TR_NORMAL || TRB_TYPE(*trb) == TR_ISOCH) {
|
1629 |
length += trb->status & 0x1ffff;
|
1630 |
} |
1631 |
} |
1632 |
DPRINTF("xhci: total TD length=%d\n", length);
|
1633 |
|
1634 |
if (!epctx->has_bg) {
|
1635 |
xfer->data_length = length; |
1636 |
xfer->backgrounded = 0;
|
1637 |
return xhci_submit(xhci, xfer, epctx);
|
1638 |
} else {
|
1639 |
if (!epctx->bg_running) {
|
1640 |
for (i = 0; i < BG_XFERS; i++) { |
1641 |
XHCITransfer *t = &epctx->bg_transfers[i]; |
1642 |
t->xhci = xhci; |
1643 |
t->epid = xfer->epid; |
1644 |
t->slotid = xfer->slotid; |
1645 |
t->pkts = BG_PKTS; |
1646 |
t->pktsize = epctx->max_psize; |
1647 |
t->data_length = t->pkts * t->pktsize; |
1648 |
t->bg_xfer = 1;
|
1649 |
if (xhci_submit(xhci, t, epctx) < 0) { |
1650 |
fprintf(stderr, "xhci: bg submit failed\n");
|
1651 |
return -1; |
1652 |
} |
1653 |
} |
1654 |
epctx->bg_running = 1;
|
1655 |
} |
1656 |
xfer->backgrounded = 1;
|
1657 |
xhci_bg_update(xhci, epctx); |
1658 |
return 0; |
1659 |
} |
1660 |
} |
1661 |
|
1662 |
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) |
1663 |
{ |
1664 |
XHCIEPContext *epctx; |
1665 |
int length;
|
1666 |
int i;
|
1667 |
|
1668 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1669 |
assert(epid >= 1 && epid <= 31); |
1670 |
DPRINTF("xhci_kick_ep(%d, %d)\n", slotid, epid);
|
1671 |
|
1672 |
if (!xhci->slots[slotid-1].enabled) { |
1673 |
fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
|
1674 |
return;
|
1675 |
} |
1676 |
epctx = xhci->slots[slotid-1].eps[epid-1]; |
1677 |
if (!epctx) {
|
1678 |
fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
|
1679 |
epid, slotid); |
1680 |
return;
|
1681 |
} |
1682 |
|
1683 |
if (epctx->retry) {
|
1684 |
/* retry nak'ed transfer */
|
1685 |
XHCITransfer *xfer = epctx->retry; |
1686 |
int result;
|
1687 |
|
1688 |
DPRINTF("xhci: retry nack'ed transfer ...\n");
|
1689 |
assert(xfer->running_retry); |
1690 |
xhci_setup_packet(xfer, xfer->packet.ep->dev); |
1691 |
result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1692 |
if (result == USB_RET_NAK) {
|
1693 |
DPRINTF("xhci: ... xfer still nacked\n");
|
1694 |
return;
|
1695 |
} |
1696 |
DPRINTF("xhci: ... result %d\n", result);
|
1697 |
xhci_complete_packet(xfer, result); |
1698 |
assert(!xfer->running_retry); |
1699 |
epctx->retry = NULL;
|
1700 |
} |
1701 |
|
1702 |
if (epctx->state == EP_HALTED) {
|
1703 |
DPRINTF("xhci: ep halted, not running schedule\n");
|
1704 |
return;
|
1705 |
} |
1706 |
|
1707 |
xhci_set_ep_state(xhci, epctx, EP_RUNNING); |
1708 |
|
1709 |
while (1) { |
1710 |
XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; |
1711 |
if (xfer->running_async || xfer->running_retry || xfer->backgrounded) {
|
1712 |
DPRINTF("xhci: ep is busy (#%d,%d,%d,%d)\n",
|
1713 |
epctx->next_xfer, xfer->running_async, |
1714 |
xfer->running_retry, xfer->backgrounded); |
1715 |
break;
|
1716 |
} else {
|
1717 |
DPRINTF("xhci: ep: using #%d\n", epctx->next_xfer);
|
1718 |
} |
1719 |
length = xhci_ring_chain_length(xhci, &epctx->ring); |
1720 |
if (length < 0) { |
1721 |
DPRINTF("xhci: incomplete TD (%d TRBs)\n", -length);
|
1722 |
break;
|
1723 |
} else if (length == 0) { |
1724 |
break;
|
1725 |
} |
1726 |
DPRINTF("xhci: fetching %d-TRB TD\n", length);
|
1727 |
if (xfer->trbs && xfer->trb_alloced < length) {
|
1728 |
xfer->trb_count = 0;
|
1729 |
xfer->trb_alloced = 0;
|
1730 |
g_free(xfer->trbs); |
1731 |
xfer->trbs = NULL;
|
1732 |
} |
1733 |
if (!xfer->trbs) {
|
1734 |
xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
|
1735 |
xfer->trb_alloced = length; |
1736 |
} |
1737 |
xfer->trb_count = length; |
1738 |
|
1739 |
for (i = 0; i < length; i++) { |
1740 |
assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
|
1741 |
} |
1742 |
xfer->xhci = xhci; |
1743 |
xfer->epid = epid; |
1744 |
xfer->slotid = slotid; |
1745 |
|
1746 |
if (epid == 1) { |
1747 |
if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { |
1748 |
epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
|
1749 |
} else {
|
1750 |
fprintf(stderr, "xhci: error firing CTL transfer\n");
|
1751 |
} |
1752 |
} else {
|
1753 |
if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { |
1754 |
epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
|
1755 |
} else {
|
1756 |
fprintf(stderr, "xhci: error firing data transfer\n");
|
1757 |
} |
1758 |
} |
1759 |
|
1760 |
if (epctx->state == EP_HALTED) {
|
1761 |
DPRINTF("xhci: ep halted, stopping schedule\n");
|
1762 |
break;
|
1763 |
} |
1764 |
if (xfer->running_retry) {
|
1765 |
DPRINTF("xhci: xfer nacked, stopping schedule\n");
|
1766 |
epctx->retry = xfer; |
1767 |
break;
|
1768 |
} |
1769 |
} |
1770 |
} |
1771 |
|
1772 |
static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) |
1773 |
{ |
1774 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1775 |
DPRINTF("xhci_enable_slot(%d)\n", slotid);
|
1776 |
xhci->slots[slotid-1].enabled = 1; |
1777 |
xhci->slots[slotid-1].port = 0; |
1778 |
memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); |
1779 |
|
1780 |
return CC_SUCCESS;
|
1781 |
} |
1782 |
|
1783 |
static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) |
1784 |
{ |
1785 |
int i;
|
1786 |
|
1787 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1788 |
DPRINTF("xhci_disable_slot(%d)\n", slotid);
|
1789 |
|
1790 |
for (i = 1; i <= 31; i++) { |
1791 |
if (xhci->slots[slotid-1].eps[i-1]) { |
1792 |
xhci_disable_ep(xhci, slotid, i); |
1793 |
} |
1794 |
} |
1795 |
|
1796 |
xhci->slots[slotid-1].enabled = 0; |
1797 |
return CC_SUCCESS;
|
1798 |
} |
1799 |
|
1800 |
static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, |
1801 |
uint64_t pictx, bool bsr)
|
1802 |
{ |
1803 |
XHCISlot *slot; |
1804 |
USBDevice *dev; |
1805 |
target_phys_addr_t ictx, octx, dcbaap; |
1806 |
uint64_t poctx; |
1807 |
uint32_t ictl_ctx[2];
|
1808 |
uint32_t slot_ctx[4];
|
1809 |
uint32_t ep0_ctx[5];
|
1810 |
unsigned int port; |
1811 |
int i;
|
1812 |
TRBCCode res; |
1813 |
|
1814 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1815 |
DPRINTF("xhci_address_slot(%d)\n", slotid);
|
1816 |
|
1817 |
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); |
1818 |
cpu_physical_memory_read(dcbaap + 8*slotid,
|
1819 |
(uint8_t *) &poctx, sizeof(poctx));
|
1820 |
ictx = xhci_mask64(pictx); |
1821 |
octx = xhci_mask64(le64_to_cpu(poctx)); |
1822 |
|
1823 |
DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx); |
1824 |
DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx); |
1825 |
|
1826 |
cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
|
1827 |
|
1828 |
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { |
1829 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
1830 |
ictl_ctx[0], ictl_ctx[1]); |
1831 |
return CC_TRB_ERROR;
|
1832 |
} |
1833 |
|
1834 |
cpu_physical_memory_read(ictx+32, (uint8_t *) slot_ctx, sizeof(slot_ctx)); |
1835 |
cpu_physical_memory_read(ictx+64, (uint8_t *) ep0_ctx, sizeof(ep0_ctx)); |
1836 |
|
1837 |
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
|
1838 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1839 |
|
1840 |
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
|
1841 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
1842 |
|
1843 |
port = (slot_ctx[1]>>16) & 0xFF; |
1844 |
dev = xhci->ports[port-1].port.dev;
|
1845 |
|
1846 |
if (port < 1 || port > MAXPORTS) { |
1847 |
fprintf(stderr, "xhci: bad port %d\n", port);
|
1848 |
return CC_TRB_ERROR;
|
1849 |
} else if (!dev) { |
1850 |
fprintf(stderr, "xhci: port %d not connected\n", port);
|
1851 |
return CC_USB_TRANSACTION_ERROR;
|
1852 |
} |
1853 |
|
1854 |
for (i = 0; i < MAXSLOTS; i++) { |
1855 |
if (xhci->slots[i].port == port) {
|
1856 |
fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
|
1857 |
port, i+1);
|
1858 |
return CC_TRB_ERROR;
|
1859 |
} |
1860 |
} |
1861 |
|
1862 |
slot = &xhci->slots[slotid-1];
|
1863 |
slot->port = port; |
1864 |
slot->ctx = octx; |
1865 |
|
1866 |
if (bsr) {
|
1867 |
slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
|
1868 |
} else {
|
1869 |
slot->devaddr = xhci->devaddr++; |
1870 |
slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
|
1871 |
DPRINTF("xhci: device address is %d\n", slot->devaddr);
|
1872 |
usb_device_handle_control(dev, NULL,
|
1873 |
DeviceOutRequest | USB_REQ_SET_ADDRESS, |
1874 |
slot->devaddr, 0, 0, NULL); |
1875 |
} |
1876 |
|
1877 |
res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); |
1878 |
|
1879 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1880 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1881 |
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
|
1882 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
1883 |
|
1884 |
cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
1885 |
cpu_physical_memory_write(octx+32, (uint8_t *) ep0_ctx, sizeof(ep0_ctx)); |
1886 |
|
1887 |
return res;
|
1888 |
} |
1889 |
|
1890 |
|
1891 |
static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, |
1892 |
uint64_t pictx, bool dc)
|
1893 |
{ |
1894 |
target_phys_addr_t ictx, octx; |
1895 |
uint32_t ictl_ctx[2];
|
1896 |
uint32_t slot_ctx[4];
|
1897 |
uint32_t islot_ctx[4];
|
1898 |
uint32_t ep_ctx[5];
|
1899 |
int i;
|
1900 |
TRBCCode res; |
1901 |
|
1902 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1903 |
DPRINTF("xhci_configure_slot(%d)\n", slotid);
|
1904 |
|
1905 |
ictx = xhci_mask64(pictx); |
1906 |
octx = xhci->slots[slotid-1].ctx;
|
1907 |
|
1908 |
DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx); |
1909 |
DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx); |
1910 |
|
1911 |
if (dc) {
|
1912 |
for (i = 2; i <= 31; i++) { |
1913 |
if (xhci->slots[slotid-1].eps[i-1]) { |
1914 |
xhci_disable_ep(xhci, slotid, i); |
1915 |
} |
1916 |
} |
1917 |
|
1918 |
cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
1919 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
1920 |
slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
|
1921 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1922 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1923 |
cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
1924 |
|
1925 |
return CC_SUCCESS;
|
1926 |
} |
1927 |
|
1928 |
cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
|
1929 |
|
1930 |
if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { |
1931 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
1932 |
ictl_ctx[0], ictl_ctx[1]); |
1933 |
return CC_TRB_ERROR;
|
1934 |
} |
1935 |
|
1936 |
cpu_physical_memory_read(ictx+32, (uint8_t *) islot_ctx, sizeof(islot_ctx)); |
1937 |
cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
1938 |
|
1939 |
if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { |
1940 |
fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); |
1941 |
return CC_CONTEXT_STATE_ERROR;
|
1942 |
} |
1943 |
|
1944 |
for (i = 2; i <= 31; i++) { |
1945 |
if (ictl_ctx[0] & (1<<i)) { |
1946 |
xhci_disable_ep(xhci, slotid, i); |
1947 |
} |
1948 |
if (ictl_ctx[1] & (1<<i)) { |
1949 |
cpu_physical_memory_read(ictx+32+(32*i), |
1950 |
(uint8_t *) ep_ctx, sizeof(ep_ctx));
|
1951 |
DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
|
1952 |
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], |
1953 |
ep_ctx[3], ep_ctx[4]); |
1954 |
xhci_disable_ep(xhci, slotid, i); |
1955 |
res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
|
1956 |
if (res != CC_SUCCESS) {
|
1957 |
return res;
|
1958 |
} |
1959 |
DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
|
1960 |
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], |
1961 |
ep_ctx[3], ep_ctx[4]); |
1962 |
cpu_physical_memory_write(octx+(32*i),
|
1963 |
(uint8_t *) ep_ctx, sizeof(ep_ctx));
|
1964 |
} |
1965 |
} |
1966 |
|
1967 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
1968 |
slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
|
1969 |
slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
|
1970 |
slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << |
1971 |
SLOT_CONTEXT_ENTRIES_SHIFT); |
1972 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
1973 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
1974 |
|
1975 |
cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
1976 |
|
1977 |
return CC_SUCCESS;
|
1978 |
} |
1979 |
|
1980 |
|
1981 |
static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, |
1982 |
uint64_t pictx) |
1983 |
{ |
1984 |
target_phys_addr_t ictx, octx; |
1985 |
uint32_t ictl_ctx[2];
|
1986 |
uint32_t iep0_ctx[5];
|
1987 |
uint32_t ep0_ctx[5];
|
1988 |
uint32_t islot_ctx[4];
|
1989 |
uint32_t slot_ctx[4];
|
1990 |
|
1991 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
1992 |
DPRINTF("xhci_evaluate_slot(%d)\n", slotid);
|
1993 |
|
1994 |
ictx = xhci_mask64(pictx); |
1995 |
octx = xhci->slots[slotid-1].ctx;
|
1996 |
|
1997 |
DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx); |
1998 |
DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx); |
1999 |
|
2000 |
cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
|
2001 |
|
2002 |
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { |
2003 |
fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
|
2004 |
ictl_ctx[0], ictl_ctx[1]); |
2005 |
return CC_TRB_ERROR;
|
2006 |
} |
2007 |
|
2008 |
if (ictl_ctx[1] & 0x1) { |
2009 |
cpu_physical_memory_read(ictx+32,
|
2010 |
(uint8_t *) islot_ctx, sizeof(islot_ctx));
|
2011 |
|
2012 |
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
|
2013 |
islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); |
2014 |
|
2015 |
cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
2016 |
|
2017 |
slot_ctx[1] &= ~0xFFFF; /* max exit latency */ |
2018 |
slot_ctx[1] |= islot_ctx[1] & 0xFFFF; |
2019 |
slot_ctx[2] &= ~0xFF00000; /* interrupter target */ |
2020 |
slot_ctx[2] |= islot_ctx[2] & 0xFF000000; |
2021 |
|
2022 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
2023 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
2024 |
|
2025 |
cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
2026 |
} |
2027 |
|
2028 |
if (ictl_ctx[1] & 0x2) { |
2029 |
cpu_physical_memory_read(ictx+64,
|
2030 |
(uint8_t *) iep0_ctx, sizeof(iep0_ctx));
|
2031 |
|
2032 |
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
|
2033 |
iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], |
2034 |
iep0_ctx[3], iep0_ctx[4]); |
2035 |
|
2036 |
cpu_physical_memory_read(octx+32, (uint8_t *) ep0_ctx, sizeof(ep0_ctx)); |
2037 |
|
2038 |
ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ |
2039 |
ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; |
2040 |
|
2041 |
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
|
2042 |
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); |
2043 |
|
2044 |
cpu_physical_memory_write(octx+32,
|
2045 |
(uint8_t *) ep0_ctx, sizeof(ep0_ctx));
|
2046 |
} |
2047 |
|
2048 |
return CC_SUCCESS;
|
2049 |
} |
2050 |
|
2051 |
static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) |
2052 |
{ |
2053 |
uint32_t slot_ctx[4];
|
2054 |
target_phys_addr_t octx; |
2055 |
int i;
|
2056 |
|
2057 |
assert(slotid >= 1 && slotid <= MAXSLOTS);
|
2058 |
DPRINTF("xhci_reset_slot(%d)\n", slotid);
|
2059 |
|
2060 |
octx = xhci->slots[slotid-1].ctx;
|
2061 |
|
2062 |
DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx); |
2063 |
|
2064 |
for (i = 2; i <= 31; i++) { |
2065 |
if (xhci->slots[slotid-1].eps[i-1]) { |
2066 |
xhci_disable_ep(xhci, slotid, i); |
2067 |
} |
2068 |
} |
2069 |
|
2070 |
cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
2071 |
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
|
2072 |
slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
|
2073 |
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
|
2074 |
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); |
2075 |
cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
|
2076 |
|
2077 |
return CC_SUCCESS;
|
2078 |
} |
2079 |
|
2080 |
static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) |
2081 |
{ |
2082 |
unsigned int slotid; |
2083 |
slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; |
2084 |
if (slotid < 1 || slotid > MAXSLOTS) { |
2085 |
fprintf(stderr, "xhci: bad slot id %d\n", slotid);
|
2086 |
event->ccode = CC_TRB_ERROR; |
2087 |
return 0; |
2088 |
} else if (!xhci->slots[slotid-1].enabled) { |
2089 |
fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
|
2090 |
event->ccode = CC_SLOT_NOT_ENABLED_ERROR; |
2091 |
return 0; |
2092 |
} |
2093 |
return slotid;
|
2094 |
} |
2095 |
|
2096 |
static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
|
2097 |
{ |
2098 |
target_phys_addr_t ctx; |
2099 |
uint8_t bw_ctx[MAXPORTS+1];
|
2100 |
|
2101 |
DPRINTF("xhci_get_port_bandwidth()\n");
|
2102 |
|
2103 |
ctx = xhci_mask64(pctx); |
2104 |
|
2105 |
DPRINTF("xhci: bandwidth context at "TARGET_FMT_plx"\n", ctx); |
2106 |
|
2107 |
/* TODO: actually implement real values here */
|
2108 |
bw_ctx[0] = 0; |
2109 |
memset(&bw_ctx[1], 80, MAXPORTS); /* 80% */ |
2110 |
cpu_physical_memory_write(ctx, bw_ctx, sizeof(bw_ctx));
|
2111 |
|
2112 |
return CC_SUCCESS;
|
2113 |
} |
2114 |
|
2115 |
static uint32_t rotl(uint32_t v, unsigned count) |
2116 |
{ |
2117 |
count &= 31;
|
2118 |
return (v << count) | (v >> (32 - count)); |
2119 |
} |
2120 |
|
2121 |
|
2122 |
static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
|
2123 |
{ |
2124 |
uint32_t val; |
2125 |
val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); |
2126 |
val += rotl(lo + 0x49434878, hi & 0x1F); |
2127 |
val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); |
2128 |
return ~val;
|
2129 |
} |
2130 |
|
2131 |
static void xhci_via_challenge(uint64_t addr) |
2132 |
{ |
2133 |
uint32_t buf[8];
|
2134 |
uint32_t obuf[8];
|
2135 |
target_phys_addr_t paddr = xhci_mask64(addr); |
2136 |
|
2137 |
cpu_physical_memory_read(paddr, (uint8_t *) &buf, 32);
|
2138 |
|
2139 |
memcpy(obuf, buf, sizeof(obuf));
|
2140 |
|
2141 |
if ((buf[0] & 0xff) == 2) { |
2142 |
obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; |
2143 |
obuf[0] |= (buf[2] * buf[3]) & 0xff; |
2144 |
obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; |
2145 |
obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; |
2146 |
obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; |
2147 |
obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; |
2148 |
obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; |
2149 |
obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; |
2150 |
obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; |
2151 |
} |
2152 |
|
2153 |
cpu_physical_memory_write(paddr, (uint8_t *) &obuf, 32);
|
2154 |
} |
2155 |
|
2156 |
static void xhci_process_commands(XHCIState *xhci) |
2157 |
{ |
2158 |
XHCITRB trb; |
2159 |
TRBType type; |
2160 |
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; |
2161 |
target_phys_addr_t addr; |
2162 |
unsigned int i, slotid = 0; |
2163 |
|
2164 |
DPRINTF("xhci_process_commands()\n");
|
2165 |
if (!xhci_running(xhci)) {
|
2166 |
DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
|
2167 |
return;
|
2168 |
} |
2169 |
|
2170 |
xhci->crcr_low |= CRCR_CRR; |
2171 |
|
2172 |
while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
|
2173 |
event.ptr = addr; |
2174 |
switch (type) {
|
2175 |
case CR_ENABLE_SLOT:
|
2176 |
for (i = 0; i < MAXSLOTS; i++) { |
2177 |
if (!xhci->slots[i].enabled) {
|
2178 |
break;
|
2179 |
} |
2180 |
} |
2181 |
if (i >= MAXSLOTS) {
|
2182 |
fprintf(stderr, "xhci: no device slots available\n");
|
2183 |
event.ccode = CC_NO_SLOTS_ERROR; |
2184 |
} else {
|
2185 |
slotid = i+1;
|
2186 |
event.ccode = xhci_enable_slot(xhci, slotid); |
2187 |
} |
2188 |
break;
|
2189 |
case CR_DISABLE_SLOT:
|
2190 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2191 |
if (slotid) {
|
2192 |
event.ccode = xhci_disable_slot(xhci, slotid); |
2193 |
} |
2194 |
break;
|
2195 |
case CR_ADDRESS_DEVICE:
|
2196 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2197 |
if (slotid) {
|
2198 |
event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, |
2199 |
trb.control & TRB_CR_BSR); |
2200 |
} |
2201 |
break;
|
2202 |
case CR_CONFIGURE_ENDPOINT:
|
2203 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2204 |
if (slotid) {
|
2205 |
event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, |
2206 |
trb.control & TRB_CR_DC); |
2207 |
} |
2208 |
break;
|
2209 |
case CR_EVALUATE_CONTEXT:
|
2210 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2211 |
if (slotid) {
|
2212 |
event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); |
2213 |
} |
2214 |
break;
|
2215 |
case CR_STOP_ENDPOINT:
|
2216 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2217 |
if (slotid) {
|
2218 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
2219 |
& TRB_CR_EPID_MASK; |
2220 |
event.ccode = xhci_stop_ep(xhci, slotid, epid); |
2221 |
} |
2222 |
break;
|
2223 |
case CR_RESET_ENDPOINT:
|
2224 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2225 |
if (slotid) {
|
2226 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
2227 |
& TRB_CR_EPID_MASK; |
2228 |
event.ccode = xhci_reset_ep(xhci, slotid, epid); |
2229 |
} |
2230 |
break;
|
2231 |
case CR_SET_TR_DEQUEUE:
|
2232 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2233 |
if (slotid) {
|
2234 |
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) |
2235 |
& TRB_CR_EPID_MASK; |
2236 |
event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, |
2237 |
trb.parameter); |
2238 |
} |
2239 |
break;
|
2240 |
case CR_RESET_DEVICE:
|
2241 |
slotid = xhci_get_slot(xhci, &event, &trb); |
2242 |
if (slotid) {
|
2243 |
event.ccode = xhci_reset_slot(xhci, slotid); |
2244 |
} |
2245 |
break;
|
2246 |
case CR_GET_PORT_BANDWIDTH:
|
2247 |
event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); |
2248 |
break;
|
2249 |
case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
|
2250 |
xhci_via_challenge(trb.parameter); |
2251 |
break;
|
2252 |
case CR_VENDOR_NEC_FIRMWARE_REVISION:
|
2253 |
event.type = 48; /* NEC reply */ |
2254 |
event.length = 0x3025;
|
2255 |
break;
|
2256 |
case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
|
2257 |
{ |
2258 |
uint32_t chi = trb.parameter >> 32;
|
2259 |
uint32_t clo = trb.parameter; |
2260 |
uint32_t val = xhci_nec_challenge(chi, clo); |
2261 |
event.length = val & 0xFFFF;
|
2262 |
event.epid = val >> 16;
|
2263 |
slotid = val >> 24;
|
2264 |
event.type = 48; /* NEC reply */ |
2265 |
} |
2266 |
break;
|
2267 |
default:
|
2268 |
fprintf(stderr, "xhci: unimplemented command %d\n", type);
|
2269 |
event.ccode = CC_TRB_ERROR; |
2270 |
break;
|
2271 |
} |
2272 |
event.slotid = slotid; |
2273 |
xhci_event(xhci, &event); |
2274 |
} |
2275 |
} |
2276 |
|
2277 |
static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) |
2278 |
{ |
2279 |
int nr = port->port.index + 1; |
2280 |
|
2281 |
port->portsc = PORTSC_PP; |
2282 |
if (port->port.dev && !is_detach) {
|
2283 |
port->portsc |= PORTSC_CCS; |
2284 |
switch (port->port.dev->speed) {
|
2285 |
case USB_SPEED_LOW:
|
2286 |
port->portsc |= PORTSC_SPEED_LOW; |
2287 |
break;
|
2288 |
case USB_SPEED_FULL:
|
2289 |
port->portsc |= PORTSC_SPEED_FULL; |
2290 |
break;
|
2291 |
case USB_SPEED_HIGH:
|
2292 |
port->portsc |= PORTSC_SPEED_HIGH; |
2293 |
break;
|
2294 |
} |
2295 |
} |
2296 |
|
2297 |
if (xhci_running(xhci)) {
|
2298 |
port->portsc |= PORTSC_CSC; |
2299 |
XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
|
2300 |
xhci_event(xhci, &ev); |
2301 |
DPRINTF("xhci: port change event for port %d\n", nr);
|
2302 |
} |
2303 |
} |
2304 |
|
2305 |
static void xhci_reset(void *opaque) |
2306 |
{ |
2307 |
XHCIState *xhci = opaque; |
2308 |
int i;
|
2309 |
|
2310 |
DPRINTF("xhci: full reset\n");
|
2311 |
if (!(xhci->usbsts & USBSTS_HCH)) {
|
2312 |
fprintf(stderr, "xhci: reset while running!\n");
|
2313 |
} |
2314 |
|
2315 |
xhci->usbcmd = 0;
|
2316 |
xhci->usbsts = USBSTS_HCH; |
2317 |
xhci->dnctrl = 0;
|
2318 |
xhci->crcr_low = 0;
|
2319 |
xhci->crcr_high = 0;
|
2320 |
xhci->dcbaap_low = 0;
|
2321 |
xhci->dcbaap_high = 0;
|
2322 |
xhci->config = 0;
|
2323 |
xhci->devaddr = 2;
|
2324 |
|
2325 |
for (i = 0; i < MAXSLOTS; i++) { |
2326 |
xhci_disable_slot(xhci, i+1);
|
2327 |
} |
2328 |
|
2329 |
for (i = 0; i < MAXPORTS; i++) { |
2330 |
xhci_update_port(xhci, xhci->ports + i, 0);
|
2331 |
} |
2332 |
|
2333 |
xhci->mfindex = 0;
|
2334 |
xhci->iman = 0;
|
2335 |
xhci->imod = 0;
|
2336 |
xhci->erstsz = 0;
|
2337 |
xhci->erstba_low = 0;
|
2338 |
xhci->erstba_high = 0;
|
2339 |
xhci->erdp_low = 0;
|
2340 |
xhci->erdp_high = 0;
|
2341 |
|
2342 |
xhci->er_ep_idx = 0;
|
2343 |
xhci->er_pcs = 1;
|
2344 |
xhci->er_full = 0;
|
2345 |
xhci->ev_buffer_put = 0;
|
2346 |
xhci->ev_buffer_get = 0;
|
2347 |
} |
2348 |
|
2349 |
static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
|
2350 |
{ |
2351 |
DPRINTF("xhci_cap_read(0x%x)\n", reg);
|
2352 |
|
2353 |
switch (reg) {
|
2354 |
case 0x00: /* HCIVERSION, CAPLENGTH */ |
2355 |
return 0x01000000 | LEN_CAP; |
2356 |
case 0x04: /* HCSPARAMS 1 */ |
2357 |
return (MAXPORTS<<24) | (MAXINTRS<<8) | MAXSLOTS; |
2358 |
case 0x08: /* HCSPARAMS 2 */ |
2359 |
return 0x0000000f; |
2360 |
case 0x0c: /* HCSPARAMS 3 */ |
2361 |
return 0x00000000; |
2362 |
case 0x10: /* HCCPARAMS */ |
2363 |
#if TARGET_PHYS_ADDR_BITS > 32 |
2364 |
return 0x00081001; |
2365 |
#else
|
2366 |
return 0x00081000; |
2367 |
#endif
|
2368 |
case 0x14: /* DBOFF */ |
2369 |
return OFF_DOORBELL;
|
2370 |
case 0x18: /* RTSOFF */ |
2371 |
return OFF_RUNTIME;
|
2372 |
|
2373 |
/* extended capabilities */
|
2374 |
case 0x20: /* Supported Protocol:00 */ |
2375 |
#if USB3_PORTS > 0 |
2376 |
return 0x02000402; /* USB 2.0 */ |
2377 |
#else
|
2378 |
return 0x02000002; /* USB 2.0 */ |
2379 |
#endif
|
2380 |
case 0x24: /* Supported Protocol:04 */ |
2381 |
return 0x20425455; /* "USB " */ |
2382 |
case 0x28: /* Supported Protocol:08 */ |
2383 |
return 0x00000001 | (USB2_PORTS<<8); |
2384 |
case 0x2c: /* Supported Protocol:0c */ |
2385 |
return 0x00000000; /* reserved */ |
2386 |
#if USB3_PORTS > 0 |
2387 |
case 0x30: /* Supported Protocol:00 */ |
2388 |
return 0x03000002; /* USB 3.0 */ |
2389 |
case 0x34: /* Supported Protocol:04 */ |
2390 |
return 0x20425455; /* "USB " */ |
2391 |
case 0x38: /* Supported Protocol:08 */ |
2392 |
return 0x00000000 | (USB2_PORTS+1) | (USB3_PORTS<<8); |
2393 |
case 0x3c: /* Supported Protocol:0c */ |
2394 |
return 0x00000000; /* reserved */ |
2395 |
#endif
|
2396 |
default:
|
2397 |
fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
|
2398 |
} |
2399 |
return 0; |
2400 |
} |
2401 |
|
2402 |
static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
|
2403 |
{ |
2404 |
uint32_t port = reg >> 4;
|
2405 |
if (port >= MAXPORTS) {
|
2406 |
fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
|
2407 |
return 0; |
2408 |
} |
2409 |
|
2410 |
switch (reg & 0xf) { |
2411 |
case 0x00: /* PORTSC */ |
2412 |
return xhci->ports[port].portsc;
|
2413 |
case 0x04: /* PORTPMSC */ |
2414 |
case 0x08: /* PORTLI */ |
2415 |
return 0; |
2416 |
case 0x0c: /* reserved */ |
2417 |
default:
|
2418 |
fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
|
2419 |
port, reg); |
2420 |
return 0; |
2421 |
} |
2422 |
} |
2423 |
|
2424 |
static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2425 |
{ |
2426 |
uint32_t port = reg >> 4;
|
2427 |
uint32_t portsc; |
2428 |
|
2429 |
if (port >= MAXPORTS) {
|
2430 |
fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
|
2431 |
return;
|
2432 |
} |
2433 |
|
2434 |
switch (reg & 0xf) { |
2435 |
case 0x00: /* PORTSC */ |
2436 |
portsc = xhci->ports[port].portsc; |
2437 |
/* write-1-to-clear bits*/
|
2438 |
portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| |
2439 |
PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); |
2440 |
if (val & PORTSC_LWS) {
|
2441 |
/* overwrite PLS only when LWS=1 */
|
2442 |
portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); |
2443 |
portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); |
2444 |
} |
2445 |
/* read/write bits */
|
2446 |
portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); |
2447 |
portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); |
2448 |
/* write-1-to-start bits */
|
2449 |
if (val & PORTSC_PR) {
|
2450 |
DPRINTF("xhci: port %d reset\n", port);
|
2451 |
usb_device_reset(xhci->ports[port].port.dev); |
2452 |
portsc |= PORTSC_PRC | PORTSC_PED; |
2453 |
} |
2454 |
xhci->ports[port].portsc = portsc; |
2455 |
break;
|
2456 |
case 0x04: /* PORTPMSC */ |
2457 |
case 0x08: /* PORTLI */ |
2458 |
default:
|
2459 |
fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
|
2460 |
port, reg); |
2461 |
} |
2462 |
} |
2463 |
|
2464 |
static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
|
2465 |
{ |
2466 |
DPRINTF("xhci_oper_read(0x%x)\n", reg);
|
2467 |
|
2468 |
if (reg >= 0x400) { |
2469 |
return xhci_port_read(xhci, reg - 0x400); |
2470 |
} |
2471 |
|
2472 |
switch (reg) {
|
2473 |
case 0x00: /* USBCMD */ |
2474 |
return xhci->usbcmd;
|
2475 |
case 0x04: /* USBSTS */ |
2476 |
return xhci->usbsts;
|
2477 |
case 0x08: /* PAGESIZE */ |
2478 |
return 1; /* 4KiB */ |
2479 |
case 0x14: /* DNCTRL */ |
2480 |
return xhci->dnctrl;
|
2481 |
case 0x18: /* CRCR low */ |
2482 |
return xhci->crcr_low & ~0xe; |
2483 |
case 0x1c: /* CRCR high */ |
2484 |
return xhci->crcr_high;
|
2485 |
case 0x30: /* DCBAAP low */ |
2486 |
return xhci->dcbaap_low;
|
2487 |
case 0x34: /* DCBAAP high */ |
2488 |
return xhci->dcbaap_high;
|
2489 |
case 0x38: /* CONFIG */ |
2490 |
return xhci->config;
|
2491 |
default:
|
2492 |
fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
|
2493 |
} |
2494 |
return 0; |
2495 |
} |
2496 |
|
2497 |
static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2498 |
{ |
2499 |
DPRINTF("xhci_oper_write(0x%x, 0x%08x)\n", reg, val);
|
2500 |
|
2501 |
if (reg >= 0x400) { |
2502 |
xhci_port_write(xhci, reg - 0x400, val);
|
2503 |
return;
|
2504 |
} |
2505 |
|
2506 |
switch (reg) {
|
2507 |
case 0x00: /* USBCMD */ |
2508 |
if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
|
2509 |
xhci_run(xhci); |
2510 |
} else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { |
2511 |
xhci_stop(xhci); |
2512 |
} |
2513 |
xhci->usbcmd = val & 0xc0f;
|
2514 |
if (val & USBCMD_HCRST) {
|
2515 |
xhci_reset(xhci); |
2516 |
} |
2517 |
xhci_irq_update(xhci); |
2518 |
break;
|
2519 |
|
2520 |
case 0x04: /* USBSTS */ |
2521 |
/* these bits are write-1-to-clear */
|
2522 |
xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); |
2523 |
xhci_irq_update(xhci); |
2524 |
break;
|
2525 |
|
2526 |
case 0x14: /* DNCTRL */ |
2527 |
xhci->dnctrl = val & 0xffff;
|
2528 |
break;
|
2529 |
case 0x18: /* CRCR low */ |
2530 |
xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
|
2531 |
break;
|
2532 |
case 0x1c: /* CRCR high */ |
2533 |
xhci->crcr_high = val; |
2534 |
if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
|
2535 |
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; |
2536 |
xhci->crcr_low &= ~CRCR_CRR; |
2537 |
xhci_event(xhci, &event); |
2538 |
DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
|
2539 |
} else {
|
2540 |
target_phys_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
|
2541 |
xhci_ring_init(xhci, &xhci->cmd_ring, base); |
2542 |
} |
2543 |
xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); |
2544 |
break;
|
2545 |
case 0x30: /* DCBAAP low */ |
2546 |
xhci->dcbaap_low = val & 0xffffffc0;
|
2547 |
break;
|
2548 |
case 0x34: /* DCBAAP high */ |
2549 |
xhci->dcbaap_high = val; |
2550 |
break;
|
2551 |
case 0x38: /* CONFIG */ |
2552 |
xhci->config = val & 0xff;
|
2553 |
break;
|
2554 |
default:
|
2555 |
fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
|
2556 |
} |
2557 |
} |
2558 |
|
2559 |
static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
|
2560 |
{ |
2561 |
DPRINTF("xhci_runtime_read(0x%x)\n", reg);
|
2562 |
|
2563 |
switch (reg) {
|
2564 |
case 0x00: /* MFINDEX */ |
2565 |
fprintf(stderr, "xhci_runtime_read: MFINDEX not yet implemented\n");
|
2566 |
return xhci->mfindex;
|
2567 |
case 0x20: /* IMAN */ |
2568 |
return xhci->iman;
|
2569 |
case 0x24: /* IMOD */ |
2570 |
return xhci->imod;
|
2571 |
case 0x28: /* ERSTSZ */ |
2572 |
return xhci->erstsz;
|
2573 |
case 0x30: /* ERSTBA low */ |
2574 |
return xhci->erstba_low;
|
2575 |
case 0x34: /* ERSTBA high */ |
2576 |
return xhci->erstba_high;
|
2577 |
case 0x38: /* ERDP low */ |
2578 |
return xhci->erdp_low;
|
2579 |
case 0x3c: /* ERDP high */ |
2580 |
return xhci->erdp_high;
|
2581 |
default:
|
2582 |
fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
|
2583 |
} |
2584 |
return 0; |
2585 |
} |
2586 |
|
2587 |
static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2588 |
{ |
2589 |
DPRINTF("xhci_runtime_write(0x%x, 0x%08x)\n", reg, val);
|
2590 |
|
2591 |
switch (reg) {
|
2592 |
case 0x20: /* IMAN */ |
2593 |
if (val & IMAN_IP) {
|
2594 |
xhci->iman &= ~IMAN_IP; |
2595 |
} |
2596 |
xhci->iman &= ~IMAN_IE; |
2597 |
xhci->iman |= val & IMAN_IE; |
2598 |
xhci_irq_update(xhci); |
2599 |
break;
|
2600 |
case 0x24: /* IMOD */ |
2601 |
xhci->imod = val; |
2602 |
break;
|
2603 |
case 0x28: /* ERSTSZ */ |
2604 |
xhci->erstsz = val & 0xffff;
|
2605 |
break;
|
2606 |
case 0x30: /* ERSTBA low */ |
2607 |
/* XXX NEC driver bug: it doesn't align this to 64 bytes
|
2608 |
xhci->erstba_low = val & 0xffffffc0; */
|
2609 |
xhci->erstba_low = val & 0xfffffff0;
|
2610 |
break;
|
2611 |
case 0x34: /* ERSTBA high */ |
2612 |
xhci->erstba_high = val; |
2613 |
xhci_er_reset(xhci); |
2614 |
break;
|
2615 |
case 0x38: /* ERDP low */ |
2616 |
if (val & ERDP_EHB) {
|
2617 |
xhci->erdp_low &= ~ERDP_EHB; |
2618 |
} |
2619 |
xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB); |
2620 |
break;
|
2621 |
case 0x3c: /* ERDP high */ |
2622 |
xhci->erdp_high = val; |
2623 |
xhci_events_update(xhci); |
2624 |
break;
|
2625 |
default:
|
2626 |
fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
|
2627 |
} |
2628 |
} |
2629 |
|
2630 |
static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
|
2631 |
{ |
2632 |
DPRINTF("xhci_doorbell_read(0x%x)\n", reg);
|
2633 |
/* doorbells always read as 0 */
|
2634 |
return 0; |
2635 |
} |
2636 |
|
2637 |
static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val) |
2638 |
{ |
2639 |
DPRINTF("xhci_doorbell_write(0x%x, 0x%08x)\n", reg, val);
|
2640 |
|
2641 |
if (!xhci_running(xhci)) {
|
2642 |
fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
|
2643 |
return;
|
2644 |
} |
2645 |
|
2646 |
reg >>= 2;
|
2647 |
|
2648 |
if (reg == 0) { |
2649 |
if (val == 0) { |
2650 |
xhci_process_commands(xhci); |
2651 |
} else {
|
2652 |
fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
|
2653 |
} |
2654 |
} else {
|
2655 |
if (reg > MAXSLOTS) {
|
2656 |
fprintf(stderr, "xhci: bad doorbell %d\n", reg);
|
2657 |
} else if (val > 31) { |
2658 |
fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
|
2659 |
} else {
|
2660 |
xhci_kick_ep(xhci, reg, val); |
2661 |
} |
2662 |
} |
2663 |
} |
2664 |
|
2665 |
static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr, |
2666 |
unsigned size)
|
2667 |
{ |
2668 |
XHCIState *xhci = ptr; |
2669 |
|
2670 |
/* Only aligned reads are allowed on xHCI */
|
2671 |
if (addr & 3) { |
2672 |
fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
|
2673 |
return 0; |
2674 |
} |
2675 |
|
2676 |
if (addr < LEN_CAP) {
|
2677 |
return xhci_cap_read(xhci, addr);
|
2678 |
} else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) { |
2679 |
return xhci_oper_read(xhci, addr - OFF_OPER);
|
2680 |
} else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { |
2681 |
return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
|
2682 |
} else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { |
2683 |
return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
|
2684 |
} else {
|
2685 |
fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr); |
2686 |
return 0; |
2687 |
} |
2688 |
} |
2689 |
|
2690 |
static void xhci_mem_write(void *ptr, target_phys_addr_t addr, |
2691 |
uint64_t val, unsigned size)
|
2692 |
{ |
2693 |
XHCIState *xhci = ptr; |
2694 |
|
2695 |
/* Only aligned writes are allowed on xHCI */
|
2696 |
if (addr & 3) { |
2697 |
fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
|
2698 |
return;
|
2699 |
} |
2700 |
|
2701 |
if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
|
2702 |
xhci_oper_write(xhci, addr - OFF_OPER, val); |
2703 |
} else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { |
2704 |
xhci_runtime_write(xhci, addr - OFF_RUNTIME, val); |
2705 |
} else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { |
2706 |
xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val); |
2707 |
} else {
|
2708 |
fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr); |
2709 |
} |
2710 |
} |
2711 |
|
2712 |
static const MemoryRegionOps xhci_mem_ops = { |
2713 |
.read = xhci_mem_read, |
2714 |
.write = xhci_mem_write, |
2715 |
.valid.min_access_size = 4,
|
2716 |
.valid.max_access_size = 4,
|
2717 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2718 |
}; |
2719 |
|
2720 |
static void xhci_attach(USBPort *usbport) |
2721 |
{ |
2722 |
XHCIState *xhci = usbport->opaque; |
2723 |
XHCIPort *port = &xhci->ports[usbport->index]; |
2724 |
|
2725 |
xhci_update_port(xhci, port, 0);
|
2726 |
} |
2727 |
|
2728 |
static void xhci_detach(USBPort *usbport) |
2729 |
{ |
2730 |
XHCIState *xhci = usbport->opaque; |
2731 |
XHCIPort *port = &xhci->ports[usbport->index]; |
2732 |
|
2733 |
xhci_update_port(xhci, port, 1);
|
2734 |
} |
2735 |
|
2736 |
static void xhci_wakeup(USBPort *usbport) |
2737 |
{ |
2738 |
XHCIState *xhci = usbport->opaque; |
2739 |
XHCIPort *port = &xhci->ports[usbport->index]; |
2740 |
int nr = port->port.index + 1; |
2741 |
XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
|
2742 |
uint32_t pls; |
2743 |
|
2744 |
pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; |
2745 |
if (pls != 3) { |
2746 |
return;
|
2747 |
} |
2748 |
port->portsc |= 0xf << PORTSC_PLS_SHIFT;
|
2749 |
if (port->portsc & PORTSC_PLC) {
|
2750 |
return;
|
2751 |
} |
2752 |
port->portsc |= PORTSC_PLC; |
2753 |
xhci_event(xhci, &ev); |
2754 |
} |
2755 |
|
2756 |
static void xhci_complete(USBPort *port, USBPacket *packet) |
2757 |
{ |
2758 |
XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); |
2759 |
|
2760 |
xhci_complete_packet(xfer, packet->result); |
2761 |
xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); |
2762 |
} |
2763 |
|
2764 |
static void xhci_child_detach(USBPort *port, USBDevice *child) |
2765 |
{ |
2766 |
FIXME(); |
2767 |
} |
2768 |
|
2769 |
static USBPortOps xhci_port_ops = {
|
2770 |
.attach = xhci_attach, |
2771 |
.detach = xhci_detach, |
2772 |
.wakeup = xhci_wakeup, |
2773 |
.complete = xhci_complete, |
2774 |
.child_detach = xhci_child_detach, |
2775 |
}; |
2776 |
|
2777 |
static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) |
2778 |
{ |
2779 |
XHCISlot *slot; |
2780 |
int slotid;
|
2781 |
|
2782 |
for (slotid = 1; slotid <= MAXSLOTS; slotid++) { |
2783 |
slot = &xhci->slots[slotid-1];
|
2784 |
if (slot->devaddr == dev->addr) {
|
2785 |
return slotid;
|
2786 |
} |
2787 |
} |
2788 |
return 0; |
2789 |
} |
2790 |
|
2791 |
static int xhci_find_epid(USBEndpoint *ep) |
2792 |
{ |
2793 |
if (ep->nr == 0) { |
2794 |
return 1; |
2795 |
} |
2796 |
if (ep->pid == USB_TOKEN_IN) {
|
2797 |
return ep->nr * 2 + 1; |
2798 |
} else {
|
2799 |
return ep->nr * 2; |
2800 |
} |
2801 |
} |
2802 |
|
2803 |
static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) |
2804 |
{ |
2805 |
XHCIState *xhci = container_of(bus, XHCIState, bus); |
2806 |
int slotid;
|
2807 |
|
2808 |
DPRINTF("%s\n", __func__);
|
2809 |
slotid = xhci_find_slotid(xhci, ep->dev); |
2810 |
if (slotid == 0 || !xhci->slots[slotid-1].enabled) { |
2811 |
DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
|
2812 |
return;
|
2813 |
} |
2814 |
xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); |
2815 |
} |
2816 |
|
2817 |
static USBBusOps xhci_bus_ops = {
|
2818 |
.wakeup_endpoint = xhci_wakeup_endpoint, |
2819 |
}; |
2820 |
|
2821 |
static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) |
2822 |
{ |
2823 |
int i;
|
2824 |
|
2825 |
xhci->usbsts = USBSTS_HCH; |
2826 |
|
2827 |
usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); |
2828 |
|
2829 |
for (i = 0; i < MAXPORTS; i++) { |
2830 |
memset(&xhci->ports[i], 0, sizeof(xhci->ports[i])); |
2831 |
usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i, |
2832 |
&xhci_port_ops, |
2833 |
USB_SPEED_MASK_LOW | |
2834 |
USB_SPEED_MASK_FULL | |
2835 |
USB_SPEED_MASK_HIGH); |
2836 |
} |
2837 |
for (i = 0; i < MAXSLOTS; i++) { |
2838 |
xhci->slots[i].enabled = 0;
|
2839 |
} |
2840 |
|
2841 |
qemu_register_reset(xhci_reset, xhci); |
2842 |
} |
2843 |
|
2844 |
static int usb_xhci_initfn(struct PCIDevice *dev) |
2845 |
{ |
2846 |
int ret;
|
2847 |
|
2848 |
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); |
2849 |
|
2850 |
xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ |
2851 |
xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ |
2852 |
xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
|
2853 |
xhci->pci_dev.config[0x60] = 0x30; /* release number */ |
2854 |
|
2855 |
usb_xhci_init(xhci, &dev->qdev); |
2856 |
|
2857 |
xhci->irq = xhci->pci_dev.irq[0];
|
2858 |
|
2859 |
memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci, |
2860 |
"xhci", LEN_REGS);
|
2861 |
pci_register_bar(&xhci->pci_dev, 0,
|
2862 |
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, |
2863 |
&xhci->mem); |
2864 |
|
2865 |
ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); |
2866 |
assert(ret >= 0);
|
2867 |
|
2868 |
if (xhci->msi) {
|
2869 |
ret = msi_init(&xhci->pci_dev, 0x70, 1, true, false); |
2870 |
assert(ret >= 0);
|
2871 |
} |
2872 |
|
2873 |
return 0; |
2874 |
} |
2875 |
|
2876 |
static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, |
2877 |
int len)
|
2878 |
{ |
2879 |
XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); |
2880 |
|
2881 |
pci_default_write_config(dev, addr, val, len); |
2882 |
if (xhci->msi) {
|
2883 |
msi_write_config(dev, addr, val, len); |
2884 |
} |
2885 |
} |
2886 |
|
2887 |
static const VMStateDescription vmstate_xhci = { |
2888 |
.name = "xhci",
|
2889 |
.unmigratable = 1,
|
2890 |
}; |
2891 |
|
2892 |
static Property xhci_properties[] = {
|
2893 |
DEFINE_PROP_UINT32("msi", XHCIState, msi, 0), |
2894 |
DEFINE_PROP_END_OF_LIST(), |
2895 |
}; |
2896 |
|
2897 |
static void xhci_class_init(ObjectClass *klass, void *data) |
2898 |
{ |
2899 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2900 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2901 |
|
2902 |
dc->vmsd = &vmstate_xhci; |
2903 |
dc->props = xhci_properties; |
2904 |
k->init = usb_xhci_initfn; |
2905 |
k->vendor_id = PCI_VENDOR_ID_NEC; |
2906 |
k->device_id = PCI_DEVICE_ID_NEC_UPD720200; |
2907 |
k->class_id = PCI_CLASS_SERIAL_USB; |
2908 |
k->revision = 0x03;
|
2909 |
k->is_express = 1;
|
2910 |
k->config_write = xhci_write_config; |
2911 |
} |
2912 |
|
2913 |
static TypeInfo xhci_info = {
|
2914 |
.name = "nec-usb-xhci",
|
2915 |
.parent = TYPE_PCI_DEVICE, |
2916 |
.instance_size = sizeof(XHCIState),
|
2917 |
.class_init = xhci_class_init, |
2918 |
}; |
2919 |
|
2920 |
static void xhci_register_types(void) |
2921 |
{ |
2922 |
type_register_static(&xhci_info); |
2923 |
} |
2924 |
|
2925 |
type_init(xhci_register_types) |