root / hw / mips_jazz.c @ 2860e3eb
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1 | 4ce7ff6e | aurel32 | /*
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2 | 4ce7ff6e | aurel32 | * QEMU MIPS Jazz support
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3 | 4ce7ff6e | aurel32 | *
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4 | 4ce7ff6e | aurel32 | * Copyright (c) 2007-2008 Hervé Poussineau
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5 | 4ce7ff6e | aurel32 | *
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6 | 4ce7ff6e | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 4ce7ff6e | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 4ce7ff6e | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 4ce7ff6e | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 4ce7ff6e | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 4ce7ff6e | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 4ce7ff6e | aurel32 | *
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13 | 4ce7ff6e | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 4ce7ff6e | aurel32 | * all copies or substantial portions of the Software.
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15 | 4ce7ff6e | aurel32 | *
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16 | 4ce7ff6e | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 4ce7ff6e | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 4ce7ff6e | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 4ce7ff6e | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 4ce7ff6e | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 4ce7ff6e | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 4ce7ff6e | aurel32 | * THE SOFTWARE.
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23 | 4ce7ff6e | aurel32 | */
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24 | 4ce7ff6e | aurel32 | |
25 | 4ce7ff6e | aurel32 | #include "hw.h" |
26 | 4ce7ff6e | aurel32 | #include "mips.h" |
27 | b970ea8f | Blue Swirl | #include "mips_cpudevs.h" |
28 | 4ce7ff6e | aurel32 | #include "pc.h" |
29 | 4ce7ff6e | aurel32 | #include "isa.h" |
30 | 4ce7ff6e | aurel32 | #include "fdc.h" |
31 | 4ce7ff6e | aurel32 | #include "sysemu.h" |
32 | 0dfa5ef9 | Isaku Yamahata | #include "arch_init.h" |
33 | 4ce7ff6e | aurel32 | #include "boards.h" |
34 | 4ce7ff6e | aurel32 | #include "net.h" |
35 | 1cd3af54 | Gerd Hoffmann | #include "esp.h" |
36 | bba831e8 | Paul Brook | #include "mips-bios.h" |
37 | ca20cf32 | Blue Swirl | #include "loader.h" |
38 | 1d914fa0 | Isaku Yamahata | #include "mc146818rtc.h" |
39 | 2446333c | Blue Swirl | #include "blockdev.h" |
40 | 4ce7ff6e | aurel32 | |
41 | 4ce7ff6e | aurel32 | enum jazz_model_e
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42 | 4ce7ff6e | aurel32 | { |
43 | 4ce7ff6e | aurel32 | JAZZ_MAGNUM, |
44 | c171148c | aurel32 | JAZZ_PICA61, |
45 | 4ce7ff6e | aurel32 | }; |
46 | 4ce7ff6e | aurel32 | |
47 | 4ce7ff6e | aurel32 | static void main_cpu_reset(void *opaque) |
48 | 4ce7ff6e | aurel32 | { |
49 | 4ce7ff6e | aurel32 | CPUState *env = opaque; |
50 | 4ce7ff6e | aurel32 | cpu_reset(env); |
51 | 4ce7ff6e | aurel32 | } |
52 | 4ce7ff6e | aurel32 | |
53 | c227f099 | Anthony Liguori | static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr) |
54 | 4ce7ff6e | aurel32 | { |
55 | afcea8cb | Blue Swirl | return cpu_inw(0x71); |
56 | 4ce7ff6e | aurel32 | } |
57 | 4ce7ff6e | aurel32 | |
58 | c227f099 | Anthony Liguori | static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
59 | 4ce7ff6e | aurel32 | { |
60 | afcea8cb | Blue Swirl | cpu_outw(0x71, val & 0xff); |
61 | 4ce7ff6e | aurel32 | } |
62 | 4ce7ff6e | aurel32 | |
63 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const rtc_read[3] = { |
64 | 4ce7ff6e | aurel32 | rtc_readb, |
65 | 4ce7ff6e | aurel32 | rtc_readb, |
66 | 4ce7ff6e | aurel32 | rtc_readb, |
67 | 4ce7ff6e | aurel32 | }; |
68 | 4ce7ff6e | aurel32 | |
69 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const rtc_write[3] = { |
70 | 4ce7ff6e | aurel32 | rtc_writeb, |
71 | 4ce7ff6e | aurel32 | rtc_writeb, |
72 | 4ce7ff6e | aurel32 | rtc_writeb, |
73 | 4ce7ff6e | aurel32 | }; |
74 | 4ce7ff6e | aurel32 | |
75 | c227f099 | Anthony Liguori | static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
76 | c6945b15 | aurel32 | { |
77 | c6945b15 | aurel32 | /* Nothing to do. That is only to ensure that
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78 | c6945b15 | aurel32 | * the current DMA acknowledge cycle is completed. */
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79 | c6945b15 | aurel32 | } |
80 | c6945b15 | aurel32 | |
81 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const dma_dummy_read[3] = { |
82 | c6945b15 | aurel32 | NULL,
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83 | c6945b15 | aurel32 | NULL,
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84 | c6945b15 | aurel32 | NULL,
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85 | c6945b15 | aurel32 | }; |
86 | c6945b15 | aurel32 | |
87 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const dma_dummy_write[3] = { |
88 | c6945b15 | aurel32 | dma_dummy_writeb, |
89 | c6945b15 | aurel32 | dma_dummy_writeb, |
90 | c6945b15 | aurel32 | dma_dummy_writeb, |
91 | c6945b15 | aurel32 | }; |
92 | c6945b15 | aurel32 | |
93 | 4ce7ff6e | aurel32 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
94 | 4ce7ff6e | aurel32 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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95 | 4ce7ff6e | aurel32 | |
96 | 4556bd8b | Blue Swirl | static void cpu_request_exit(void *opaque, int irq, int level) |
97 | 4556bd8b | Blue Swirl | { |
98 | 4556bd8b | Blue Swirl | CPUState *env = cpu_single_env; |
99 | 4556bd8b | Blue Swirl | |
100 | 4556bd8b | Blue Swirl | if (env && level) {
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101 | 4556bd8b | Blue Swirl | cpu_exit(env); |
102 | 4556bd8b | Blue Swirl | } |
103 | 4556bd8b | Blue Swirl | } |
104 | 4556bd8b | Blue Swirl | |
105 | 4ce7ff6e | aurel32 | static
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106 | c227f099 | Anthony Liguori | void mips_jazz_init (ram_addr_t ram_size,
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107 | 3023f332 | aliguori | const char *cpu_model, |
108 | 4ce7ff6e | aurel32 | enum jazz_model_e jazz_model)
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109 | 4ce7ff6e | aurel32 | { |
110 | 5cea8590 | Paul Brook | char *filename;
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111 | 4ce7ff6e | aurel32 | int bios_size, n;
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112 | 4ce7ff6e | aurel32 | CPUState *env; |
113 | 4ce7ff6e | aurel32 | qemu_irq *rc4030, *i8259; |
114 | c6945b15 | aurel32 | rc4030_dma *dmas; |
115 | 68238a9e | aurel32 | void* rc4030_opaque;
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116 | c6945b15 | aurel32 | int s_rtc, s_dma_dummy;
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117 | a65f56ee | aurel32 | NICInfo *nd; |
118 | 64d7e9a4 | Blue Swirl | ISADevice *pit; |
119 | fd8014e1 | Gerd Hoffmann | DriveInfo *fds[MAX_FD]; |
120 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
121 | 4556bd8b | Blue Swirl | qemu_irq *cpu_exit_irq; |
122 | c227f099 | Anthony Liguori | ram_addr_t ram_offset; |
123 | c227f099 | Anthony Liguori | ram_addr_t bios_offset; |
124 | 4ce7ff6e | aurel32 | |
125 | 4ce7ff6e | aurel32 | /* init CPUs */
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126 | 4ce7ff6e | aurel32 | if (cpu_model == NULL) { |
127 | 4ce7ff6e | aurel32 | #ifdef TARGET_MIPS64
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128 | 4ce7ff6e | aurel32 | cpu_model = "R4000";
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129 | 4ce7ff6e | aurel32 | #else
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130 | 4ce7ff6e | aurel32 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
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131 | 4ce7ff6e | aurel32 | cpu_model = "24Kf";
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132 | 4ce7ff6e | aurel32 | #endif
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133 | 4ce7ff6e | aurel32 | } |
134 | 4ce7ff6e | aurel32 | env = cpu_init(cpu_model); |
135 | 4ce7ff6e | aurel32 | if (!env) {
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136 | 4ce7ff6e | aurel32 | fprintf(stderr, "Unable to find CPU definition\n");
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137 | 4ce7ff6e | aurel32 | exit(1);
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138 | 4ce7ff6e | aurel32 | } |
139 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, env); |
140 | 4ce7ff6e | aurel32 | |
141 | 4ce7ff6e | aurel32 | /* allocate RAM */
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142 | 1724f049 | Alex Williamson | ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size); |
143 | dcac9679 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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144 | dcac9679 | pbrook | |
145 | 1724f049 | Alex Williamson | bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE); |
146 | dcac9679 | pbrook | cpu_register_physical_memory(0x1fc00000LL,
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147 | dcac9679 | pbrook | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
148 | dcac9679 | pbrook | cpu_register_physical_memory(0xfff00000LL,
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149 | dcac9679 | pbrook | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
150 | 4ce7ff6e | aurel32 | |
151 | 4ce7ff6e | aurel32 | /* load the BIOS image. */
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152 | c6945b15 | aurel32 | if (bios_name == NULL) |
153 | c6945b15 | aurel32 | bios_name = BIOS_FILENAME; |
154 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
155 | 5cea8590 | Paul Brook | if (filename) {
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156 | 5cea8590 | Paul Brook | bios_size = load_image_targphys(filename, 0xfff00000LL,
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157 | 5cea8590 | Paul Brook | MAGNUM_BIOS_SIZE); |
158 | 5cea8590 | Paul Brook | qemu_free(filename); |
159 | 5cea8590 | Paul Brook | } else {
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160 | 5cea8590 | Paul Brook | bios_size = -1;
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161 | 5cea8590 | Paul Brook | } |
162 | 4ce7ff6e | aurel32 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
163 | 4ce7ff6e | aurel32 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
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164 | 5cea8590 | Paul Brook | bios_name); |
165 | 4ce7ff6e | aurel32 | exit(1);
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166 | 4ce7ff6e | aurel32 | } |
167 | 4ce7ff6e | aurel32 | |
168 | 4ce7ff6e | aurel32 | /* Init CPU internal devices */
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169 | 4ce7ff6e | aurel32 | cpu_mips_irq_init_cpu(env); |
170 | 4ce7ff6e | aurel32 | cpu_mips_clock_init(env); |
171 | 4ce7ff6e | aurel32 | |
172 | 4ce7ff6e | aurel32 | /* Chipset */
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173 | 68238a9e | aurel32 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas); |
174 | 2507c12a | Alexander Graf | s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
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175 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
176 | c6945b15 | aurel32 | cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); |
177 | 4ce7ff6e | aurel32 | |
178 | 4ce7ff6e | aurel32 | /* ISA devices */
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179 | 4ce7ff6e | aurel32 | i8259 = i8259_init(env->irq[4]);
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180 | 5041fccd | Roy Tam | isa_bus_new(NULL);
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181 | 5041fccd | Roy Tam | isa_bus_irqs(i8259); |
182 | 4556bd8b | Blue Swirl | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
183 | 4556bd8b | Blue Swirl | DMA_init(0, cpu_exit_irq);
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184 | 64d7e9a4 | Blue Swirl | pit = pit_init(0x40, 0); |
185 | 4ce7ff6e | aurel32 | pcspk_init(pit); |
186 | 4ce7ff6e | aurel32 | |
187 | 4ce7ff6e | aurel32 | /* ISA IO space at 0x90000000 */
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188 | 968d683c | Alexander Graf | isa_mmio_init(0x90000000, 0x01000000); |
189 | 4ce7ff6e | aurel32 | isa_mem_base = 0x11000000;
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190 | 4ce7ff6e | aurel32 | |
191 | 4ce7ff6e | aurel32 | /* Video card */
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192 | 4ce7ff6e | aurel32 | switch (jazz_model) {
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193 | 4ce7ff6e | aurel32 | case JAZZ_MAGNUM:
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194 | fbe1b595 | Paul Brook | g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]); |
195 | 4ce7ff6e | aurel32 | break;
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196 | c171148c | aurel32 | case JAZZ_PICA61:
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197 | fbe1b595 | Paul Brook | isa_vga_mm_init(0x40000000, 0x60000000, 0); |
198 | c171148c | aurel32 | break;
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199 | 4ce7ff6e | aurel32 | default:
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200 | 4ce7ff6e | aurel32 | break;
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201 | 4ce7ff6e | aurel32 | } |
202 | 4ce7ff6e | aurel32 | |
203 | 4ce7ff6e | aurel32 | /* Network controller */
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204 | a65f56ee | aurel32 | for (n = 0; n < nb_nics; n++) { |
205 | a65f56ee | aurel32 | nd = &nd_table[n]; |
206 | a65f56ee | aurel32 | if (!nd->model)
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207 | 9203f520 | Mark McLoughlin | nd->model = qemu_strdup("dp83932");
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208 | a65f56ee | aurel32 | if (strcmp(nd->model, "dp83932") == 0) { |
209 | a65f56ee | aurel32 | dp83932_init(nd, 0x80001000, 2, rc4030[4], |
210 | a65f56ee | aurel32 | rc4030_opaque, rc4030_dma_memory_rw); |
211 | a65f56ee | aurel32 | break;
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212 | a65f56ee | aurel32 | } else if (strcmp(nd->model, "?") == 0) { |
213 | a65f56ee | aurel32 | fprintf(stderr, "qemu: Supported NICs: dp83932\n");
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214 | a65f56ee | aurel32 | exit(1);
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215 | a65f56ee | aurel32 | } else {
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216 | a65f56ee | aurel32 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
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217 | a65f56ee | aurel32 | exit(1);
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218 | a65f56ee | aurel32 | } |
219 | a65f56ee | aurel32 | } |
220 | 4ce7ff6e | aurel32 | |
221 | 4ce7ff6e | aurel32 | /* SCSI adapter */
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222 | cfb9de9c | Paul Brook | esp_init(0x80002000, 0, |
223 | cfb9de9c | Paul Brook | rc4030_dma_read, rc4030_dma_write, dmas[0],
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224 | 73d74342 | Blue Swirl | rc4030[5], &esp_reset, &dma_enable);
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225 | 4ce7ff6e | aurel32 | |
226 | 4ce7ff6e | aurel32 | /* Floppy */
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227 | 4ce7ff6e | aurel32 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
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228 | 4ce7ff6e | aurel32 | fprintf(stderr, "qemu: too many floppy drives\n");
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229 | 4ce7ff6e | aurel32 | exit(1);
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230 | 4ce7ff6e | aurel32 | } |
231 | 4ce7ff6e | aurel32 | for (n = 0; n < MAX_FD; n++) { |
232 | fd8014e1 | Gerd Hoffmann | fds[n] = drive_get(IF_FLOPPY, 0, n);
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233 | 4ce7ff6e | aurel32 | } |
234 | 2091ba23 | Gerd Hoffmann | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
235 | 4ce7ff6e | aurel32 | |
236 | 4ce7ff6e | aurel32 | /* Real time clock */
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237 | 7d932dfd | Jan Kiszka | rtc_init(1980, NULL); |
238 | 2507c12a | Alexander Graf | s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
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239 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
240 | 4ce7ff6e | aurel32 | cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); |
241 | 4ce7ff6e | aurel32 | |
242 | 4ce7ff6e | aurel32 | /* Keyboard (i8042) */
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243 | 4efbe58f | aurel32 | i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); |
244 | 4ce7ff6e | aurel32 | |
245 | 4ce7ff6e | aurel32 | /* Serial ports */
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246 | 2d48377a | Blue Swirl | if (serial_hds[0]) { |
247 | 2d48377a | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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248 | 2d48377a | Blue Swirl | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1); |
249 | 2d48377a | Blue Swirl | #else
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250 | 2d48377a | Blue Swirl | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0); |
251 | 2d48377a | Blue Swirl | #endif
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252 | 2d48377a | Blue Swirl | } |
253 | 2d48377a | Blue Swirl | if (serial_hds[1]) { |
254 | 2d48377a | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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255 | 2d48377a | Blue Swirl | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1); |
256 | 2d48377a | Blue Swirl | #else
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257 | 2d48377a | Blue Swirl | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0); |
258 | 2d48377a | Blue Swirl | #endif
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259 | 2d48377a | Blue Swirl | } |
260 | 4ce7ff6e | aurel32 | |
261 | 4ce7ff6e | aurel32 | /* Parallel port */
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262 | 4ce7ff6e | aurel32 | if (parallel_hds[0]) |
263 | 4ce7ff6e | aurel32 | parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]); |
264 | 4ce7ff6e | aurel32 | |
265 | 4ce7ff6e | aurel32 | /* Sound card */
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266 | 4ce7ff6e | aurel32 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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267 | 0dfa5ef9 | Isaku Yamahata | audio_init(i8259, NULL);
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268 | 4ce7ff6e | aurel32 | |
269 | 4ce7ff6e | aurel32 | /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
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270 | 4ce7ff6e | aurel32 | ds1225y_init(0x80009000, "nvram"); |
271 | 4ce7ff6e | aurel32 | |
272 | 4ce7ff6e | aurel32 | /* LED indicator */
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273 | 3023f332 | aliguori | jazz_led_init(0x8000f000);
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274 | 4ce7ff6e | aurel32 | } |
275 | 4ce7ff6e | aurel32 | |
276 | 4ce7ff6e | aurel32 | static
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277 | c227f099 | Anthony Liguori | void mips_magnum_init (ram_addr_t ram_size,
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278 | 3023f332 | aliguori | const char *boot_device, |
279 | 4ce7ff6e | aurel32 | const char *kernel_filename, const char *kernel_cmdline, |
280 | 4ce7ff6e | aurel32 | const char *initrd_filename, const char *cpu_model) |
281 | 4ce7ff6e | aurel32 | { |
282 | fbe1b595 | Paul Brook | mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM); |
283 | 4ce7ff6e | aurel32 | } |
284 | 4ce7ff6e | aurel32 | |
285 | c171148c | aurel32 | static
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286 | c227f099 | Anthony Liguori | void mips_pica61_init (ram_addr_t ram_size,
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287 | 3023f332 | aliguori | const char *boot_device, |
288 | c171148c | aurel32 | const char *kernel_filename, const char *kernel_cmdline, |
289 | c171148c | aurel32 | const char *initrd_filename, const char *cpu_model) |
290 | c171148c | aurel32 | { |
291 | fbe1b595 | Paul Brook | mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61); |
292 | c171148c | aurel32 | } |
293 | c171148c | aurel32 | |
294 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_magnum_machine = {
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295 | eec2743e | ths | .name = "magnum",
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296 | eec2743e | ths | .desc = "MIPS Magnum",
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297 | eec2743e | ths | .init = mips_magnum_init, |
298 | c6945b15 | aurel32 | .use_scsi = 1,
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299 | 4ce7ff6e | aurel32 | }; |
300 | c171148c | aurel32 | |
301 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_pica61_machine = {
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302 | eec2743e | ths | .name = "pica61",
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303 | eec2743e | ths | .desc = "Acer Pica 61",
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304 | eec2743e | ths | .init = mips_pica61_init, |
305 | c6945b15 | aurel32 | .use_scsi = 1,
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306 | c171148c | aurel32 | }; |
307 | f80f9ec9 | Anthony Liguori | |
308 | f80f9ec9 | Anthony Liguori | static void mips_jazz_machine_init(void) |
309 | f80f9ec9 | Anthony Liguori | { |
310 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_magnum_machine); |
311 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_pica61_machine); |
312 | f80f9ec9 | Anthony Liguori | } |
313 | f80f9ec9 | Anthony Liguori | |
314 | f80f9ec9 | Anthony Liguori | machine_init(mips_jazz_machine_init); |