Revision 28de16da target-cris/translate.c
b/target-cris/translate.c | ||
---|---|---|
216 | 216 |
else if (r == PR_SRS) |
217 | 217 |
tcg_gen_andi_tl(cpu_PR[r], tn, 3); |
218 | 218 |
else { |
219 |
tcg_gen_mov_tl(cpu_PR[r], tn); |
|
220 | 219 |
if (r == PR_PID) |
221 | 220 |
tcg_gen_helper_0_1(helper_tlb_flush_pid, tn); |
222 | 221 |
else if (r == PR_CCS) |
223 | 222 |
dc->cpustate_changed = 1; |
223 |
tcg_gen_mov_tl(cpu_PR[r], tn); |
|
224 | 224 |
} |
225 | 225 |
} |
226 | 226 |
|
... | ... | |
1223 | 1223 |
else |
1224 | 1224 |
tcg_gen_qemu_ld16u(dst, addr, mem_index); |
1225 | 1225 |
} |
1226 |
else { |
|
1226 |
else if (size == 4) {
|
|
1227 | 1227 |
tcg_gen_qemu_ld32u(dst, addr, mem_index); |
1228 | 1228 |
} |
1229 |
else if (size == 8) { |
|
1230 |
tcg_gen_qemu_ld64(dst, addr, mem_index); |
|
1231 |
} |
|
1229 | 1232 |
} |
1230 | 1233 |
|
1231 | 1234 |
void gen_store (DisasContext *dc, TCGv addr, TCGv val, |
... | ... | |
1248 | 1251 |
return; |
1249 | 1252 |
} |
1250 | 1253 |
|
1251 |
/* Remember, operands are flipped. CRIS has reversed order. */ |
|
1252 | 1254 |
if (size == 1) |
1253 | 1255 |
tcg_gen_qemu_st8(val, addr, mem_index); |
1254 | 1256 |
else if (size == 2) |
... | ... | |
2548 | 2550 |
{ |
2549 | 2551 |
TCGv tmp[16]; |
2550 | 2552 |
int i; |
2553 |
int nr = dc->op2 + 1; |
|
2551 | 2554 |
|
2552 | 2555 |
DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1, |
2553 | 2556 |
dc->postinc ? "+]" : "]", dc->op2)); |
2554 | 2557 |
|
2555 |
/* fetch the address into T0 and T1. */
|
|
2558 |
/* There are probably better ways of doing this. */
|
|
2556 | 2559 |
cris_flush_cc_state(dc); |
2557 |
for (i = 0; i <= dc->op2; i++) { |
|
2558 |
tmp[i] = tcg_temp_new(TCG_TYPE_TL); |
|
2559 |
/* Perform the load onto regnum i. Always dword wide. */ |
|
2560 |
tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4); |
|
2560 |
for (i = 0; i < (nr >> 1); i++) { |
|
2561 |
tmp[i] = tcg_temp_new(TCG_TYPE_I64); |
|
2562 |
tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8); |
|
2563 |
gen_load(dc, tmp[i], cpu_T[0], 8, 0); |
|
2564 |
} |
|
2565 |
if (nr & 1) { |
|
2566 |
tmp[i] = tcg_temp_new(TCG_TYPE_I32); |
|
2567 |
tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 8); |
|
2561 | 2568 |
gen_load(dc, tmp[i], cpu_T[0], 4, 0); |
2562 | 2569 |
} |
2563 | 2570 |
|
2564 |
for (i = 0; i <= dc->op2; i++) { |
|
2565 |
tcg_gen_mov_tl(cpu_R[i], tmp[i]); |
|
2571 |
for (i = 0; i < (nr >> 1); i++) { |
|
2572 |
tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]); |
|
2573 |
tcg_gen_shri_i64(tmp[i], tmp[i], 32); |
|
2574 |
tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]); |
|
2575 |
tcg_temp_free(tmp[i]); |
|
2576 |
} |
|
2577 |
if (nr & 1) { |
|
2578 |
tcg_gen_mov_tl(cpu_R[dc->op2], tmp[i]); |
|
2566 | 2579 |
tcg_temp_free(tmp[i]); |
2567 | 2580 |
} |
2568 | 2581 |
|
2569 | 2582 |
/* writeback the updated pointer value. */ |
2570 | 2583 |
if (dc->postinc) |
2571 |
tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
|
|
2584 |
tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
|
|
2572 | 2585 |
|
2573 | 2586 |
/* gen_load might want to evaluate the previous insns flags. */ |
2574 | 2587 |
cris_cc_mask(dc, 0); |
... | ... | |
2948 | 2961 |
unsigned int insn_len = 2; |
2949 | 2962 |
int i; |
2950 | 2963 |
|
2964 |
if (unlikely(loglevel & CPU_LOG_TB_OP)) |
|
2965 |
tcg_gen_debug_insn_start(dc->pc); |
|
2966 |
|
|
2951 | 2967 |
/* Load a halfword onto the instruction register. */ |
2952 | 2968 |
dc->ir = lduw_code(dc->pc); |
2953 | 2969 |
|
... | ... | |
3131 | 3147 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
3132 | 3148 |
gen_io_start(); |
3133 | 3149 |
dc->clear_x = 1; |
3134 |
if (unlikely(loglevel & CPU_LOG_TB_OP)) |
|
3135 |
tcg_gen_debug_insn_start(dc->pc); |
|
3136 |
insn_len = cris_decoder(dc); |
|
3150 |
|
|
3151 |
insn_len = cris_decoder(dc); |
|
3137 | 3152 |
dc->ppc = dc->pc; |
3138 | 3153 |
dc->pc += insn_len; |
3139 | 3154 |
if (dc->clear_x) |
... | ... | |
3357 | 3372 |
} |
3358 | 3373 |
|
3359 | 3374 |
TCG_HELPER(helper_raise_exception); |
3360 |
TCG_HELPER(helper_store); |
|
3361 | 3375 |
TCG_HELPER(helper_dump); |
3362 |
TCG_HELPER(helper_dummy); |
|
3363 | 3376 |
|
3364 | 3377 |
TCG_HELPER(helper_tlb_flush_pid); |
3365 | 3378 |
TCG_HELPER(helper_movl_sreg_reg); |
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