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/*
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* i386 CPUID helper functions
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "kvm.h" |
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#include "qemu-option.h" |
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#include "qemu-config.h" |
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#include "hyperv.h" |
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/* feature flags taken from "Intel Processor Identification and the CPUID
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* Instruction" and AMD's "CPUID Specification". In cases of disagreement
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* between feature naming conventions, aliases may be added.
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*/
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static const char *feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8", "apic", NULL, "sep", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, |
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NULL, "ds" /* Intel dts */, "acpi", "mmx", |
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"fxsr", "sse", "sse2", "ss", |
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"ht" /* Intel htt */, "tm", "ia64", "pbe", |
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}; |
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static const char *ext_feature_name[] = { |
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"pni|sse3" /* Intel,AMD sse3 */, "pclmuldq", "dtes64", "monitor", |
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"ds_cpl", "vmx", "smx", "est", |
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"tm2", "ssse3", "cid", NULL, |
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"fma", "cx16", "xtpr", "pdcm", |
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NULL, NULL, "dca", "sse4.1|sse4_1", |
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"sse4.2|sse4_2", "x2apic", "movbe", "popcnt", |
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NULL, "aes", "xsave", "osxsave", |
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"avx", NULL, NULL, "hypervisor", |
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}; |
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static const char *ext2_feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", NULL, NULL /* Linux mp */, |
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"nx" /* Intel xd */, NULL, "mmxext", "mmx", |
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"fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp", |
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NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow", |
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}; |
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static const char *ext3_feature_name[] = { |
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"lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, |
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"cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", |
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"3dnowprefetch", "osvw", "ibs", "xop", |
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"skinit", "wdt", NULL, NULL, |
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"fma4", NULL, "cvt16", "nodeid_msr", |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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}; |
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static const char *kvm_feature_name[] = { |
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"kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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}; |
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static const char *svm_feature_name[] = { |
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"npt", "lbrv", "svm_lock", "nrip_save", |
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"tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", |
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NULL, NULL, "pause_filter", NULL, |
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"pfthreshold", NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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}; |
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/* collects per-function cpuid data
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*/
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typedef struct model_features_t { |
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uint32_t *guest_feat; |
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uint32_t *host_feat; |
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uint32_t check_feat; |
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const char **flag_names; |
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uint32_t cpuid; |
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} model_features_t; |
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int check_cpuid = 0; |
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int enforce_cpuid = 0; |
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void host_cpuid(uint32_t function, uint32_t count,
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uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) |
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{ |
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#if defined(CONFIG_KVM)
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uint32_t vec[4];
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#ifdef __x86_64__
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asm volatile("cpuid" |
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: "=a"(vec[0]), "=b"(vec[1]), |
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"=c"(vec[2]), "=d"(vec[3]) |
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: "0"(function), "c"(count) : "cc"); |
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#else
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asm volatile("pusha \n\t" |
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"cpuid \n\t"
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"mov %%eax, 0(%2) \n\t"
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"mov %%ebx, 4(%2) \n\t"
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"mov %%ecx, 8(%2) \n\t"
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"mov %%edx, 12(%2) \n\t"
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"popa"
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: : "a"(function), "c"(count), "S"(vec) |
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: "memory", "cc"); |
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#endif
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if (eax)
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*eax = vec[0];
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if (ebx)
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*ebx = vec[1];
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if (ecx)
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*ecx = vec[2];
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if (edx)
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*edx = vec[3];
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#endif
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} |
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#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c))) |
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/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
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* a substring. ex if !NULL points to the first char after a substring,
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* otherwise the string is assumed to sized by a terminating nul.
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* Return lexical ordering of *s1:*s2.
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*/
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static int sstrcmp(const char *s1, const char *e1, const char *s2, |
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const char *e2) |
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{ |
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for (;;) {
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if (!*s1 || !*s2 || *s1 != *s2)
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return (*s1 - *s2);
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++s1, ++s2; |
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if (s1 == e1 && s2 == e2)
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return (0); |
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else if (s1 == e1) |
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return (*s2);
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else if (s2 == e2) |
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return (*s1);
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} |
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} |
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/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
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* '|' delimited (possibly empty) strings in which case search for a match
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* within the alternatives proceeds left to right. Return 0 for success,
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* non-zero otherwise.
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*/
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static int altcmp(const char *s, const char *e, const char *altstr) |
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{ |
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const char *p, *q; |
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for (q = p = altstr; ; ) {
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while (*p && *p != '|') |
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++p; |
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if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
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return (0); |
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if (!*p)
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return (1); |
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else
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q = ++p; |
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} |
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} |
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/* search featureset for flag *[s..e), if found set corresponding bit in
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* *pval and return true, otherwise return false
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*/
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static bool lookup_feature(uint32_t *pval, const char *s, const char *e, |
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const char **featureset) |
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{ |
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uint32_t mask; |
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const char **ppc; |
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bool found = false; |
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for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) { |
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if (*ppc && !altcmp(s, e, *ppc)) {
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*pval |= mask; |
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found = true;
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} |
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} |
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return found;
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} |
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static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features, |
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uint32_t *ext_features, |
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uint32_t *ext2_features, |
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uint32_t *ext3_features, |
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uint32_t *kvm_features, |
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uint32_t *svm_features) |
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{ |
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if (!lookup_feature(features, flagname, NULL, feature_name) && |
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!lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
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!lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
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!lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
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!lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
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!lookup_feature(svm_features, flagname, NULL, svm_feature_name))
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fprintf(stderr, "CPU feature %s not found\n", flagname);
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} |
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typedef struct x86_def_t { |
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struct x86_def_t *next;
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const char *name; |
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uint32_t level; |
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uint32_t vendor1, vendor2, vendor3; |
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int family;
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int model;
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int stepping;
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int tsc_khz;
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uint32_t features, ext_features, ext2_features, ext3_features; |
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uint32_t kvm_features, svm_features; |
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uint32_t xlevel; |
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char model_id[48]; |
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int vendor_override;
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uint32_t flags; |
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/* Store the results of Centaur's CPUID instructions */
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uint32_t ext4_features; |
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uint32_t xlevel2; |
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} x86_def_t; |
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) |
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#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
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CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ |
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CPUID_PSE36 | CPUID_FXSR) |
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#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
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#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ |
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CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ |
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CPUID_PAE | CPUID_SEP | CPUID_APIC) |
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#define EXT2_FEATURE_MASK 0x0183F3FF |
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#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
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CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ |
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CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ |
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CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ |
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CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) |
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/* partly implemented:
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CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
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CPUID_PSE36 (needed for Solaris) */
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/* missing:
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CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
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#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
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CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ |
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CPUID_EXT_HYPERVISOR) |
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/* missing:
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CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
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CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
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#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
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CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ |
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT) |
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/* missing:
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CPUID_EXT2_PDPE1GB */
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#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
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CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) |
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#define TCG_SVM_FEATURES 0 |
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/* maintains list of cpu model definitions
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*/
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static x86_def_t *x86_defs = {NULL}; |
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/* built-in cpu model definitions (deprecated)
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*/
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static x86_def_t builtin_x86_defs[] = {
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{ |
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.name = "qemu64",
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.level = 4,
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 6,
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.model = 2,
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.stepping = 3,
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, |
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
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.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
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.xlevel = 0x8000000A,
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.model_id = "QEMU Virtual CPU version " QEMU_VERSION,
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}, |
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{ |
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.name = "phenom",
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.level = 5,
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 16,
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.model = 2,
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.stepping = 3,
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36 | CPUID_VME | CPUID_HT, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | |
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CPUID_EXT_POPCNT, |
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | |
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | |
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CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, |
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/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
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CPUID_EXT3_CR8LEG,
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CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
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CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
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.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
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.svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV, |
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.xlevel = 0x8000001A,
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.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
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}, |
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{ |
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.name = "core2duo",
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.level = 10,
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.family = 6,
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.model = 15,
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.stepping = 11,
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.features = PPRO_FEATURES | |
341 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS | |
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CPUID_HT | CPUID_TM | CPUID_PBE, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
345 |
CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST | |
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CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, |
347 |
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
348 |
.ext3_features = CPUID_EXT3_LAHF_LM, |
349 |
.xlevel = 0x80000008,
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.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
|
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}, |
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{ |
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.name = "kvm64",
|
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.level = 5,
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.vendor1 = CPUID_VENDOR_INTEL_1, |
356 |
.vendor2 = CPUID_VENDOR_INTEL_2, |
357 |
.vendor3 = CPUID_VENDOR_INTEL_3, |
358 |
.family = 15,
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.model = 6,
|
360 |
.stepping = 1,
|
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/* Missing: CPUID_VME, CPUID_HT */
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.features = PPRO_FEATURES | |
363 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
364 |
CPUID_PSE36, |
365 |
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16, |
367 |
/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
|
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
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/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
|
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CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
|
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CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
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CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
|
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.ext3_features = 0,
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.xlevel = 0x80000008,
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.model_id = "Common KVM processor"
|
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}, |
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{ |
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.name = "qemu32",
|
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.level = 4,
|
381 |
.family = 6,
|
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.model = 3,
|
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.stepping = 3,
|
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.features = PPRO_FEATURES, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, |
386 |
.xlevel = 0x80000004,
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.model_id = "QEMU Virtual CPU version " QEMU_VERSION,
|
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}, |
389 |
{ |
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.name = "kvm32",
|
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.level = 5,
|
392 |
.family = 15,
|
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.model = 6,
|
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.stepping = 1,
|
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.features = PPRO_FEATURES | |
396 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, |
397 |
.ext_features = CPUID_EXT_SSE3, |
398 |
.ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK, |
399 |
.ext3_features = 0,
|
400 |
.xlevel = 0x80000008,
|
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.model_id = "Common 32-bit KVM processor"
|
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}, |
403 |
{ |
404 |
.name = "coreduo",
|
405 |
.level = 10,
|
406 |
.family = 6,
|
407 |
.model = 14,
|
408 |
.stepping = 8,
|
409 |
.features = PPRO_FEATURES | CPUID_VME | |
410 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI | |
411 |
CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, |
412 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX | |
413 |
CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, |
414 |
.ext2_features = CPUID_EXT2_NX, |
415 |
.xlevel = 0x80000008,
|
416 |
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
|
417 |
}, |
418 |
{ |
419 |
.name = "486",
|
420 |
.level = 1,
|
421 |
.family = 4,
|
422 |
.model = 0,
|
423 |
.stepping = 0,
|
424 |
.features = I486_FEATURES, |
425 |
.xlevel = 0,
|
426 |
}, |
427 |
{ |
428 |
.name = "pentium",
|
429 |
.level = 1,
|
430 |
.family = 5,
|
431 |
.model = 4,
|
432 |
.stepping = 3,
|
433 |
.features = PENTIUM_FEATURES, |
434 |
.xlevel = 0,
|
435 |
}, |
436 |
{ |
437 |
.name = "pentium2",
|
438 |
.level = 2,
|
439 |
.family = 6,
|
440 |
.model = 5,
|
441 |
.stepping = 2,
|
442 |
.features = PENTIUM2_FEATURES, |
443 |
.xlevel = 0,
|
444 |
}, |
445 |
{ |
446 |
.name = "pentium3",
|
447 |
.level = 2,
|
448 |
.family = 6,
|
449 |
.model = 7,
|
450 |
.stepping = 3,
|
451 |
.features = PENTIUM3_FEATURES, |
452 |
.xlevel = 0,
|
453 |
}, |
454 |
{ |
455 |
.name = "athlon",
|
456 |
.level = 2,
|
457 |
.vendor1 = CPUID_VENDOR_AMD_1, |
458 |
.vendor2 = CPUID_VENDOR_AMD_2, |
459 |
.vendor3 = CPUID_VENDOR_AMD_3, |
460 |
.family = 6,
|
461 |
.model = 2,
|
462 |
.stepping = 3,
|
463 |
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, |
464 |
.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, |
465 |
.xlevel = 0x80000008,
|
466 |
/* XXX: put another string ? */
|
467 |
.model_id = "QEMU Virtual CPU version " QEMU_VERSION,
|
468 |
}, |
469 |
{ |
470 |
.name = "n270",
|
471 |
/* original is on level 10 */
|
472 |
.level = 5,
|
473 |
.family = 6,
|
474 |
.model = 28,
|
475 |
.stepping = 2,
|
476 |
.features = PPRO_FEATURES | |
477 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS | |
478 |
CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, |
479 |
/* Some CPUs got no CPUID_SEP */
|
480 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
481 |
CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR, |
482 |
.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX, |
483 |
.ext3_features = CPUID_EXT3_LAHF_LM, |
484 |
.xlevel = 0x8000000A,
|
485 |
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
|
486 |
}, |
487 |
}; |
488 |
|
489 |
static int cpu_x86_fill_model_id(char *str) |
490 |
{ |
491 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
492 |
int i;
|
493 |
|
494 |
for (i = 0; i < 3; i++) { |
495 |
host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); |
496 |
memcpy(str + i * 16 + 0, &eax, 4); |
497 |
memcpy(str + i * 16 + 4, &ebx, 4); |
498 |
memcpy(str + i * 16 + 8, &ecx, 4); |
499 |
memcpy(str + i * 16 + 12, &edx, 4); |
500 |
} |
501 |
return 0; |
502 |
} |
503 |
|
504 |
static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) |
505 |
{ |
506 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
507 |
|
508 |
x86_cpu_def->name = "host";
|
509 |
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); |
510 |
x86_cpu_def->level = eax; |
511 |
x86_cpu_def->vendor1 = ebx; |
512 |
x86_cpu_def->vendor2 = edx; |
513 |
x86_cpu_def->vendor3 = ecx; |
514 |
|
515 |
host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); |
516 |
x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); |
517 |
x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); |
518 |
x86_cpu_def->stepping = eax & 0x0F;
|
519 |
x86_cpu_def->ext_features = ecx; |
520 |
x86_cpu_def->features = edx; |
521 |
|
522 |
host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx); |
523 |
x86_cpu_def->xlevel = eax; |
524 |
|
525 |
host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx); |
526 |
x86_cpu_def->ext2_features = edx; |
527 |
x86_cpu_def->ext3_features = ecx; |
528 |
cpu_x86_fill_model_id(x86_cpu_def->model_id); |
529 |
x86_cpu_def->vendor_override = 0;
|
530 |
|
531 |
/* Call Centaur's CPUID instruction. */
|
532 |
if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
|
533 |
x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 && |
534 |
x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) { |
535 |
host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); |
536 |
if (eax >= 0xC0000001) { |
537 |
/* Support VIA max extended level */
|
538 |
x86_cpu_def->xlevel2 = eax; |
539 |
host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); |
540 |
x86_cpu_def->ext4_features = edx; |
541 |
} |
542 |
} |
543 |
|
544 |
/*
|
545 |
* Every SVM feature requires emulation support in KVM - so we can't just
|
546 |
* read the host features here. KVM might even support SVM features not
|
547 |
* available on the host hardware. Just set all bits and mask out the
|
548 |
* unsupported ones later.
|
549 |
*/
|
550 |
x86_cpu_def->svm_features = -1;
|
551 |
|
552 |
return 0; |
553 |
} |
554 |
|
555 |
static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) |
556 |
{ |
557 |
int i;
|
558 |
|
559 |
for (i = 0; i < 32; ++i) |
560 |
if (1 << i & mask) { |
561 |
fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
|
562 |
" flag '%s' [0x%08x]\n",
|
563 |
f->cpuid >> 16, f->cpuid & 0xffff, |
564 |
f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
|
565 |
break;
|
566 |
} |
567 |
return 0; |
568 |
} |
569 |
|
570 |
/* best effort attempt to inform user requested cpu flags aren't making
|
571 |
* their way to the guest. Note: ft[].check_feat ideally should be
|
572 |
* specified via a guest_def field to suppress report of extraneous flags.
|
573 |
*/
|
574 |
static int check_features_against_host(x86_def_t *guest_def) |
575 |
{ |
576 |
x86_def_t host_def; |
577 |
uint32_t mask; |
578 |
int rv, i;
|
579 |
struct model_features_t ft[] = {
|
580 |
{&guest_def->features, &host_def.features, |
581 |
~0, feature_name, 0x00000000}, |
582 |
{&guest_def->ext_features, &host_def.ext_features, |
583 |
~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
|
584 |
{&guest_def->ext2_features, &host_def.ext2_features, |
585 |
~PPRO_FEATURES, ext2_feature_name, 0x80000000},
|
586 |
{&guest_def->ext3_features, &host_def.ext3_features, |
587 |
~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
|
588 |
|
589 |
cpu_x86_fill_host(&host_def); |
590 |
for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) |
591 |
for (mask = 1; mask; mask <<= 1) |
592 |
if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
|
593 |
!(*ft[i].host_feat & mask)) { |
594 |
unavailable_host_feature(&ft[i], mask); |
595 |
rv = 1;
|
596 |
} |
597 |
return rv;
|
598 |
} |
599 |
|
600 |
static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) |
601 |
{ |
602 |
unsigned int i; |
603 |
x86_def_t *def; |
604 |
|
605 |
char *s = g_strdup(cpu_model);
|
606 |
char *featurestr, *name = strtok(s, ","); |
607 |
/* Features to be added*/
|
608 |
uint32_t plus_features = 0, plus_ext_features = 0; |
609 |
uint32_t plus_ext2_features = 0, plus_ext3_features = 0; |
610 |
uint32_t plus_kvm_features = 0, plus_svm_features = 0; |
611 |
/* Features to be removed */
|
612 |
uint32_t minus_features = 0, minus_ext_features = 0; |
613 |
uint32_t minus_ext2_features = 0, minus_ext3_features = 0; |
614 |
uint32_t minus_kvm_features = 0, minus_svm_features = 0; |
615 |
uint32_t numvalue; |
616 |
|
617 |
for (def = x86_defs; def; def = def->next)
|
618 |
if (name && !strcmp(name, def->name))
|
619 |
break;
|
620 |
if (kvm_enabled() && name && strcmp(name, "host") == 0) { |
621 |
cpu_x86_fill_host(x86_cpu_def); |
622 |
} else if (!def) { |
623 |
goto error;
|
624 |
} else {
|
625 |
memcpy(x86_cpu_def, def, sizeof(*def));
|
626 |
} |
627 |
|
628 |
plus_kvm_features = ~0; /* not supported bits will be filtered out later */ |
629 |
|
630 |
add_flagname_to_bitmaps("hypervisor", &plus_features,
|
631 |
&plus_ext_features, &plus_ext2_features, &plus_ext3_features, |
632 |
&plus_kvm_features, &plus_svm_features); |
633 |
|
634 |
featurestr = strtok(NULL, ","); |
635 |
|
636 |
while (featurestr) {
|
637 |
char *val;
|
638 |
if (featurestr[0] == '+') { |
639 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features,
|
640 |
&plus_ext_features, &plus_ext2_features, |
641 |
&plus_ext3_features, &plus_kvm_features, |
642 |
&plus_svm_features); |
643 |
} else if (featurestr[0] == '-') { |
644 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features,
|
645 |
&minus_ext_features, &minus_ext2_features, |
646 |
&minus_ext3_features, &minus_kvm_features, |
647 |
&minus_svm_features); |
648 |
} else if ((val = strchr(featurestr, '='))) { |
649 |
*val = 0; val++;
|
650 |
if (!strcmp(featurestr, "family")) { |
651 |
char *err;
|
652 |
numvalue = strtoul(val, &err, 0);
|
653 |
if (!*val || *err) {
|
654 |
fprintf(stderr, "bad numerical value %s\n", val);
|
655 |
goto error;
|
656 |
} |
657 |
x86_cpu_def->family = numvalue; |
658 |
} else if (!strcmp(featurestr, "model")) { |
659 |
char *err;
|
660 |
numvalue = strtoul(val, &err, 0);
|
661 |
if (!*val || *err || numvalue > 0xff) { |
662 |
fprintf(stderr, "bad numerical value %s\n", val);
|
663 |
goto error;
|
664 |
} |
665 |
x86_cpu_def->model = numvalue; |
666 |
} else if (!strcmp(featurestr, "stepping")) { |
667 |
char *err;
|
668 |
numvalue = strtoul(val, &err, 0);
|
669 |
if (!*val || *err || numvalue > 0xf) { |
670 |
fprintf(stderr, "bad numerical value %s\n", val);
|
671 |
goto error;
|
672 |
} |
673 |
x86_cpu_def->stepping = numvalue ; |
674 |
} else if (!strcmp(featurestr, "level")) { |
675 |
char *err;
|
676 |
numvalue = strtoul(val, &err, 0);
|
677 |
if (!*val || *err) {
|
678 |
fprintf(stderr, "bad numerical value %s\n", val);
|
679 |
goto error;
|
680 |
} |
681 |
x86_cpu_def->level = numvalue; |
682 |
} else if (!strcmp(featurestr, "xlevel")) { |
683 |
char *err;
|
684 |
numvalue = strtoul(val, &err, 0);
|
685 |
if (!*val || *err) {
|
686 |
fprintf(stderr, "bad numerical value %s\n", val);
|
687 |
goto error;
|
688 |
} |
689 |
if (numvalue < 0x80000000) { |
690 |
numvalue += 0x80000000;
|
691 |
} |
692 |
x86_cpu_def->xlevel = numvalue; |
693 |
} else if (!strcmp(featurestr, "vendor")) { |
694 |
if (strlen(val) != 12) { |
695 |
fprintf(stderr, "vendor string must be 12 chars long\n");
|
696 |
goto error;
|
697 |
} |
698 |
x86_cpu_def->vendor1 = 0;
|
699 |
x86_cpu_def->vendor2 = 0;
|
700 |
x86_cpu_def->vendor3 = 0;
|
701 |
for(i = 0; i < 4; i++) { |
702 |
x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
|
703 |
x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i); |
704 |
x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i); |
705 |
} |
706 |
x86_cpu_def->vendor_override = 1;
|
707 |
} else if (!strcmp(featurestr, "model_id")) { |
708 |
pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
|
709 |
val); |
710 |
} else if (!strcmp(featurestr, "tsc_freq")) { |
711 |
int64_t tsc_freq; |
712 |
char *err;
|
713 |
|
714 |
tsc_freq = strtosz_suffix_unit(val, &err, |
715 |
STRTOSZ_DEFSUFFIX_B, 1000);
|
716 |
if (tsc_freq < 0 || *err) { |
717 |
fprintf(stderr, "bad numerical value %s\n", val);
|
718 |
goto error;
|
719 |
} |
720 |
x86_cpu_def->tsc_khz = tsc_freq / 1000;
|
721 |
} else if (!strcmp(featurestr, "hv_spinlocks")) { |
722 |
char *err;
|
723 |
numvalue = strtoul(val, &err, 0);
|
724 |
if (!*val || *err) {
|
725 |
fprintf(stderr, "bad numerical value %s\n", val);
|
726 |
goto error;
|
727 |
} |
728 |
hyperv_set_spinlock_retries(numvalue); |
729 |
} else {
|
730 |
fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
731 |
goto error;
|
732 |
} |
733 |
} else if (!strcmp(featurestr, "check")) { |
734 |
check_cpuid = 1;
|
735 |
} else if (!strcmp(featurestr, "enforce")) { |
736 |
check_cpuid = enforce_cpuid = 1;
|
737 |
} else if (!strcmp(featurestr, "hv_relaxed")) { |
738 |
hyperv_enable_relaxed_timing(true);
|
739 |
} else if (!strcmp(featurestr, "hv_vapic")) { |
740 |
hyperv_enable_vapic_recommended(true);
|
741 |
} else {
|
742 |
fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
|
743 |
goto error;
|
744 |
} |
745 |
featurestr = strtok(NULL, ","); |
746 |
} |
747 |
x86_cpu_def->features |= plus_features; |
748 |
x86_cpu_def->ext_features |= plus_ext_features; |
749 |
x86_cpu_def->ext2_features |= plus_ext2_features; |
750 |
x86_cpu_def->ext3_features |= plus_ext3_features; |
751 |
x86_cpu_def->kvm_features |= plus_kvm_features; |
752 |
x86_cpu_def->svm_features |= plus_svm_features; |
753 |
x86_cpu_def->features &= ~minus_features; |
754 |
x86_cpu_def->ext_features &= ~minus_ext_features; |
755 |
x86_cpu_def->ext2_features &= ~minus_ext2_features; |
756 |
x86_cpu_def->ext3_features &= ~minus_ext3_features; |
757 |
x86_cpu_def->kvm_features &= ~minus_kvm_features; |
758 |
x86_cpu_def->svm_features &= ~minus_svm_features; |
759 |
if (check_cpuid) {
|
760 |
if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
|
761 |
goto error;
|
762 |
} |
763 |
g_free(s); |
764 |
return 0; |
765 |
|
766 |
error:
|
767 |
g_free(s); |
768 |
return -1; |
769 |
} |
770 |
|
771 |
/* generate a composite string into buf of all cpuid names in featureset
|
772 |
* selected by fbits. indicate truncation at bufsize in the event of overflow.
|
773 |
* if flags, suppress names undefined in featureset.
|
774 |
*/
|
775 |
static void listflags(char *buf, int bufsize, uint32_t fbits, |
776 |
const char **featureset, uint32_t flags) |
777 |
{ |
778 |
const char **p = &featureset[31]; |
779 |
char *q, *b, bit;
|
780 |
int nc;
|
781 |
|
782 |
b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL; |
783 |
*buf = '\0';
|
784 |
for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit) |
785 |
if (fbits & 1 << bit && (*p || !flags)) { |
786 |
if (*p)
|
787 |
nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p); |
788 |
else
|
789 |
nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit); |
790 |
if (bufsize <= nc) {
|
791 |
if (b) {
|
792 |
memcpy(b, "...", sizeof("...")); |
793 |
} |
794 |
return;
|
795 |
} |
796 |
q += nc; |
797 |
bufsize -= nc; |
798 |
} |
799 |
} |
800 |
|
801 |
/* generate CPU information:
|
802 |
* -? list model names
|
803 |
* -?model list model names/IDs
|
804 |
* -?dump output all model (x86_def_t) data
|
805 |
* -?cpuid list all recognized cpuid flag names
|
806 |
*/
|
807 |
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg) |
808 |
{ |
809 |
unsigned char model = !strcmp("?model", optarg); |
810 |
unsigned char dump = !strcmp("?dump", optarg); |
811 |
unsigned char cpuid = !strcmp("?cpuid", optarg); |
812 |
x86_def_t *def; |
813 |
char buf[256]; |
814 |
|
815 |
if (cpuid) {
|
816 |
(*cpu_fprintf)(f, "Recognized CPUID flags:\n");
|
817 |
listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1); |
818 |
(*cpu_fprintf)(f, " f_edx: %s\n", buf);
|
819 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1); |
820 |
(*cpu_fprintf)(f, " f_ecx: %s\n", buf);
|
821 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1); |
822 |
(*cpu_fprintf)(f, " extf_edx: %s\n", buf);
|
823 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1); |
824 |
(*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
|
825 |
return;
|
826 |
} |
827 |
for (def = x86_defs; def; def = def->next) {
|
828 |
snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name); |
829 |
if (model || dump) {
|
830 |
(*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
|
831 |
} else {
|
832 |
(*cpu_fprintf)(f, "x86 %16s\n", buf);
|
833 |
} |
834 |
if (dump) {
|
835 |
memcpy(buf, &def->vendor1, sizeof (def->vendor1));
|
836 |
memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2)); |
837 |
memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3)); |
838 |
buf[12] = '\0'; |
839 |
(*cpu_fprintf)(f, |
840 |
" family %d model %d stepping %d level %d xlevel 0x%x"
|
841 |
" vendor \"%s\"\n",
|
842 |
def->family, def->model, def->stepping, def->level, |
843 |
def->xlevel, buf); |
844 |
listflags(buf, sizeof (buf), def->features, feature_name, 0); |
845 |
(*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
|
846 |
buf); |
847 |
listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
|
848 |
0);
|
849 |
(*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
|
850 |
buf); |
851 |
listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
|
852 |
0);
|
853 |
(*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
|
854 |
def->ext2_features, buf); |
855 |
listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
|
856 |
0);
|
857 |
(*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
|
858 |
def->ext3_features, buf); |
859 |
(*cpu_fprintf)(f, "\n");
|
860 |
} |
861 |
} |
862 |
if (kvm_enabled()) {
|
863 |
(*cpu_fprintf)(f, "x86 %16s\n", "[host]"); |
864 |
} |
865 |
} |
866 |
|
867 |
int cpu_x86_register (CPUX86State *env, const char *cpu_model) |
868 |
{ |
869 |
x86_def_t def1, *def = &def1; |
870 |
|
871 |
memset(def, 0, sizeof(*def)); |
872 |
|
873 |
if (cpu_x86_find_by_name(def, cpu_model) < 0) |
874 |
return -1; |
875 |
if (def->vendor1) {
|
876 |
env->cpuid_vendor1 = def->vendor1; |
877 |
env->cpuid_vendor2 = def->vendor2; |
878 |
env->cpuid_vendor3 = def->vendor3; |
879 |
} else {
|
880 |
env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1; |
881 |
env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2; |
882 |
env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3; |
883 |
} |
884 |
env->cpuid_vendor_override = def->vendor_override; |
885 |
env->cpuid_level = def->level; |
886 |
if (def->family > 0x0f) |
887 |
env->cpuid_version = 0xf00 | ((def->family - 0x0f) << 20); |
888 |
else
|
889 |
env->cpuid_version = def->family << 8;
|
890 |
env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16); |
891 |
env->cpuid_version |= def->stepping; |
892 |
env->cpuid_features = def->features; |
893 |
env->cpuid_ext_features = def->ext_features; |
894 |
env->cpuid_ext2_features = def->ext2_features; |
895 |
env->cpuid_ext3_features = def->ext3_features; |
896 |
env->cpuid_xlevel = def->xlevel; |
897 |
env->cpuid_kvm_features = def->kvm_features; |
898 |
env->cpuid_svm_features = def->svm_features; |
899 |
env->cpuid_ext4_features = def->ext4_features; |
900 |
env->cpuid_xlevel2 = def->xlevel2; |
901 |
env->tsc_khz = def->tsc_khz; |
902 |
if (!kvm_enabled()) {
|
903 |
env->cpuid_features &= TCG_FEATURES; |
904 |
env->cpuid_ext_features &= TCG_EXT_FEATURES; |
905 |
env->cpuid_ext2_features &= (TCG_EXT2_FEATURES |
906 |
#ifdef TARGET_X86_64
|
907 |
| CPUID_EXT2_SYSCALL | CPUID_EXT2_LM |
908 |
#endif
|
909 |
); |
910 |
env->cpuid_ext3_features &= TCG_EXT3_FEATURES; |
911 |
env->cpuid_svm_features &= TCG_SVM_FEATURES; |
912 |
} |
913 |
{ |
914 |
const char *model_id = def->model_id; |
915 |
int c, len, i;
|
916 |
if (!model_id)
|
917 |
model_id = "";
|
918 |
len = strlen(model_id); |
919 |
for(i = 0; i < 48; i++) { |
920 |
if (i >= len)
|
921 |
c = '\0';
|
922 |
else
|
923 |
c = (uint8_t)model_id[i]; |
924 |
env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); |
925 |
} |
926 |
} |
927 |
return 0; |
928 |
} |
929 |
|
930 |
#if !defined(CONFIG_USER_ONLY)
|
931 |
/* copy vendor id string to 32 bit register, nul pad as needed
|
932 |
*/
|
933 |
static void cpyid(const char *s, uint32_t *id) |
934 |
{ |
935 |
char *d = (char *)id; |
936 |
char i;
|
937 |
|
938 |
for (i = sizeof (*id); i--; ) |
939 |
*d++ = *s ? *s++ : '\0';
|
940 |
} |
941 |
|
942 |
/* interpret radix and convert from string to arbitrary scalar,
|
943 |
* otherwise flag failure
|
944 |
*/
|
945 |
#define setscalar(pval, str, perr) \
|
946 |
{ \ |
947 |
char *pend; \
|
948 |
unsigned long ul; \ |
949 |
\ |
950 |
ul = strtoul(str, &pend, 0); \
|
951 |
*str && !*pend ? (*pval = ul) : (*perr = 1); \
|
952 |
} |
953 |
|
954 |
/* map cpuid options to feature bits, otherwise return failure
|
955 |
* (option tags in *str are delimited by whitespace)
|
956 |
*/
|
957 |
static void setfeatures(uint32_t *pval, const char *str, |
958 |
const char **featureset, int *perr) |
959 |
{ |
960 |
const char *p, *q; |
961 |
|
962 |
for (q = p = str; *p || *q; q = p) {
|
963 |
while (iswhite(*p))
|
964 |
q = ++p; |
965 |
while (*p && !iswhite(*p))
|
966 |
++p; |
967 |
if (!*q && !*p)
|
968 |
return;
|
969 |
if (!lookup_feature(pval, q, p, featureset)) {
|
970 |
fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
|
971 |
(int)(p - q), q);
|
972 |
*perr = 1;
|
973 |
return;
|
974 |
} |
975 |
} |
976 |
} |
977 |
|
978 |
/* map config file options to x86_def_t form
|
979 |
*/
|
980 |
static int cpudef_setfield(const char *name, const char *str, void *opaque) |
981 |
{ |
982 |
x86_def_t *def = opaque; |
983 |
int err = 0; |
984 |
|
985 |
if (!strcmp(name, "name")) { |
986 |
g_free((void *)def->name);
|
987 |
def->name = g_strdup(str); |
988 |
} else if (!strcmp(name, "model_id")) { |
989 |
strncpy(def->model_id, str, sizeof (def->model_id));
|
990 |
} else if (!strcmp(name, "level")) { |
991 |
setscalar(&def->level, str, &err) |
992 |
} else if (!strcmp(name, "vendor")) { |
993 |
cpyid(&str[0], &def->vendor1);
|
994 |
cpyid(&str[4], &def->vendor2);
|
995 |
cpyid(&str[8], &def->vendor3);
|
996 |
} else if (!strcmp(name, "family")) { |
997 |
setscalar(&def->family, str, &err) |
998 |
} else if (!strcmp(name, "model")) { |
999 |
setscalar(&def->model, str, &err) |
1000 |
} else if (!strcmp(name, "stepping")) { |
1001 |
setscalar(&def->stepping, str, &err) |
1002 |
} else if (!strcmp(name, "feature_edx")) { |
1003 |
setfeatures(&def->features, str, feature_name, &err); |
1004 |
} else if (!strcmp(name, "feature_ecx")) { |
1005 |
setfeatures(&def->ext_features, str, ext_feature_name, &err); |
1006 |
} else if (!strcmp(name, "extfeature_edx")) { |
1007 |
setfeatures(&def->ext2_features, str, ext2_feature_name, &err); |
1008 |
} else if (!strcmp(name, "extfeature_ecx")) { |
1009 |
setfeatures(&def->ext3_features, str, ext3_feature_name, &err); |
1010 |
} else if (!strcmp(name, "xlevel")) { |
1011 |
setscalar(&def->xlevel, str, &err) |
1012 |
} else {
|
1013 |
fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
|
1014 |
return (1); |
1015 |
} |
1016 |
if (err) {
|
1017 |
fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
|
1018 |
return (1); |
1019 |
} |
1020 |
return (0); |
1021 |
} |
1022 |
|
1023 |
/* register config file entry as x86_def_t
|
1024 |
*/
|
1025 |
static int cpudef_register(QemuOpts *opts, void *opaque) |
1026 |
{ |
1027 |
x86_def_t *def = g_malloc0(sizeof (x86_def_t));
|
1028 |
|
1029 |
qemu_opt_foreach(opts, cpudef_setfield, def, 1);
|
1030 |
def->next = x86_defs; |
1031 |
x86_defs = def; |
1032 |
return (0); |
1033 |
} |
1034 |
|
1035 |
void cpu_clear_apic_feature(CPUX86State *env)
|
1036 |
{ |
1037 |
env->cpuid_features &= ~CPUID_APIC; |
1038 |
} |
1039 |
|
1040 |
#endif /* !CONFIG_USER_ONLY */ |
1041 |
|
1042 |
/* register "cpudef" models defined in configuration file. Here we first
|
1043 |
* preload any built-in definitions
|
1044 |
*/
|
1045 |
void x86_cpudef_setup(void) |
1046 |
{ |
1047 |
int i;
|
1048 |
|
1049 |
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { |
1050 |
builtin_x86_defs[i].next = x86_defs; |
1051 |
builtin_x86_defs[i].flags = 1;
|
1052 |
x86_defs = &builtin_x86_defs[i]; |
1053 |
} |
1054 |
#if !defined(CONFIG_USER_ONLY)
|
1055 |
qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0); |
1056 |
#endif
|
1057 |
} |
1058 |
|
1059 |
static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx, |
1060 |
uint32_t *ecx, uint32_t *edx) |
1061 |
{ |
1062 |
*ebx = env->cpuid_vendor1; |
1063 |
*edx = env->cpuid_vendor2; |
1064 |
*ecx = env->cpuid_vendor3; |
1065 |
|
1066 |
/* sysenter isn't supported on compatibility mode on AMD, syscall
|
1067 |
* isn't supported in compatibility mode on Intel.
|
1068 |
* Normally we advertise the actual cpu vendor, but you can override
|
1069 |
* this if you want to use KVM's sysenter/syscall emulation
|
1070 |
* in compatibility mode and when doing cross vendor migration
|
1071 |
*/
|
1072 |
if (kvm_enabled() && ! env->cpuid_vendor_override) {
|
1073 |
host_cpuid(0, 0, NULL, ebx, ecx, edx); |
1074 |
} |
1075 |
} |
1076 |
|
1077 |
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
1078 |
uint32_t *eax, uint32_t *ebx, |
1079 |
uint32_t *ecx, uint32_t *edx) |
1080 |
{ |
1081 |
/* test if maximum index reached */
|
1082 |
if (index & 0x80000000) { |
1083 |
if (index > env->cpuid_xlevel) {
|
1084 |
if (env->cpuid_xlevel2 > 0) { |
1085 |
/* Handle the Centaur's CPUID instruction. */
|
1086 |
if (index > env->cpuid_xlevel2) {
|
1087 |
index = env->cpuid_xlevel2; |
1088 |
} else if (index < 0xC0000000) { |
1089 |
index = env->cpuid_xlevel; |
1090 |
} |
1091 |
} else {
|
1092 |
index = env->cpuid_xlevel; |
1093 |
} |
1094 |
} |
1095 |
} else {
|
1096 |
if (index > env->cpuid_level)
|
1097 |
index = env->cpuid_level; |
1098 |
} |
1099 |
|
1100 |
switch(index) {
|
1101 |
case 0: |
1102 |
*eax = env->cpuid_level; |
1103 |
get_cpuid_vendor(env, ebx, ecx, edx); |
1104 |
break;
|
1105 |
case 1: |
1106 |
*eax = env->cpuid_version; |
1107 |
*ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ |
1108 |
*ecx = env->cpuid_ext_features; |
1109 |
*edx = env->cpuid_features; |
1110 |
if (env->nr_cores * env->nr_threads > 1) { |
1111 |
*ebx |= (env->nr_cores * env->nr_threads) << 16;
|
1112 |
*edx |= 1 << 28; /* HTT bit */ |
1113 |
} |
1114 |
break;
|
1115 |
case 2: |
1116 |
/* cache info: needed for Pentium Pro compatibility */
|
1117 |
*eax = 1;
|
1118 |
*ebx = 0;
|
1119 |
*ecx = 0;
|
1120 |
*edx = 0x2c307d;
|
1121 |
break;
|
1122 |
case 4: |
1123 |
/* cache info: needed for Core compatibility */
|
1124 |
if (env->nr_cores > 1) { |
1125 |
*eax = (env->nr_cores - 1) << 26; |
1126 |
} else {
|
1127 |
*eax = 0;
|
1128 |
} |
1129 |
switch (count) {
|
1130 |
case 0: /* L1 dcache info */ |
1131 |
*eax |= 0x0000121;
|
1132 |
*ebx = 0x1c0003f;
|
1133 |
*ecx = 0x000003f;
|
1134 |
*edx = 0x0000001;
|
1135 |
break;
|
1136 |
case 1: /* L1 icache info */ |
1137 |
*eax |= 0x0000122;
|
1138 |
*ebx = 0x1c0003f;
|
1139 |
*ecx = 0x000003f;
|
1140 |
*edx = 0x0000001;
|
1141 |
break;
|
1142 |
case 2: /* L2 cache info */ |
1143 |
*eax |= 0x0000143;
|
1144 |
if (env->nr_threads > 1) { |
1145 |
*eax |= (env->nr_threads - 1) << 14; |
1146 |
} |
1147 |
*ebx = 0x3c0003f;
|
1148 |
*ecx = 0x0000fff;
|
1149 |
*edx = 0x0000001;
|
1150 |
break;
|
1151 |
default: /* end of info */ |
1152 |
*eax = 0;
|
1153 |
*ebx = 0;
|
1154 |
*ecx = 0;
|
1155 |
*edx = 0;
|
1156 |
break;
|
1157 |
} |
1158 |
break;
|
1159 |
case 5: |
1160 |
/* mwait info: needed for Core compatibility */
|
1161 |
*eax = 0; /* Smallest monitor-line size in bytes */ |
1162 |
*ebx = 0; /* Largest monitor-line size in bytes */ |
1163 |
*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; |
1164 |
*edx = 0;
|
1165 |
break;
|
1166 |
case 6: |
1167 |
/* Thermal and Power Leaf */
|
1168 |
*eax = 0;
|
1169 |
*ebx = 0;
|
1170 |
*ecx = 0;
|
1171 |
*edx = 0;
|
1172 |
break;
|
1173 |
case 7: |
1174 |
if (kvm_enabled()) {
|
1175 |
KVMState *s = env->kvm_state; |
1176 |
|
1177 |
*eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
|
1178 |
*ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
|
1179 |
*ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
|
1180 |
*edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
|
1181 |
} else {
|
1182 |
*eax = 0;
|
1183 |
*ebx = 0;
|
1184 |
*ecx = 0;
|
1185 |
*edx = 0;
|
1186 |
} |
1187 |
break;
|
1188 |
case 9: |
1189 |
/* Direct Cache Access Information Leaf */
|
1190 |
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */ |
1191 |
*ebx = 0;
|
1192 |
*ecx = 0;
|
1193 |
*edx = 0;
|
1194 |
break;
|
1195 |
case 0xA: |
1196 |
/* Architectural Performance Monitoring Leaf */
|
1197 |
if (kvm_enabled()) {
|
1198 |
KVMState *s = env->kvm_state; |
1199 |
|
1200 |
*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
|
1201 |
*ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
|
1202 |
*ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
|
1203 |
*edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
|
1204 |
} else {
|
1205 |
*eax = 0;
|
1206 |
*ebx = 0;
|
1207 |
*ecx = 0;
|
1208 |
*edx = 0;
|
1209 |
} |
1210 |
break;
|
1211 |
case 0xD: |
1212 |
/* Processor Extended State */
|
1213 |
if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
|
1214 |
*eax = 0;
|
1215 |
*ebx = 0;
|
1216 |
*ecx = 0;
|
1217 |
*edx = 0;
|
1218 |
break;
|
1219 |
} |
1220 |
if (kvm_enabled()) {
|
1221 |
KVMState *s = env->kvm_state; |
1222 |
|
1223 |
*eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
|
1224 |
*ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
|
1225 |
*ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
|
1226 |
*edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
|
1227 |
} else {
|
1228 |
*eax = 0;
|
1229 |
*ebx = 0;
|
1230 |
*ecx = 0;
|
1231 |
*edx = 0;
|
1232 |
} |
1233 |
break;
|
1234 |
case 0x80000000: |
1235 |
*eax = env->cpuid_xlevel; |
1236 |
*ebx = env->cpuid_vendor1; |
1237 |
*edx = env->cpuid_vendor2; |
1238 |
*ecx = env->cpuid_vendor3; |
1239 |
break;
|
1240 |
case 0x80000001: |
1241 |
*eax = env->cpuid_version; |
1242 |
*ebx = 0;
|
1243 |
*ecx = env->cpuid_ext3_features; |
1244 |
*edx = env->cpuid_ext2_features; |
1245 |
|
1246 |
/* The Linux kernel checks for the CMPLegacy bit and
|
1247 |
* discards multiple thread information if it is set.
|
1248 |
* So dont set it here for Intel to make Linux guests happy.
|
1249 |
*/
|
1250 |
if (env->nr_cores * env->nr_threads > 1) { |
1251 |
uint32_t tebx, tecx, tedx; |
1252 |
get_cpuid_vendor(env, &tebx, &tecx, &tedx); |
1253 |
if (tebx != CPUID_VENDOR_INTEL_1 ||
|
1254 |
tedx != CPUID_VENDOR_INTEL_2 || |
1255 |
tecx != CPUID_VENDOR_INTEL_3) { |
1256 |
*ecx |= 1 << 1; /* CmpLegacy bit */ |
1257 |
} |
1258 |
} |
1259 |
break;
|
1260 |
case 0x80000002: |
1261 |
case 0x80000003: |
1262 |
case 0x80000004: |
1263 |
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; |
1264 |
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; |
1265 |
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; |
1266 |
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; |
1267 |
break;
|
1268 |
case 0x80000005: |
1269 |
/* cache info (L1 cache) */
|
1270 |
*eax = 0x01ff01ff;
|
1271 |
*ebx = 0x01ff01ff;
|
1272 |
*ecx = 0x40020140;
|
1273 |
*edx = 0x40020140;
|
1274 |
break;
|
1275 |
case 0x80000006: |
1276 |
/* cache info (L2 cache) */
|
1277 |
*eax = 0;
|
1278 |
*ebx = 0x42004200;
|
1279 |
*ecx = 0x02008140;
|
1280 |
*edx = 0;
|
1281 |
break;
|
1282 |
case 0x80000008: |
1283 |
/* virtual & phys address size in low 2 bytes. */
|
1284 |
/* XXX: This value must match the one used in the MMU code. */
|
1285 |
if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
|
1286 |
/* 64 bit processor */
|
1287 |
/* XXX: The physical address space is limited to 42 bits in exec.c. */
|
1288 |
*eax = 0x00003028; /* 48 bits virtual, 40 bits physical */ |
1289 |
} else {
|
1290 |
if (env->cpuid_features & CPUID_PSE36)
|
1291 |
*eax = 0x00000024; /* 36 bits physical */ |
1292 |
else
|
1293 |
*eax = 0x00000020; /* 32 bits physical */ |
1294 |
} |
1295 |
*ebx = 0;
|
1296 |
*ecx = 0;
|
1297 |
*edx = 0;
|
1298 |
if (env->nr_cores * env->nr_threads > 1) { |
1299 |
*ecx |= (env->nr_cores * env->nr_threads) - 1;
|
1300 |
} |
1301 |
break;
|
1302 |
case 0x8000000A: |
1303 |
if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
|
1304 |
*eax = 0x00000001; /* SVM Revision */ |
1305 |
*ebx = 0x00000010; /* nr of ASIDs */ |
1306 |
*ecx = 0;
|
1307 |
*edx = env->cpuid_svm_features; /* optional features */
|
1308 |
} else {
|
1309 |
*eax = 0;
|
1310 |
*ebx = 0;
|
1311 |
*ecx = 0;
|
1312 |
*edx = 0;
|
1313 |
} |
1314 |
break;
|
1315 |
case 0xC0000000: |
1316 |
*eax = env->cpuid_xlevel2; |
1317 |
*ebx = 0;
|
1318 |
*ecx = 0;
|
1319 |
*edx = 0;
|
1320 |
break;
|
1321 |
case 0xC0000001: |
1322 |
/* Support for VIA CPU's CPUID instruction */
|
1323 |
*eax = env->cpuid_version; |
1324 |
*ebx = 0;
|
1325 |
*ecx = 0;
|
1326 |
*edx = env->cpuid_ext4_features; |
1327 |
break;
|
1328 |
case 0xC0000002: |
1329 |
case 0xC0000003: |
1330 |
case 0xC0000004: |
1331 |
/* Reserved for the future, and now filled with zero */
|
1332 |
*eax = 0;
|
1333 |
*ebx = 0;
|
1334 |
*ecx = 0;
|
1335 |
*edx = 0;
|
1336 |
break;
|
1337 |
default:
|
1338 |
/* reserved values: zero */
|
1339 |
*eax = 0;
|
1340 |
*ebx = 0;
|
1341 |
*ecx = 0;
|
1342 |
*edx = 0;
|
1343 |
break;
|
1344 |
} |
1345 |
} |