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1 | 574bbf7b | bellard | /*
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2 | 574bbf7b | bellard | * APIC support
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3 | 5fafdf24 | ths | *
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4 | 574bbf7b | bellard | * Copyright (c) 2004-2005 Fabrice Bellard
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5 | 574bbf7b | bellard | *
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6 | 574bbf7b | bellard | * This library is free software; you can redistribute it and/or
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7 | 574bbf7b | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 574bbf7b | bellard | * License as published by the Free Software Foundation; either
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9 | 574bbf7b | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 574bbf7b | bellard | *
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11 | 574bbf7b | bellard | * This library is distributed in the hope that it will be useful,
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12 | 574bbf7b | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 574bbf7b | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 574bbf7b | bellard | * Lesser General Public License for more details.
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15 | 574bbf7b | bellard | *
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16 | 574bbf7b | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 574bbf7b | bellard | * License along with this library; if not, write to the Free Software
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18 | 574bbf7b | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 574bbf7b | bellard | */
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20 | 87ecb68b | pbrook | #include "hw.h" |
21 | 87ecb68b | pbrook | #include "pc.h" |
22 | 87ecb68b | pbrook | #include "qemu-timer.h" |
23 | 574bbf7b | bellard | |
24 | 574bbf7b | bellard | //#define DEBUG_APIC
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25 | d592d303 | bellard | //#define DEBUG_IOAPIC
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26 | 574bbf7b | bellard | |
27 | 574bbf7b | bellard | /* APIC Local Vector Table */
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28 | 574bbf7b | bellard | #define APIC_LVT_TIMER 0 |
29 | 574bbf7b | bellard | #define APIC_LVT_THERMAL 1 |
30 | 574bbf7b | bellard | #define APIC_LVT_PERFORM 2 |
31 | 574bbf7b | bellard | #define APIC_LVT_LINT0 3 |
32 | 574bbf7b | bellard | #define APIC_LVT_LINT1 4 |
33 | 574bbf7b | bellard | #define APIC_LVT_ERROR 5 |
34 | 574bbf7b | bellard | #define APIC_LVT_NB 6 |
35 | 574bbf7b | bellard | |
36 | 574bbf7b | bellard | /* APIC delivery modes */
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37 | 574bbf7b | bellard | #define APIC_DM_FIXED 0 |
38 | 574bbf7b | bellard | #define APIC_DM_LOWPRI 1 |
39 | 574bbf7b | bellard | #define APIC_DM_SMI 2 |
40 | 574bbf7b | bellard | #define APIC_DM_NMI 4 |
41 | 574bbf7b | bellard | #define APIC_DM_INIT 5 |
42 | 574bbf7b | bellard | #define APIC_DM_SIPI 6 |
43 | 574bbf7b | bellard | #define APIC_DM_EXTINT 7 |
44 | 574bbf7b | bellard | |
45 | d592d303 | bellard | /* APIC destination mode */
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46 | d592d303 | bellard | #define APIC_DESTMODE_FLAT 0xf |
47 | d592d303 | bellard | #define APIC_DESTMODE_CLUSTER 1 |
48 | d592d303 | bellard | |
49 | 574bbf7b | bellard | #define APIC_TRIGGER_EDGE 0 |
50 | 574bbf7b | bellard | #define APIC_TRIGGER_LEVEL 1 |
51 | 574bbf7b | bellard | |
52 | 574bbf7b | bellard | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
53 | 574bbf7b | bellard | #define APIC_LVT_MASKED (1<<16) |
54 | 574bbf7b | bellard | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
55 | 574bbf7b | bellard | #define APIC_LVT_REMOTE_IRR (1<<14) |
56 | 574bbf7b | bellard | #define APIC_INPUT_POLARITY (1<<13) |
57 | 574bbf7b | bellard | #define APIC_SEND_PENDING (1<<12) |
58 | 574bbf7b | bellard | |
59 | d592d303 | bellard | #define IOAPIC_NUM_PINS 0x18 |
60 | d592d303 | bellard | |
61 | 574bbf7b | bellard | #define ESR_ILLEGAL_ADDRESS (1 << 7) |
62 | 574bbf7b | bellard | |
63 | 574bbf7b | bellard | #define APIC_SV_ENABLE (1 << 8) |
64 | 574bbf7b | bellard | |
65 | d3e9db93 | bellard | #define MAX_APICS 255 |
66 | d3e9db93 | bellard | #define MAX_APIC_WORDS 8 |
67 | d3e9db93 | bellard | |
68 | 574bbf7b | bellard | typedef struct APICState { |
69 | 574bbf7b | bellard | CPUState *cpu_env; |
70 | 574bbf7b | bellard | uint32_t apicbase; |
71 | 574bbf7b | bellard | uint8_t id; |
72 | d592d303 | bellard | uint8_t arb_id; |
73 | 574bbf7b | bellard | uint8_t tpr; |
74 | 574bbf7b | bellard | uint32_t spurious_vec; |
75 | d592d303 | bellard | uint8_t log_dest; |
76 | d592d303 | bellard | uint8_t dest_mode; |
77 | 574bbf7b | bellard | uint32_t isr[8]; /* in service register */ |
78 | 574bbf7b | bellard | uint32_t tmr[8]; /* trigger mode register */ |
79 | 574bbf7b | bellard | uint32_t irr[8]; /* interrupt request register */ |
80 | 574bbf7b | bellard | uint32_t lvt[APIC_LVT_NB]; |
81 | 574bbf7b | bellard | uint32_t esr; /* error register */
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82 | 574bbf7b | bellard | uint32_t icr[2];
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83 | 574bbf7b | bellard | |
84 | 574bbf7b | bellard | uint32_t divide_conf; |
85 | 574bbf7b | bellard | int count_shift;
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86 | 574bbf7b | bellard | uint32_t initial_count; |
87 | 574bbf7b | bellard | int64_t initial_count_load_time, next_time; |
88 | 574bbf7b | bellard | QEMUTimer *timer; |
89 | 574bbf7b | bellard | } APICState; |
90 | 574bbf7b | bellard | |
91 | d592d303 | bellard | struct IOAPICState {
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92 | d592d303 | bellard | uint8_t id; |
93 | d592d303 | bellard | uint8_t ioregsel; |
94 | d592d303 | bellard | |
95 | d592d303 | bellard | uint32_t irr; |
96 | d592d303 | bellard | uint64_t ioredtbl[IOAPIC_NUM_PINS]; |
97 | d592d303 | bellard | }; |
98 | d592d303 | bellard | |
99 | 574bbf7b | bellard | static int apic_io_memory; |
100 | d3e9db93 | bellard | static APICState *local_apics[MAX_APICS + 1]; |
101 | d592d303 | bellard | static int last_apic_id = 0; |
102 | d592d303 | bellard | |
103 | d592d303 | bellard | static void apic_init_ipi(APICState *s); |
104 | d592d303 | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
105 | d592d303 | bellard | static void apic_update_irq(APICState *s); |
106 | d592d303 | bellard | |
107 | d3e9db93 | bellard | /* Find first bit starting from msb. Return 0 if value = 0 */
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108 | d3e9db93 | bellard | static int fls_bit(uint32_t value) |
109 | d3e9db93 | bellard | { |
110 | d3e9db93 | bellard | unsigned int ret = 0; |
111 | d3e9db93 | bellard | |
112 | d3e9db93 | bellard | #if defined(HOST_I386)
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113 | d3e9db93 | bellard | __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value)); |
114 | d3e9db93 | bellard | return ret;
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115 | d3e9db93 | bellard | #else
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116 | d3e9db93 | bellard | if (value > 0xffff) |
117 | d3e9db93 | bellard | value >>= 16, ret = 16; |
118 | d3e9db93 | bellard | if (value > 0xff) |
119 | d3e9db93 | bellard | value >>= 8, ret += 8; |
120 | d3e9db93 | bellard | if (value > 0xf) |
121 | d3e9db93 | bellard | value >>= 4, ret += 4; |
122 | d3e9db93 | bellard | if (value > 0x3) |
123 | d3e9db93 | bellard | value >>= 2, ret += 2; |
124 | d3e9db93 | bellard | return ret + (value >> 1); |
125 | d3e9db93 | bellard | #endif
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126 | d3e9db93 | bellard | } |
127 | d3e9db93 | bellard | |
128 | d3e9db93 | bellard | /* Find first bit starting from lsb. Return 0 if value = 0 */
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129 | d3e9db93 | bellard | static int ffs_bit(uint32_t value) |
130 | d3e9db93 | bellard | { |
131 | d3e9db93 | bellard | unsigned int ret = 0; |
132 | d3e9db93 | bellard | |
133 | d3e9db93 | bellard | #if defined(HOST_I386)
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134 | d3e9db93 | bellard | __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value)); |
135 | d3e9db93 | bellard | return ret;
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136 | d3e9db93 | bellard | #else
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137 | d3e9db93 | bellard | if (!value)
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138 | d3e9db93 | bellard | return 0; |
139 | d3e9db93 | bellard | if (!(value & 0xffff)) |
140 | d3e9db93 | bellard | value >>= 16, ret = 16; |
141 | d3e9db93 | bellard | if (!(value & 0xff)) |
142 | d3e9db93 | bellard | value >>= 8, ret += 8; |
143 | d3e9db93 | bellard | if (!(value & 0xf)) |
144 | d3e9db93 | bellard | value >>= 4, ret += 4; |
145 | d3e9db93 | bellard | if (!(value & 0x3)) |
146 | d3e9db93 | bellard | value >>= 2, ret += 2; |
147 | d3e9db93 | bellard | if (!(value & 0x1)) |
148 | d3e9db93 | bellard | ret++; |
149 | d3e9db93 | bellard | return ret;
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150 | d3e9db93 | bellard | #endif
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151 | d3e9db93 | bellard | } |
152 | d3e9db93 | bellard | |
153 | d3e9db93 | bellard | static inline void set_bit(uint32_t *tab, int index) |
154 | d3e9db93 | bellard | { |
155 | d3e9db93 | bellard | int i, mask;
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156 | d3e9db93 | bellard | i = index >> 5;
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157 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
158 | d3e9db93 | bellard | tab[i] |= mask; |
159 | d3e9db93 | bellard | } |
160 | d3e9db93 | bellard | |
161 | d3e9db93 | bellard | static inline void reset_bit(uint32_t *tab, int index) |
162 | d3e9db93 | bellard | { |
163 | d3e9db93 | bellard | int i, mask;
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164 | d3e9db93 | bellard | i = index >> 5;
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165 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
166 | d3e9db93 | bellard | tab[i] &= ~mask; |
167 | d3e9db93 | bellard | } |
168 | d3e9db93 | bellard | |
169 | d3e9db93 | bellard | #define foreach_apic(apic, deliver_bitmask, code) \
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170 | d3e9db93 | bellard | {\ |
171 | d3e9db93 | bellard | int __i, __j, __mask;\
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172 | d3e9db93 | bellard | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
173 | d3e9db93 | bellard | __mask = deliver_bitmask[__i];\ |
174 | d3e9db93 | bellard | if (__mask) {\
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175 | d3e9db93 | bellard | for(__j = 0; __j < 32; __j++) {\ |
176 | d3e9db93 | bellard | if (__mask & (1 << __j)) {\ |
177 | d3e9db93 | bellard | apic = local_apics[__i * 32 + __j];\
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178 | d3e9db93 | bellard | if (apic) {\
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179 | d3e9db93 | bellard | code;\ |
180 | d3e9db93 | bellard | }\ |
181 | d3e9db93 | bellard | }\ |
182 | d3e9db93 | bellard | }\ |
183 | d3e9db93 | bellard | }\ |
184 | d3e9db93 | bellard | }\ |
185 | d3e9db93 | bellard | } |
186 | d3e9db93 | bellard | |
187 | 5fafdf24 | ths | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
188 | d3e9db93 | bellard | uint8_t delivery_mode, |
189 | d592d303 | bellard | uint8_t vector_num, uint8_t polarity, |
190 | d592d303 | bellard | uint8_t trigger_mode) |
191 | d592d303 | bellard | { |
192 | d592d303 | bellard | APICState *apic_iter; |
193 | d592d303 | bellard | |
194 | d592d303 | bellard | switch (delivery_mode) {
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195 | d592d303 | bellard | case APIC_DM_LOWPRI:
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196 | 8dd69b8f | bellard | /* XXX: search for focus processor, arbitration */
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197 | d3e9db93 | bellard | { |
198 | d3e9db93 | bellard | int i, d;
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199 | d3e9db93 | bellard | d = -1;
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200 | d3e9db93 | bellard | for(i = 0; i < MAX_APIC_WORDS; i++) { |
201 | d3e9db93 | bellard | if (deliver_bitmask[i]) {
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202 | d3e9db93 | bellard | d = i * 32 + ffs_bit(deliver_bitmask[i]);
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203 | d3e9db93 | bellard | break;
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204 | d3e9db93 | bellard | } |
205 | d3e9db93 | bellard | } |
206 | d3e9db93 | bellard | if (d >= 0) { |
207 | d3e9db93 | bellard | apic_iter = local_apics[d]; |
208 | d3e9db93 | bellard | if (apic_iter) {
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209 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode); |
210 | d3e9db93 | bellard | } |
211 | d3e9db93 | bellard | } |
212 | 8dd69b8f | bellard | } |
213 | d3e9db93 | bellard | return;
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214 | 8dd69b8f | bellard | |
215 | d592d303 | bellard | case APIC_DM_FIXED:
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216 | d592d303 | bellard | break;
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217 | d592d303 | bellard | |
218 | d592d303 | bellard | case APIC_DM_SMI:
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219 | d592d303 | bellard | case APIC_DM_NMI:
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220 | d592d303 | bellard | break;
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221 | d592d303 | bellard | |
222 | d592d303 | bellard | case APIC_DM_INIT:
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223 | d592d303 | bellard | /* normal INIT IPI sent to processors */
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224 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
225 | d3e9db93 | bellard | apic_init_ipi(apic_iter) ); |
226 | d592d303 | bellard | return;
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227 | 3b46e624 | ths | |
228 | d592d303 | bellard | case APIC_DM_EXTINT:
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229 | b1fc0348 | bellard | /* handled in I/O APIC code */
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230 | d592d303 | bellard | break;
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231 | d592d303 | bellard | |
232 | d592d303 | bellard | default:
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233 | d592d303 | bellard | return;
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234 | d592d303 | bellard | } |
235 | d592d303 | bellard | |
236 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
237 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
238 | d592d303 | bellard | } |
239 | 574bbf7b | bellard | |
240 | 574bbf7b | bellard | void cpu_set_apic_base(CPUState *env, uint64_t val)
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241 | 574bbf7b | bellard | { |
242 | 574bbf7b | bellard | APICState *s = env->apic_state; |
243 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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244 | 26a76461 | bellard | printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
245 | 574bbf7b | bellard | #endif
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246 | 5fafdf24 | ths | s->apicbase = (val & 0xfffff000) |
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247 | 574bbf7b | bellard | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
248 | 574bbf7b | bellard | /* if disabled, cannot be enabled again */
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249 | 574bbf7b | bellard | if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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250 | 574bbf7b | bellard | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
251 | 574bbf7b | bellard | env->cpuid_features &= ~CPUID_APIC; |
252 | 574bbf7b | bellard | s->spurious_vec &= ~APIC_SV_ENABLE; |
253 | 574bbf7b | bellard | } |
254 | 574bbf7b | bellard | } |
255 | 574bbf7b | bellard | |
256 | 574bbf7b | bellard | uint64_t cpu_get_apic_base(CPUState *env) |
257 | 574bbf7b | bellard | { |
258 | 574bbf7b | bellard | APICState *s = env->apic_state; |
259 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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260 | 26a76461 | bellard | printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase); |
261 | 574bbf7b | bellard | #endif
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262 | 574bbf7b | bellard | return s->apicbase;
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263 | 574bbf7b | bellard | } |
264 | 574bbf7b | bellard | |
265 | 9230e66e | bellard | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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266 | 9230e66e | bellard | { |
267 | 9230e66e | bellard | APICState *s = env->apic_state; |
268 | 9230e66e | bellard | s->tpr = (val & 0x0f) << 4; |
269 | d592d303 | bellard | apic_update_irq(s); |
270 | 9230e66e | bellard | } |
271 | 9230e66e | bellard | |
272 | 9230e66e | bellard | uint8_t cpu_get_apic_tpr(CPUX86State *env) |
273 | 9230e66e | bellard | { |
274 | 9230e66e | bellard | APICState *s = env->apic_state; |
275 | 9230e66e | bellard | return s->tpr >> 4; |
276 | 9230e66e | bellard | } |
277 | 9230e66e | bellard | |
278 | d592d303 | bellard | /* return -1 if no bit is set */
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279 | d592d303 | bellard | static int get_highest_priority_int(uint32_t *tab) |
280 | d592d303 | bellard | { |
281 | d592d303 | bellard | int i;
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282 | d592d303 | bellard | for(i = 7; i >= 0; i--) { |
283 | d592d303 | bellard | if (tab[i] != 0) { |
284 | d592d303 | bellard | return i * 32 + fls_bit(tab[i]); |
285 | d592d303 | bellard | } |
286 | d592d303 | bellard | } |
287 | d592d303 | bellard | return -1; |
288 | d592d303 | bellard | } |
289 | d592d303 | bellard | |
290 | 574bbf7b | bellard | static int apic_get_ppr(APICState *s) |
291 | 574bbf7b | bellard | { |
292 | 574bbf7b | bellard | int tpr, isrv, ppr;
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293 | 574bbf7b | bellard | |
294 | 574bbf7b | bellard | tpr = (s->tpr >> 4);
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295 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
296 | 574bbf7b | bellard | if (isrv < 0) |
297 | 574bbf7b | bellard | isrv = 0;
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298 | 574bbf7b | bellard | isrv >>= 4;
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299 | 574bbf7b | bellard | if (tpr >= isrv)
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300 | 574bbf7b | bellard | ppr = s->tpr; |
301 | 574bbf7b | bellard | else
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302 | 574bbf7b | bellard | ppr = isrv << 4;
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303 | 574bbf7b | bellard | return ppr;
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304 | 574bbf7b | bellard | } |
305 | 574bbf7b | bellard | |
306 | d592d303 | bellard | static int apic_get_arb_pri(APICState *s) |
307 | d592d303 | bellard | { |
308 | d592d303 | bellard | /* XXX: arbitration */
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309 | d592d303 | bellard | return 0; |
310 | d592d303 | bellard | } |
311 | d592d303 | bellard | |
312 | 574bbf7b | bellard | /* signal the CPU if an irq is pending */
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313 | 574bbf7b | bellard | static void apic_update_irq(APICState *s) |
314 | 574bbf7b | bellard | { |
315 | d592d303 | bellard | int irrv, ppr;
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316 | d592d303 | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
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317 | d592d303 | bellard | return;
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318 | 574bbf7b | bellard | irrv = get_highest_priority_int(s->irr); |
319 | 574bbf7b | bellard | if (irrv < 0) |
320 | 574bbf7b | bellard | return;
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321 | d592d303 | bellard | ppr = apic_get_ppr(s); |
322 | d592d303 | bellard | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
323 | 574bbf7b | bellard | return;
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324 | 574bbf7b | bellard | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
325 | 574bbf7b | bellard | } |
326 | 574bbf7b | bellard | |
327 | 574bbf7b | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
328 | 574bbf7b | bellard | { |
329 | 574bbf7b | bellard | set_bit(s->irr, vector_num); |
330 | 574bbf7b | bellard | if (trigger_mode)
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331 | 574bbf7b | bellard | set_bit(s->tmr, vector_num); |
332 | 574bbf7b | bellard | else
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333 | 574bbf7b | bellard | reset_bit(s->tmr, vector_num); |
334 | 574bbf7b | bellard | apic_update_irq(s); |
335 | 574bbf7b | bellard | } |
336 | 574bbf7b | bellard | |
337 | 574bbf7b | bellard | static void apic_eoi(APICState *s) |
338 | 574bbf7b | bellard | { |
339 | 574bbf7b | bellard | int isrv;
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340 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
341 | 574bbf7b | bellard | if (isrv < 0) |
342 | 574bbf7b | bellard | return;
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343 | 574bbf7b | bellard | reset_bit(s->isr, isrv); |
344 | d592d303 | bellard | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
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345 | d592d303 | bellard | set the remote IRR bit for level triggered interrupts. */
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346 | 574bbf7b | bellard | apic_update_irq(s); |
347 | 574bbf7b | bellard | } |
348 | 574bbf7b | bellard | |
349 | d3e9db93 | bellard | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
350 | d3e9db93 | bellard | uint8_t dest, uint8_t dest_mode) |
351 | d592d303 | bellard | { |
352 | d592d303 | bellard | APICState *apic_iter; |
353 | d3e9db93 | bellard | int i;
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354 | d592d303 | bellard | |
355 | d592d303 | bellard | if (dest_mode == 0) { |
356 | d3e9db93 | bellard | if (dest == 0xff) { |
357 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
358 | d3e9db93 | bellard | } else {
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359 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
360 | d3e9db93 | bellard | set_bit(deliver_bitmask, dest); |
361 | d3e9db93 | bellard | } |
362 | d592d303 | bellard | } else {
|
363 | d592d303 | bellard | /* XXX: cluster mode */
|
364 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
365 | d3e9db93 | bellard | for(i = 0; i < MAX_APICS; i++) { |
366 | d3e9db93 | bellard | apic_iter = local_apics[i]; |
367 | d3e9db93 | bellard | if (apic_iter) {
|
368 | d3e9db93 | bellard | if (apic_iter->dest_mode == 0xf) { |
369 | d3e9db93 | bellard | if (dest & apic_iter->log_dest)
|
370 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
371 | d3e9db93 | bellard | } else if (apic_iter->dest_mode == 0x0) { |
372 | d3e9db93 | bellard | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
373 | d3e9db93 | bellard | (dest & apic_iter->log_dest & 0x0f)) {
|
374 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
375 | d3e9db93 | bellard | } |
376 | d3e9db93 | bellard | } |
377 | d3e9db93 | bellard | } |
378 | d592d303 | bellard | } |
379 | d592d303 | bellard | } |
380 | d592d303 | bellard | } |
381 | d592d303 | bellard | |
382 | d592d303 | bellard | |
383 | d592d303 | bellard | static void apic_init_ipi(APICState *s) |
384 | d592d303 | bellard | { |
385 | d592d303 | bellard | int i;
|
386 | d592d303 | bellard | |
387 | d592d303 | bellard | s->tpr = 0;
|
388 | d592d303 | bellard | s->spurious_vec = 0xff;
|
389 | d592d303 | bellard | s->log_dest = 0;
|
390 | e0fd8781 | bellard | s->dest_mode = 0xf;
|
391 | d592d303 | bellard | memset(s->isr, 0, sizeof(s->isr)); |
392 | d592d303 | bellard | memset(s->tmr, 0, sizeof(s->tmr)); |
393 | d592d303 | bellard | memset(s->irr, 0, sizeof(s->irr)); |
394 | b4511723 | bellard | for(i = 0; i < APIC_LVT_NB; i++) |
395 | b4511723 | bellard | s->lvt[i] = 1 << 16; /* mask LVT */ |
396 | d592d303 | bellard | s->esr = 0;
|
397 | d592d303 | bellard | memset(s->icr, 0, sizeof(s->icr)); |
398 | d592d303 | bellard | s->divide_conf = 0;
|
399 | d592d303 | bellard | s->count_shift = 0;
|
400 | d592d303 | bellard | s->initial_count = 0;
|
401 | d592d303 | bellard | s->initial_count_load_time = 0;
|
402 | d592d303 | bellard | s->next_time = 0;
|
403 | d592d303 | bellard | } |
404 | d592d303 | bellard | |
405 | e0fd8781 | bellard | /* send a SIPI message to the CPU to start it */
|
406 | e0fd8781 | bellard | static void apic_startup(APICState *s, int vector_num) |
407 | e0fd8781 | bellard | { |
408 | e0fd8781 | bellard | CPUState *env = s->cpu_env; |
409 | 8dd69b8f | bellard | if (!(env->hflags & HF_HALTED_MASK))
|
410 | e0fd8781 | bellard | return;
|
411 | e0fd8781 | bellard | env->eip = 0;
|
412 | 5fafdf24 | ths | cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, |
413 | e0fd8781 | bellard | 0xffff, 0); |
414 | 8dd69b8f | bellard | env->hflags &= ~HF_HALTED_MASK; |
415 | e0fd8781 | bellard | } |
416 | e0fd8781 | bellard | |
417 | d592d303 | bellard | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
418 | d592d303 | bellard | uint8_t delivery_mode, uint8_t vector_num, |
419 | d592d303 | bellard | uint8_t polarity, uint8_t trigger_mode) |
420 | d592d303 | bellard | { |
421 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
422 | d592d303 | bellard | int dest_shorthand = (s->icr[0] >> 18) & 3; |
423 | d592d303 | bellard | APICState *apic_iter; |
424 | d592d303 | bellard | |
425 | e0fd8781 | bellard | switch (dest_shorthand) {
|
426 | d3e9db93 | bellard | case 0: |
427 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
428 | d3e9db93 | bellard | break;
|
429 | d3e9db93 | bellard | case 1: |
430 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
431 | d3e9db93 | bellard | set_bit(deliver_bitmask, s->id); |
432 | d3e9db93 | bellard | break;
|
433 | d3e9db93 | bellard | case 2: |
434 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
435 | d3e9db93 | bellard | break;
|
436 | d3e9db93 | bellard | case 3: |
437 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
438 | d3e9db93 | bellard | reset_bit(deliver_bitmask, s->id); |
439 | d3e9db93 | bellard | break;
|
440 | e0fd8781 | bellard | } |
441 | e0fd8781 | bellard | |
442 | d592d303 | bellard | switch (delivery_mode) {
|
443 | d592d303 | bellard | case APIC_DM_INIT:
|
444 | d592d303 | bellard | { |
445 | d592d303 | bellard | int trig_mode = (s->icr[0] >> 15) & 1; |
446 | d592d303 | bellard | int level = (s->icr[0] >> 14) & 1; |
447 | d592d303 | bellard | if (level == 0 && trig_mode == 1) { |
448 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
449 | d3e9db93 | bellard | apic_iter->arb_id = apic_iter->id ); |
450 | d592d303 | bellard | return;
|
451 | d592d303 | bellard | } |
452 | d592d303 | bellard | } |
453 | d592d303 | bellard | break;
|
454 | d592d303 | bellard | |
455 | d592d303 | bellard | case APIC_DM_SIPI:
|
456 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
457 | d3e9db93 | bellard | apic_startup(apic_iter, vector_num) ); |
458 | d592d303 | bellard | return;
|
459 | d592d303 | bellard | } |
460 | d592d303 | bellard | |
461 | d592d303 | bellard | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
462 | d592d303 | bellard | trigger_mode); |
463 | d592d303 | bellard | } |
464 | d592d303 | bellard | |
465 | 574bbf7b | bellard | int apic_get_interrupt(CPUState *env)
|
466 | 574bbf7b | bellard | { |
467 | 574bbf7b | bellard | APICState *s = env->apic_state; |
468 | 574bbf7b | bellard | int intno;
|
469 | 574bbf7b | bellard | |
470 | 574bbf7b | bellard | /* if the APIC is installed or enabled, we let the 8259 handle the
|
471 | 574bbf7b | bellard | IRQs */
|
472 | 574bbf7b | bellard | if (!s)
|
473 | 574bbf7b | bellard | return -1; |
474 | 574bbf7b | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
475 | 574bbf7b | bellard | return -1; |
476 | 3b46e624 | ths | |
477 | 574bbf7b | bellard | /* XXX: spurious IRQ handling */
|
478 | 574bbf7b | bellard | intno = get_highest_priority_int(s->irr); |
479 | 574bbf7b | bellard | if (intno < 0) |
480 | 574bbf7b | bellard | return -1; |
481 | d592d303 | bellard | if (s->tpr && intno <= s->tpr)
|
482 | d592d303 | bellard | return s->spurious_vec & 0xff; |
483 | b4511723 | bellard | reset_bit(s->irr, intno); |
484 | 574bbf7b | bellard | set_bit(s->isr, intno); |
485 | 574bbf7b | bellard | apic_update_irq(s); |
486 | 574bbf7b | bellard | return intno;
|
487 | 574bbf7b | bellard | } |
488 | 574bbf7b | bellard | |
489 | 0e21e12b | ths | int apic_accept_pic_intr(CPUState *env)
|
490 | 0e21e12b | ths | { |
491 | 0e21e12b | ths | APICState *s = env->apic_state; |
492 | 0e21e12b | ths | uint32_t lvt0; |
493 | 0e21e12b | ths | |
494 | 0e21e12b | ths | if (!s)
|
495 | 0e21e12b | ths | return -1; |
496 | 0e21e12b | ths | |
497 | 0e21e12b | ths | lvt0 = s->lvt[APIC_LVT_LINT0]; |
498 | 0e21e12b | ths | |
499 | 0e21e12b | ths | if (s->id == 0 && |
500 | 0e21e12b | ths | ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
|
501 | 0e21e12b | ths | ((lvt0 & APIC_LVT_MASKED) == 0 &&
|
502 | 0e21e12b | ths | ((lvt0 >> 8) & 0x7) == APIC_DM_EXTINT))) |
503 | 0e21e12b | ths | return 1; |
504 | 0e21e12b | ths | |
505 | 0e21e12b | ths | return 0; |
506 | 0e21e12b | ths | } |
507 | 0e21e12b | ths | |
508 | 574bbf7b | bellard | static uint32_t apic_get_current_count(APICState *s)
|
509 | 574bbf7b | bellard | { |
510 | 574bbf7b | bellard | int64_t d; |
511 | 574bbf7b | bellard | uint32_t val; |
512 | 5fafdf24 | ths | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
513 | 574bbf7b | bellard | s->count_shift; |
514 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
515 | 574bbf7b | bellard | /* periodic */
|
516 | d592d303 | bellard | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
517 | 574bbf7b | bellard | } else {
|
518 | 574bbf7b | bellard | if (d >= s->initial_count)
|
519 | 574bbf7b | bellard | val = 0;
|
520 | 574bbf7b | bellard | else
|
521 | 574bbf7b | bellard | val = s->initial_count - d; |
522 | 574bbf7b | bellard | } |
523 | 574bbf7b | bellard | return val;
|
524 | 574bbf7b | bellard | } |
525 | 574bbf7b | bellard | |
526 | 574bbf7b | bellard | static void apic_timer_update(APICState *s, int64_t current_time) |
527 | 574bbf7b | bellard | { |
528 | 574bbf7b | bellard | int64_t next_time, d; |
529 | 3b46e624 | ths | |
530 | 574bbf7b | bellard | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
531 | 5fafdf24 | ths | d = (current_time - s->initial_count_load_time) >> |
532 | 574bbf7b | bellard | s->count_shift; |
533 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
534 | d592d303 | bellard | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
535 | 574bbf7b | bellard | } else {
|
536 | 574bbf7b | bellard | if (d >= s->initial_count)
|
537 | 574bbf7b | bellard | goto no_timer;
|
538 | d592d303 | bellard | d = (uint64_t)s->initial_count + 1;
|
539 | 574bbf7b | bellard | } |
540 | 574bbf7b | bellard | next_time = s->initial_count_load_time + (d << s->count_shift); |
541 | 574bbf7b | bellard | qemu_mod_timer(s->timer, next_time); |
542 | 574bbf7b | bellard | s->next_time = next_time; |
543 | 574bbf7b | bellard | } else {
|
544 | 574bbf7b | bellard | no_timer:
|
545 | 574bbf7b | bellard | qemu_del_timer(s->timer); |
546 | 574bbf7b | bellard | } |
547 | 574bbf7b | bellard | } |
548 | 574bbf7b | bellard | |
549 | 574bbf7b | bellard | static void apic_timer(void *opaque) |
550 | 574bbf7b | bellard | { |
551 | 574bbf7b | bellard | APICState *s = opaque; |
552 | 574bbf7b | bellard | |
553 | 574bbf7b | bellard | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
554 | 574bbf7b | bellard | apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
|
555 | 574bbf7b | bellard | } |
556 | 574bbf7b | bellard | apic_timer_update(s, s->next_time); |
557 | 574bbf7b | bellard | } |
558 | 574bbf7b | bellard | |
559 | 574bbf7b | bellard | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
560 | 574bbf7b | bellard | { |
561 | 574bbf7b | bellard | return 0; |
562 | 574bbf7b | bellard | } |
563 | 574bbf7b | bellard | |
564 | 574bbf7b | bellard | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
565 | 574bbf7b | bellard | { |
566 | 574bbf7b | bellard | return 0; |
567 | 574bbf7b | bellard | } |
568 | 574bbf7b | bellard | |
569 | 574bbf7b | bellard | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
570 | 574bbf7b | bellard | { |
571 | 574bbf7b | bellard | } |
572 | 574bbf7b | bellard | |
573 | 574bbf7b | bellard | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
574 | 574bbf7b | bellard | { |
575 | 574bbf7b | bellard | } |
576 | 574bbf7b | bellard | |
577 | 574bbf7b | bellard | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
578 | 574bbf7b | bellard | { |
579 | 574bbf7b | bellard | CPUState *env; |
580 | 574bbf7b | bellard | APICState *s; |
581 | 574bbf7b | bellard | uint32_t val; |
582 | 574bbf7b | bellard | int index;
|
583 | 574bbf7b | bellard | |
584 | 574bbf7b | bellard | env = cpu_single_env; |
585 | 574bbf7b | bellard | if (!env)
|
586 | 574bbf7b | bellard | return 0; |
587 | 574bbf7b | bellard | s = env->apic_state; |
588 | 574bbf7b | bellard | |
589 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
590 | 574bbf7b | bellard | switch(index) {
|
591 | 574bbf7b | bellard | case 0x02: /* id */ |
592 | 574bbf7b | bellard | val = s->id << 24;
|
593 | 574bbf7b | bellard | break;
|
594 | 574bbf7b | bellard | case 0x03: /* version */ |
595 | 574bbf7b | bellard | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
596 | 574bbf7b | bellard | break;
|
597 | 574bbf7b | bellard | case 0x08: |
598 | 574bbf7b | bellard | val = s->tpr; |
599 | 574bbf7b | bellard | break;
|
600 | d592d303 | bellard | case 0x09: |
601 | d592d303 | bellard | val = apic_get_arb_pri(s); |
602 | d592d303 | bellard | break;
|
603 | 574bbf7b | bellard | case 0x0a: |
604 | 574bbf7b | bellard | /* ppr */
|
605 | 574bbf7b | bellard | val = apic_get_ppr(s); |
606 | 574bbf7b | bellard | break;
|
607 | d592d303 | bellard | case 0x0d: |
608 | d592d303 | bellard | val = s->log_dest << 24;
|
609 | d592d303 | bellard | break;
|
610 | d592d303 | bellard | case 0x0e: |
611 | d592d303 | bellard | val = s->dest_mode << 28;
|
612 | d592d303 | bellard | break;
|
613 | 574bbf7b | bellard | case 0x0f: |
614 | 574bbf7b | bellard | val = s->spurious_vec; |
615 | 574bbf7b | bellard | break;
|
616 | 574bbf7b | bellard | case 0x10 ... 0x17: |
617 | 574bbf7b | bellard | val = s->isr[index & 7];
|
618 | 574bbf7b | bellard | break;
|
619 | 574bbf7b | bellard | case 0x18 ... 0x1f: |
620 | 574bbf7b | bellard | val = s->tmr[index & 7];
|
621 | 574bbf7b | bellard | break;
|
622 | 574bbf7b | bellard | case 0x20 ... 0x27: |
623 | 574bbf7b | bellard | val = s->irr[index & 7];
|
624 | 574bbf7b | bellard | break;
|
625 | 574bbf7b | bellard | case 0x28: |
626 | 574bbf7b | bellard | val = s->esr; |
627 | 574bbf7b | bellard | break;
|
628 | 574bbf7b | bellard | case 0x30: |
629 | 574bbf7b | bellard | case 0x31: |
630 | 574bbf7b | bellard | val = s->icr[index & 1];
|
631 | 574bbf7b | bellard | break;
|
632 | e0fd8781 | bellard | case 0x32 ... 0x37: |
633 | e0fd8781 | bellard | val = s->lvt[index - 0x32];
|
634 | e0fd8781 | bellard | break;
|
635 | 574bbf7b | bellard | case 0x38: |
636 | 574bbf7b | bellard | val = s->initial_count; |
637 | 574bbf7b | bellard | break;
|
638 | 574bbf7b | bellard | case 0x39: |
639 | 574bbf7b | bellard | val = apic_get_current_count(s); |
640 | 574bbf7b | bellard | break;
|
641 | 574bbf7b | bellard | case 0x3e: |
642 | 574bbf7b | bellard | val = s->divide_conf; |
643 | 574bbf7b | bellard | break;
|
644 | 574bbf7b | bellard | default:
|
645 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
646 | 574bbf7b | bellard | val = 0;
|
647 | 574bbf7b | bellard | break;
|
648 | 574bbf7b | bellard | } |
649 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
650 | 574bbf7b | bellard | printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
|
651 | 574bbf7b | bellard | #endif
|
652 | 574bbf7b | bellard | return val;
|
653 | 574bbf7b | bellard | } |
654 | 574bbf7b | bellard | |
655 | 574bbf7b | bellard | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
656 | 574bbf7b | bellard | { |
657 | 574bbf7b | bellard | CPUState *env; |
658 | 574bbf7b | bellard | APICState *s; |
659 | 574bbf7b | bellard | int index;
|
660 | 574bbf7b | bellard | |
661 | 574bbf7b | bellard | env = cpu_single_env; |
662 | 574bbf7b | bellard | if (!env)
|
663 | 574bbf7b | bellard | return;
|
664 | 574bbf7b | bellard | s = env->apic_state; |
665 | 574bbf7b | bellard | |
666 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
667 | 574bbf7b | bellard | printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
668 | 574bbf7b | bellard | #endif
|
669 | 574bbf7b | bellard | |
670 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
671 | 574bbf7b | bellard | switch(index) {
|
672 | 574bbf7b | bellard | case 0x02: |
673 | 574bbf7b | bellard | s->id = (val >> 24);
|
674 | 574bbf7b | bellard | break;
|
675 | e0fd8781 | bellard | case 0x03: |
676 | e0fd8781 | bellard | break;
|
677 | 574bbf7b | bellard | case 0x08: |
678 | 574bbf7b | bellard | s->tpr = val; |
679 | d592d303 | bellard | apic_update_irq(s); |
680 | 574bbf7b | bellard | break;
|
681 | e0fd8781 | bellard | case 0x09: |
682 | e0fd8781 | bellard | case 0x0a: |
683 | e0fd8781 | bellard | break;
|
684 | 574bbf7b | bellard | case 0x0b: /* EOI */ |
685 | 574bbf7b | bellard | apic_eoi(s); |
686 | 574bbf7b | bellard | break;
|
687 | d592d303 | bellard | case 0x0d: |
688 | d592d303 | bellard | s->log_dest = val >> 24;
|
689 | d592d303 | bellard | break;
|
690 | d592d303 | bellard | case 0x0e: |
691 | d592d303 | bellard | s->dest_mode = val >> 28;
|
692 | d592d303 | bellard | break;
|
693 | 574bbf7b | bellard | case 0x0f: |
694 | 574bbf7b | bellard | s->spurious_vec = val & 0x1ff;
|
695 | d592d303 | bellard | apic_update_irq(s); |
696 | 574bbf7b | bellard | break;
|
697 | e0fd8781 | bellard | case 0x10 ... 0x17: |
698 | e0fd8781 | bellard | case 0x18 ... 0x1f: |
699 | e0fd8781 | bellard | case 0x20 ... 0x27: |
700 | e0fd8781 | bellard | case 0x28: |
701 | e0fd8781 | bellard | break;
|
702 | 574bbf7b | bellard | case 0x30: |
703 | d592d303 | bellard | s->icr[0] = val;
|
704 | d592d303 | bellard | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
705 | d592d303 | bellard | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
706 | d592d303 | bellard | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
707 | d592d303 | bellard | break;
|
708 | 574bbf7b | bellard | case 0x31: |
709 | d592d303 | bellard | s->icr[1] = val;
|
710 | 574bbf7b | bellard | break;
|
711 | 574bbf7b | bellard | case 0x32 ... 0x37: |
712 | 574bbf7b | bellard | { |
713 | 574bbf7b | bellard | int n = index - 0x32; |
714 | 574bbf7b | bellard | s->lvt[n] = val; |
715 | 574bbf7b | bellard | if (n == APIC_LVT_TIMER)
|
716 | 574bbf7b | bellard | apic_timer_update(s, qemu_get_clock(vm_clock)); |
717 | 574bbf7b | bellard | } |
718 | 574bbf7b | bellard | break;
|
719 | 574bbf7b | bellard | case 0x38: |
720 | 574bbf7b | bellard | s->initial_count = val; |
721 | 574bbf7b | bellard | s->initial_count_load_time = qemu_get_clock(vm_clock); |
722 | 574bbf7b | bellard | apic_timer_update(s, s->initial_count_load_time); |
723 | 574bbf7b | bellard | break;
|
724 | e0fd8781 | bellard | case 0x39: |
725 | e0fd8781 | bellard | break;
|
726 | 574bbf7b | bellard | case 0x3e: |
727 | 574bbf7b | bellard | { |
728 | 574bbf7b | bellard | int v;
|
729 | 574bbf7b | bellard | s->divide_conf = val & 0xb;
|
730 | 574bbf7b | bellard | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
731 | 574bbf7b | bellard | s->count_shift = (v + 1) & 7; |
732 | 574bbf7b | bellard | } |
733 | 574bbf7b | bellard | break;
|
734 | 574bbf7b | bellard | default:
|
735 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
736 | 574bbf7b | bellard | break;
|
737 | 574bbf7b | bellard | } |
738 | 574bbf7b | bellard | } |
739 | 574bbf7b | bellard | |
740 | d592d303 | bellard | static void apic_save(QEMUFile *f, void *opaque) |
741 | d592d303 | bellard | { |
742 | d592d303 | bellard | APICState *s = opaque; |
743 | d592d303 | bellard | int i;
|
744 | d592d303 | bellard | |
745 | d592d303 | bellard | qemu_put_be32s(f, &s->apicbase); |
746 | d592d303 | bellard | qemu_put_8s(f, &s->id); |
747 | d592d303 | bellard | qemu_put_8s(f, &s->arb_id); |
748 | d592d303 | bellard | qemu_put_8s(f, &s->tpr); |
749 | d592d303 | bellard | qemu_put_be32s(f, &s->spurious_vec); |
750 | d592d303 | bellard | qemu_put_8s(f, &s->log_dest); |
751 | d592d303 | bellard | qemu_put_8s(f, &s->dest_mode); |
752 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
753 | d592d303 | bellard | qemu_put_be32s(f, &s->isr[i]); |
754 | d592d303 | bellard | qemu_put_be32s(f, &s->tmr[i]); |
755 | d592d303 | bellard | qemu_put_be32s(f, &s->irr[i]); |
756 | d592d303 | bellard | } |
757 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
758 | d592d303 | bellard | qemu_put_be32s(f, &s->lvt[i]); |
759 | d592d303 | bellard | } |
760 | d592d303 | bellard | qemu_put_be32s(f, &s->esr); |
761 | d592d303 | bellard | qemu_put_be32s(f, &s->icr[0]);
|
762 | d592d303 | bellard | qemu_put_be32s(f, &s->icr[1]);
|
763 | d592d303 | bellard | qemu_put_be32s(f, &s->divide_conf); |
764 | bee8d684 | ths | qemu_put_be32(f, s->count_shift); |
765 | d592d303 | bellard | qemu_put_be32s(f, &s->initial_count); |
766 | bee8d684 | ths | qemu_put_be64(f, s->initial_count_load_time); |
767 | bee8d684 | ths | qemu_put_be64(f, s->next_time); |
768 | e6cf6a8c | bellard | |
769 | e6cf6a8c | bellard | qemu_put_timer(f, s->timer); |
770 | d592d303 | bellard | } |
771 | d592d303 | bellard | |
772 | d592d303 | bellard | static int apic_load(QEMUFile *f, void *opaque, int version_id) |
773 | d592d303 | bellard | { |
774 | d592d303 | bellard | APICState *s = opaque; |
775 | d592d303 | bellard | int i;
|
776 | d592d303 | bellard | |
777 | e6cf6a8c | bellard | if (version_id > 2) |
778 | d592d303 | bellard | return -EINVAL;
|
779 | d592d303 | bellard | |
780 | d592d303 | bellard | /* XXX: what if the base changes? (registered memory regions) */
|
781 | d592d303 | bellard | qemu_get_be32s(f, &s->apicbase); |
782 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
783 | d592d303 | bellard | qemu_get_8s(f, &s->arb_id); |
784 | d592d303 | bellard | qemu_get_8s(f, &s->tpr); |
785 | d592d303 | bellard | qemu_get_be32s(f, &s->spurious_vec); |
786 | d592d303 | bellard | qemu_get_8s(f, &s->log_dest); |
787 | d592d303 | bellard | qemu_get_8s(f, &s->dest_mode); |
788 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
789 | d592d303 | bellard | qemu_get_be32s(f, &s->isr[i]); |
790 | d592d303 | bellard | qemu_get_be32s(f, &s->tmr[i]); |
791 | d592d303 | bellard | qemu_get_be32s(f, &s->irr[i]); |
792 | d592d303 | bellard | } |
793 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
794 | d592d303 | bellard | qemu_get_be32s(f, &s->lvt[i]); |
795 | d592d303 | bellard | } |
796 | d592d303 | bellard | qemu_get_be32s(f, &s->esr); |
797 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[0]);
|
798 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[1]);
|
799 | d592d303 | bellard | qemu_get_be32s(f, &s->divide_conf); |
800 | bee8d684 | ths | s->count_shift=qemu_get_be32(f); |
801 | d592d303 | bellard | qemu_get_be32s(f, &s->initial_count); |
802 | bee8d684 | ths | s->initial_count_load_time=qemu_get_be64(f); |
803 | bee8d684 | ths | s->next_time=qemu_get_be64(f); |
804 | e6cf6a8c | bellard | |
805 | e6cf6a8c | bellard | if (version_id >= 2) |
806 | e6cf6a8c | bellard | qemu_get_timer(f, s->timer); |
807 | d592d303 | bellard | return 0; |
808 | d592d303 | bellard | } |
809 | 574bbf7b | bellard | |
810 | d592d303 | bellard | static void apic_reset(void *opaque) |
811 | d592d303 | bellard | { |
812 | d592d303 | bellard | APICState *s = opaque; |
813 | d592d303 | bellard | apic_init_ipi(s); |
814 | 0e21e12b | ths | |
815 | 0e21e12b | ths | /*
|
816 | 0e21e12b | ths | * LINT0 delivery mode is set to ExtInt at initialization time
|
817 | 0e21e12b | ths | * typically by BIOS, so PIC interrupt can be delivered to the
|
818 | 0e21e12b | ths | * processor when local APIC is enabled.
|
819 | 0e21e12b | ths | */
|
820 | 0e21e12b | ths | s->lvt[APIC_LVT_LINT0] = 0x700;
|
821 | d592d303 | bellard | } |
822 | 574bbf7b | bellard | |
823 | 574bbf7b | bellard | static CPUReadMemoryFunc *apic_mem_read[3] = { |
824 | 574bbf7b | bellard | apic_mem_readb, |
825 | 574bbf7b | bellard | apic_mem_readw, |
826 | 574bbf7b | bellard | apic_mem_readl, |
827 | 574bbf7b | bellard | }; |
828 | 574bbf7b | bellard | |
829 | 574bbf7b | bellard | static CPUWriteMemoryFunc *apic_mem_write[3] = { |
830 | 574bbf7b | bellard | apic_mem_writeb, |
831 | 574bbf7b | bellard | apic_mem_writew, |
832 | 574bbf7b | bellard | apic_mem_writel, |
833 | 574bbf7b | bellard | }; |
834 | 574bbf7b | bellard | |
835 | 574bbf7b | bellard | int apic_init(CPUState *env)
|
836 | 574bbf7b | bellard | { |
837 | 574bbf7b | bellard | APICState *s; |
838 | 574bbf7b | bellard | |
839 | d3e9db93 | bellard | if (last_apic_id >= MAX_APICS)
|
840 | d3e9db93 | bellard | return -1; |
841 | d592d303 | bellard | s = qemu_mallocz(sizeof(APICState));
|
842 | 574bbf7b | bellard | if (!s)
|
843 | 574bbf7b | bellard | return -1; |
844 | 574bbf7b | bellard | env->apic_state = s; |
845 | d592d303 | bellard | apic_init_ipi(s); |
846 | d592d303 | bellard | s->id = last_apic_id++; |
847 | eae7629b | ths | env->cpuid_apic_id = s->id; |
848 | 574bbf7b | bellard | s->cpu_env = env; |
849 | 5fafdf24 | ths | s->apicbase = 0xfee00000 |
|
850 | d592d303 | bellard | (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
|
851 | 574bbf7b | bellard | |
852 | 0e21e12b | ths | /*
|
853 | 0e21e12b | ths | * LINT0 delivery mode is set to ExtInt at initialization time
|
854 | 0e21e12b | ths | * typically by BIOS, so PIC interrupt can be delivered to the
|
855 | 0e21e12b | ths | * processor when local APIC is enabled.
|
856 | 0e21e12b | ths | */
|
857 | 0e21e12b | ths | s->lvt[APIC_LVT_LINT0] = 0x700;
|
858 | 0e21e12b | ths | |
859 | d592d303 | bellard | /* XXX: mapping more APICs at the same memory location */
|
860 | 574bbf7b | bellard | if (apic_io_memory == 0) { |
861 | 574bbf7b | bellard | /* NOTE: the APIC is directly connected to the CPU - it is not
|
862 | 574bbf7b | bellard | on the global memory bus. */
|
863 | 5fafdf24 | ths | apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
|
864 | 574bbf7b | bellard | apic_mem_write, NULL);
|
865 | d592d303 | bellard | cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, |
866 | d592d303 | bellard | apic_io_memory); |
867 | 574bbf7b | bellard | } |
868 | 574bbf7b | bellard | s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
869 | d592d303 | bellard | |
870 | be0164f2 | ths | register_savevm("apic", s->id, 2, apic_save, apic_load, s); |
871 | d592d303 | bellard | qemu_register_reset(apic_reset, s); |
872 | 3b46e624 | ths | |
873 | d3e9db93 | bellard | local_apics[s->id] = s; |
874 | d592d303 | bellard | return 0; |
875 | d592d303 | bellard | } |
876 | d592d303 | bellard | |
877 | d592d303 | bellard | static void ioapic_service(IOAPICState *s) |
878 | d592d303 | bellard | { |
879 | b1fc0348 | bellard | uint8_t i; |
880 | b1fc0348 | bellard | uint8_t trig_mode; |
881 | d592d303 | bellard | uint8_t vector; |
882 | b1fc0348 | bellard | uint8_t delivery_mode; |
883 | d592d303 | bellard | uint32_t mask; |
884 | d592d303 | bellard | uint64_t entry; |
885 | d592d303 | bellard | uint8_t dest; |
886 | d592d303 | bellard | uint8_t dest_mode; |
887 | b1fc0348 | bellard | uint8_t polarity; |
888 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
889 | d592d303 | bellard | |
890 | b1fc0348 | bellard | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
891 | b1fc0348 | bellard | mask = 1 << i;
|
892 | d592d303 | bellard | if (s->irr & mask) {
|
893 | b1fc0348 | bellard | entry = s->ioredtbl[i]; |
894 | d592d303 | bellard | if (!(entry & APIC_LVT_MASKED)) {
|
895 | b1fc0348 | bellard | trig_mode = ((entry >> 15) & 1); |
896 | d592d303 | bellard | dest = entry >> 56;
|
897 | d592d303 | bellard | dest_mode = (entry >> 11) & 1; |
898 | b1fc0348 | bellard | delivery_mode = (entry >> 8) & 7; |
899 | b1fc0348 | bellard | polarity = (entry >> 13) & 1; |
900 | b1fc0348 | bellard | if (trig_mode == APIC_TRIGGER_EDGE)
|
901 | b1fc0348 | bellard | s->irr &= ~mask; |
902 | b1fc0348 | bellard | if (delivery_mode == APIC_DM_EXTINT)
|
903 | b1fc0348 | bellard | vector = pic_read_irq(isa_pic); |
904 | b1fc0348 | bellard | else
|
905 | b1fc0348 | bellard | vector = entry & 0xff;
|
906 | 3b46e624 | ths | |
907 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
908 | 5fafdf24 | ths | apic_bus_deliver(deliver_bitmask, delivery_mode, |
909 | d3e9db93 | bellard | vector, polarity, trig_mode); |
910 | d592d303 | bellard | } |
911 | d592d303 | bellard | } |
912 | d592d303 | bellard | } |
913 | d592d303 | bellard | } |
914 | d592d303 | bellard | |
915 | d592d303 | bellard | void ioapic_set_irq(void *opaque, int vector, int level) |
916 | d592d303 | bellard | { |
917 | d592d303 | bellard | IOAPICState *s = opaque; |
918 | d592d303 | bellard | |
919 | d592d303 | bellard | if (vector >= 0 && vector < IOAPIC_NUM_PINS) { |
920 | d592d303 | bellard | uint32_t mask = 1 << vector;
|
921 | d592d303 | bellard | uint64_t entry = s->ioredtbl[vector]; |
922 | d592d303 | bellard | |
923 | d592d303 | bellard | if ((entry >> 15) & 1) { |
924 | d592d303 | bellard | /* level triggered */
|
925 | d592d303 | bellard | if (level) {
|
926 | d592d303 | bellard | s->irr |= mask; |
927 | d592d303 | bellard | ioapic_service(s); |
928 | d592d303 | bellard | } else {
|
929 | d592d303 | bellard | s->irr &= ~mask; |
930 | d592d303 | bellard | } |
931 | d592d303 | bellard | } else {
|
932 | d592d303 | bellard | /* edge triggered */
|
933 | d592d303 | bellard | if (level) {
|
934 | d592d303 | bellard | s->irr |= mask; |
935 | d592d303 | bellard | ioapic_service(s); |
936 | d592d303 | bellard | } |
937 | d592d303 | bellard | } |
938 | d592d303 | bellard | } |
939 | d592d303 | bellard | } |
940 | d592d303 | bellard | |
941 | d592d303 | bellard | static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) |
942 | d592d303 | bellard | { |
943 | d592d303 | bellard | IOAPICState *s = opaque; |
944 | d592d303 | bellard | int index;
|
945 | d592d303 | bellard | uint32_t val = 0;
|
946 | d592d303 | bellard | |
947 | d592d303 | bellard | addr &= 0xff;
|
948 | d592d303 | bellard | if (addr == 0x00) { |
949 | d592d303 | bellard | val = s->ioregsel; |
950 | d592d303 | bellard | } else if (addr == 0x10) { |
951 | d592d303 | bellard | switch (s->ioregsel) {
|
952 | d592d303 | bellard | case 0x00: |
953 | d592d303 | bellard | val = s->id << 24;
|
954 | d592d303 | bellard | break;
|
955 | d592d303 | bellard | case 0x01: |
956 | d592d303 | bellard | val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */ |
957 | d592d303 | bellard | break;
|
958 | d592d303 | bellard | case 0x02: |
959 | d592d303 | bellard | val = 0;
|
960 | d592d303 | bellard | break;
|
961 | d592d303 | bellard | default:
|
962 | d592d303 | bellard | index = (s->ioregsel - 0x10) >> 1; |
963 | d592d303 | bellard | if (index >= 0 && index < IOAPIC_NUM_PINS) { |
964 | d592d303 | bellard | if (s->ioregsel & 1) |
965 | d592d303 | bellard | val = s->ioredtbl[index] >> 32;
|
966 | d592d303 | bellard | else
|
967 | d592d303 | bellard | val = s->ioredtbl[index] & 0xffffffff;
|
968 | d592d303 | bellard | } |
969 | d592d303 | bellard | } |
970 | d592d303 | bellard | #ifdef DEBUG_IOAPIC
|
971 | d592d303 | bellard | printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
|
972 | d592d303 | bellard | #endif
|
973 | d592d303 | bellard | } |
974 | d592d303 | bellard | return val;
|
975 | d592d303 | bellard | } |
976 | d592d303 | bellard | |
977 | d592d303 | bellard | static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
978 | d592d303 | bellard | { |
979 | d592d303 | bellard | IOAPICState *s = opaque; |
980 | d592d303 | bellard | int index;
|
981 | d592d303 | bellard | |
982 | d592d303 | bellard | addr &= 0xff;
|
983 | d592d303 | bellard | if (addr == 0x00) { |
984 | d592d303 | bellard | s->ioregsel = val; |
985 | d592d303 | bellard | return;
|
986 | d592d303 | bellard | } else if (addr == 0x10) { |
987 | d592d303 | bellard | #ifdef DEBUG_IOAPIC
|
988 | d592d303 | bellard | printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
|
989 | d592d303 | bellard | #endif
|
990 | d592d303 | bellard | switch (s->ioregsel) {
|
991 | d592d303 | bellard | case 0x00: |
992 | d592d303 | bellard | s->id = (val >> 24) & 0xff; |
993 | d592d303 | bellard | return;
|
994 | d592d303 | bellard | case 0x01: |
995 | d592d303 | bellard | case 0x02: |
996 | d592d303 | bellard | return;
|
997 | d592d303 | bellard | default:
|
998 | d592d303 | bellard | index = (s->ioregsel - 0x10) >> 1; |
999 | d592d303 | bellard | if (index >= 0 && index < IOAPIC_NUM_PINS) { |
1000 | d592d303 | bellard | if (s->ioregsel & 1) { |
1001 | d592d303 | bellard | s->ioredtbl[index] &= 0xffffffff;
|
1002 | d592d303 | bellard | s->ioredtbl[index] |= (uint64_t)val << 32;
|
1003 | d592d303 | bellard | } else {
|
1004 | d592d303 | bellard | s->ioredtbl[index] &= ~0xffffffffULL;
|
1005 | d592d303 | bellard | s->ioredtbl[index] |= val; |
1006 | d592d303 | bellard | } |
1007 | d592d303 | bellard | ioapic_service(s); |
1008 | d592d303 | bellard | } |
1009 | d592d303 | bellard | } |
1010 | d592d303 | bellard | } |
1011 | d592d303 | bellard | } |
1012 | d592d303 | bellard | |
1013 | d592d303 | bellard | static void ioapic_save(QEMUFile *f, void *opaque) |
1014 | d592d303 | bellard | { |
1015 | d592d303 | bellard | IOAPICState *s = opaque; |
1016 | d592d303 | bellard | int i;
|
1017 | d592d303 | bellard | |
1018 | d592d303 | bellard | qemu_put_8s(f, &s->id); |
1019 | d592d303 | bellard | qemu_put_8s(f, &s->ioregsel); |
1020 | d592d303 | bellard | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
1021 | d592d303 | bellard | qemu_put_be64s(f, &s->ioredtbl[i]); |
1022 | d592d303 | bellard | } |
1023 | d592d303 | bellard | } |
1024 | d592d303 | bellard | |
1025 | d592d303 | bellard | static int ioapic_load(QEMUFile *f, void *opaque, int version_id) |
1026 | d592d303 | bellard | { |
1027 | d592d303 | bellard | IOAPICState *s = opaque; |
1028 | d592d303 | bellard | int i;
|
1029 | d592d303 | bellard | |
1030 | d592d303 | bellard | if (version_id != 1) |
1031 | d592d303 | bellard | return -EINVAL;
|
1032 | d592d303 | bellard | |
1033 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
1034 | d592d303 | bellard | qemu_get_8s(f, &s->ioregsel); |
1035 | d592d303 | bellard | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
1036 | d592d303 | bellard | qemu_get_be64s(f, &s->ioredtbl[i]); |
1037 | d592d303 | bellard | } |
1038 | 574bbf7b | bellard | return 0; |
1039 | 574bbf7b | bellard | } |
1040 | d592d303 | bellard | |
1041 | d592d303 | bellard | static void ioapic_reset(void *opaque) |
1042 | d592d303 | bellard | { |
1043 | d592d303 | bellard | IOAPICState *s = opaque; |
1044 | d592d303 | bellard | int i;
|
1045 | d592d303 | bellard | |
1046 | d592d303 | bellard | memset(s, 0, sizeof(*s)); |
1047 | d592d303 | bellard | for(i = 0; i < IOAPIC_NUM_PINS; i++) |
1048 | d592d303 | bellard | s->ioredtbl[i] = 1 << 16; /* mask LVT */ |
1049 | d592d303 | bellard | } |
1050 | d592d303 | bellard | |
1051 | d592d303 | bellard | static CPUReadMemoryFunc *ioapic_mem_read[3] = { |
1052 | d592d303 | bellard | ioapic_mem_readl, |
1053 | d592d303 | bellard | ioapic_mem_readl, |
1054 | d592d303 | bellard | ioapic_mem_readl, |
1055 | d592d303 | bellard | }; |
1056 | d592d303 | bellard | |
1057 | d592d303 | bellard | static CPUWriteMemoryFunc *ioapic_mem_write[3] = { |
1058 | d592d303 | bellard | ioapic_mem_writel, |
1059 | d592d303 | bellard | ioapic_mem_writel, |
1060 | d592d303 | bellard | ioapic_mem_writel, |
1061 | d592d303 | bellard | }; |
1062 | d592d303 | bellard | |
1063 | d592d303 | bellard | IOAPICState *ioapic_init(void)
|
1064 | d592d303 | bellard | { |
1065 | d592d303 | bellard | IOAPICState *s; |
1066 | d592d303 | bellard | int io_memory;
|
1067 | d592d303 | bellard | |
1068 | b1fc0348 | bellard | s = qemu_mallocz(sizeof(IOAPICState));
|
1069 | d592d303 | bellard | if (!s)
|
1070 | d592d303 | bellard | return NULL; |
1071 | d592d303 | bellard | ioapic_reset(s); |
1072 | d592d303 | bellard | s->id = last_apic_id++; |
1073 | d592d303 | bellard | |
1074 | 5fafdf24 | ths | io_memory = cpu_register_io_memory(0, ioapic_mem_read,
|
1075 | d592d303 | bellard | ioapic_mem_write, s); |
1076 | d592d303 | bellard | cpu_register_physical_memory(0xfec00000, 0x1000, io_memory); |
1077 | d592d303 | bellard | |
1078 | d592d303 | bellard | register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s); |
1079 | d592d303 | bellard | qemu_register_reset(ioapic_reset, s); |
1080 | 3b46e624 | ths | |
1081 | d592d303 | bellard | return s;
|
1082 | d592d303 | bellard | } |