root / hw / pxa2xx_lcd.c @ 298e01b6
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/*
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* Intel XScale PXA255/270 LCDC emulation.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPLv2.
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*/
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#include "hw.h" |
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#include "console.h" |
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#include "pxa.h" |
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#include "pixel_ops.h" |
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/* FIXME: For graphic_rotate. Should probably be done in common code. */
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#include "sysemu.h" |
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typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int); |
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struct pxa2xx_lcdc_s {
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target_phys_addr_t base; |
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qemu_irq irq; |
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int irqlevel;
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int invalidated;
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DisplayState *ds; |
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drawfn *line_fn[2];
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int dest_width;
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int xres, yres;
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int pal_for;
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int transp;
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enum {
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pxa_lcdc_2bpp = 1,
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pxa_lcdc_4bpp = 2,
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pxa_lcdc_8bpp = 3,
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pxa_lcdc_16bpp = 4,
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pxa_lcdc_18bpp = 5,
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pxa_lcdc_18pbpp = 6,
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pxa_lcdc_19bpp = 7,
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pxa_lcdc_19pbpp = 8,
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pxa_lcdc_24bpp = 9,
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pxa_lcdc_25bpp = 10,
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} bpp; |
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|
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uint32_t control[6];
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uint32_t status[2];
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uint32_t ovl1c[2];
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uint32_t ovl2c[2];
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uint32_t ccr; |
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uint32_t cmdcr; |
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uint32_t trgbr; |
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uint32_t tcr; |
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uint32_t liidr; |
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uint8_t bscntr; |
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struct {
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target_phys_addr_t branch; |
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int up;
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uint8_t palette[1024];
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uint8_t pbuffer[1024];
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void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb, |
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int *miny, int *maxy); |
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|
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target_phys_addr_t descriptor; |
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target_phys_addr_t source; |
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uint32_t id; |
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uint32_t command; |
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} dma_ch[7];
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qemu_irq vsync_cb; |
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int orientation;
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}; |
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struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
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uint32_t fdaddr; |
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uint32_t fsaddr; |
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uint32_t fidr; |
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uint32_t ldcmd; |
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}; |
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|
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#define LCCR0 0x000 /* LCD Controller Control register 0 */ |
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#define LCCR1 0x004 /* LCD Controller Control register 1 */ |
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#define LCCR2 0x008 /* LCD Controller Control register 2 */ |
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#define LCCR3 0x00c /* LCD Controller Control register 3 */ |
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#define LCCR4 0x010 /* LCD Controller Control register 4 */ |
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#define LCCR5 0x014 /* LCD Controller Control register 5 */ |
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|
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#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */ |
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#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */ |
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#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */ |
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#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */ |
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#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */ |
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#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ |
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#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */ |
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|
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#define LCSR1 0x034 /* LCD Controller Status register 1 */ |
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#define LCSR0 0x038 /* LCD Controller Status register 0 */ |
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#define LIIDR 0x03c /* LCD Controller Interrupt ID register */ |
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|
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#define TRGBR 0x040 /* TMED RGB Seed register */ |
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#define TCR 0x044 /* TMED Control register */ |
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|
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#define OVL1C1 0x050 /* Overlay 1 Control register 1 */ |
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#define OVL1C2 0x060 /* Overlay 1 Control register 2 */ |
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#define OVL2C1 0x070 /* Overlay 2 Control register 1 */ |
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#define OVL2C2 0x080 /* Overlay 2 Control register 2 */ |
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#define CCR 0x090 /* Cursor Control register */ |
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|
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#define CMDCR 0x100 /* Command Control register */ |
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#define PRSR 0x104 /* Panel Read Status register */ |
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|
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#define PXA_LCDDMA_CHANS 7 |
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#define DMA_FDADR 0x00 /* Frame Descriptor Address register */ |
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#define DMA_FSADR 0x04 /* Frame Source Address register */ |
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#define DMA_FIDR 0x08 /* Frame ID register */ |
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#define DMA_LDCMD 0x0c /* Command register */ |
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|
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/* LCD Buffer Strength Control register */
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#define BSCNTR 0x04000054 |
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|
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/* Bitfield masks */
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#define LCCR0_ENB (1 << 0) |
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#define LCCR0_CMS (1 << 1) |
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#define LCCR0_SDS (1 << 2) |
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#define LCCR0_LDM (1 << 3) |
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#define LCCR0_SOFM0 (1 << 4) |
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#define LCCR0_IUM (1 << 5) |
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#define LCCR0_EOFM0 (1 << 6) |
128 |
#define LCCR0_PAS (1 << 7) |
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#define LCCR0_DPD (1 << 9) |
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#define LCCR0_DIS (1 << 10) |
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#define LCCR0_QDM (1 << 11) |
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#define LCCR0_PDD (0xff << 12) |
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#define LCCR0_BSM0 (1 << 20) |
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#define LCCR0_OUM (1 << 21) |
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#define LCCR0_LCDT (1 << 22) |
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#define LCCR0_RDSTM (1 << 23) |
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#define LCCR0_CMDIM (1 << 24) |
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#define LCCR0_OUC (1 << 25) |
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#define LCCR0_LDDALT (1 << 26) |
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#define LCCR1_PPL(x) ((x) & 0x3ff) |
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#define LCCR2_LPP(x) ((x) & 0x3ff) |
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#define LCCR3_API (15 << 16) |
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#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8)) |
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#define LCCR3_PDFOR(x) (((x) >> 30) & 3) |
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#define LCCR4_K1(x) (((x) >> 0) & 7) |
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#define LCCR4_K2(x) (((x) >> 3) & 7) |
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#define LCCR4_K3(x) (((x) >> 6) & 7) |
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#define LCCR4_PALFOR(x) (((x) >> 15) & 3) |
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#define LCCR5_SOFM(ch) (1 << (ch - 1)) |
150 |
#define LCCR5_EOFM(ch) (1 << (ch + 7)) |
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#define LCCR5_BSM(ch) (1 << (ch + 15)) |
152 |
#define LCCR5_IUM(ch) (1 << (ch + 23)) |
153 |
#define OVLC1_EN (1 << 31) |
154 |
#define CCR_CEN (1 << 31) |
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#define FBR_BRA (1 << 0) |
156 |
#define FBR_BINT (1 << 1) |
157 |
#define FBR_SRCADDR (0xfffffff << 4) |
158 |
#define LCSR0_LDD (1 << 0) |
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#define LCSR0_SOF0 (1 << 1) |
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#define LCSR0_BER (1 << 2) |
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#define LCSR0_ABC (1 << 3) |
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#define LCSR0_IU0 (1 << 4) |
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#define LCSR0_IU1 (1 << 5) |
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#define LCSR0_OU (1 << 6) |
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#define LCSR0_QD (1 << 7) |
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#define LCSR0_EOF0 (1 << 8) |
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#define LCSR0_BS0 (1 << 9) |
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#define LCSR0_SINT (1 << 10) |
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#define LCSR0_RDST (1 << 11) |
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#define LCSR0_CMDINT (1 << 12) |
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#define LCSR0_BERCH(x) (((x) & 7) << 28) |
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#define LCSR1_SOF(ch) (1 << (ch - 1)) |
173 |
#define LCSR1_EOF(ch) (1 << (ch + 7)) |
174 |
#define LCSR1_BS(ch) (1 << (ch + 15)) |
175 |
#define LCSR1_IU(ch) (1 << (ch + 23)) |
176 |
#define LDCMD_LENGTH(x) ((x) & 0x001ffffc) |
177 |
#define LDCMD_EOFINT (1 << 21) |
178 |
#define LDCMD_SOFINT (1 << 22) |
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#define LDCMD_PAL (1 << 26) |
180 |
|
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/* Route internal interrupt lines to the global IC */
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static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s) |
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{ |
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int level = 0; |
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level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM); |
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level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0); |
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level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM); |
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level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1)); |
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level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM); |
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level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM); |
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level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0); |
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level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0); |
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level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM); |
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level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM); |
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level |= (s->status[1] & ~s->control[5]); |
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qemu_set_irq(s->irq, !!level); |
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s->irqlevel = level; |
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} |
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/* Set Branch Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch) |
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{ |
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int unmasked;
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if (ch == 0) { |
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s->status[0] |= LCSR0_BS0;
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unmasked = !(s->control[0] & LCCR0_BSM0);
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} else {
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s->status[1] |= LCSR1_BS(ch);
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unmasked = !(s->control[5] & LCCR5_BSM(ch));
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} |
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
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} |
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} |
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/* Set Start Of Frame Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch) |
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{ |
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int unmasked;
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if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
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return;
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if (ch == 0) { |
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s->status[0] |= LCSR0_SOF0;
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unmasked = !(s->control[0] & LCCR0_SOFM0);
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} else {
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s->status[1] |= LCSR1_SOF(ch);
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unmasked = !(s->control[5] & LCCR5_SOFM(ch));
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} |
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
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} |
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} |
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|
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/* Set End Of Frame Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch) |
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{ |
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int unmasked;
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if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
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return;
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if (ch == 0) { |
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s->status[0] |= LCSR0_EOF0;
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unmasked = !(s->control[0] & LCCR0_EOFM0);
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} else {
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s->status[1] |= LCSR1_EOF(ch);
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unmasked = !(s->control[5] & LCCR5_EOFM(ch));
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} |
258 |
|
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
264 |
} |
265 |
} |
266 |
|
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/* Set Bus Error Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch) |
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{ |
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s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
275 |
} |
276 |
|
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/* Set Read Status interrupt high and poke associated registers */
|
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static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s) |
279 |
{ |
280 |
s->status[0] |= LCSR0_RDST;
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if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM)) |
282 |
s->status[0] |= LCSR0_SINT;
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} |
284 |
|
285 |
/* Load new Frame Descriptors from DMA */
|
286 |
static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) |
287 |
{ |
288 |
struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
|
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target_phys_addr_t descptr; |
290 |
int i;
|
291 |
|
292 |
for (i = 0; i < PXA_LCDDMA_CHANS; i ++) { |
293 |
desc[i] = 0;
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294 |
s->dma_ch[i].source = 0;
|
295 |
|
296 |
if (!s->dma_ch[i].up)
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297 |
continue;
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298 |
|
299 |
if (s->dma_ch[i].branch & FBR_BRA) {
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300 |
descptr = s->dma_ch[i].branch & FBR_SRCADDR; |
301 |
if (s->dma_ch[i].branch & FBR_BINT)
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302 |
pxa2xx_dma_bs_set(s, i); |
303 |
s->dma_ch[i].branch &= ~FBR_BRA; |
304 |
} else
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305 |
descptr = s->dma_ch[i].descriptor; |
306 |
|
307 |
if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
|
308 |
sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
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309 |
continue;
|
310 |
|
311 |
descptr -= PXA2XX_SDRAM_BASE; |
312 |
desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
|
313 |
s->dma_ch[i].descriptor = desc[i]->fdaddr; |
314 |
s->dma_ch[i].source = desc[i]->fsaddr; |
315 |
s->dma_ch[i].id = desc[i]->fidr; |
316 |
s->dma_ch[i].command = desc[i]->ldcmd; |
317 |
} |
318 |
} |
319 |
|
320 |
static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) |
321 |
{ |
322 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
323 |
int ch;
|
324 |
offset -= s->base; |
325 |
|
326 |
switch (offset) {
|
327 |
case LCCR0:
|
328 |
return s->control[0]; |
329 |
case LCCR1:
|
330 |
return s->control[1]; |
331 |
case LCCR2:
|
332 |
return s->control[2]; |
333 |
case LCCR3:
|
334 |
return s->control[3]; |
335 |
case LCCR4:
|
336 |
return s->control[4]; |
337 |
case LCCR5:
|
338 |
return s->control[5]; |
339 |
|
340 |
case OVL1C1:
|
341 |
return s->ovl1c[0]; |
342 |
case OVL1C2:
|
343 |
return s->ovl1c[1]; |
344 |
case OVL2C1:
|
345 |
return s->ovl2c[0]; |
346 |
case OVL2C2:
|
347 |
return s->ovl2c[1]; |
348 |
|
349 |
case CCR:
|
350 |
return s->ccr;
|
351 |
|
352 |
case CMDCR:
|
353 |
return s->cmdcr;
|
354 |
|
355 |
case TRGBR:
|
356 |
return s->trgbr;
|
357 |
case TCR:
|
358 |
return s->tcr;
|
359 |
|
360 |
case 0x200 ... 0x1000: /* DMA per-channel registers */ |
361 |
ch = (offset - 0x200) >> 4; |
362 |
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
363 |
goto fail;
|
364 |
|
365 |
switch (offset & 0xf) { |
366 |
case DMA_FDADR:
|
367 |
return s->dma_ch[ch].descriptor;
|
368 |
case DMA_FSADR:
|
369 |
return s->dma_ch[ch].source;
|
370 |
case DMA_FIDR:
|
371 |
return s->dma_ch[ch].id;
|
372 |
case DMA_LDCMD:
|
373 |
return s->dma_ch[ch].command;
|
374 |
default:
|
375 |
goto fail;
|
376 |
} |
377 |
|
378 |
case FBR0:
|
379 |
return s->dma_ch[0].branch; |
380 |
case FBR1:
|
381 |
return s->dma_ch[1].branch; |
382 |
case FBR2:
|
383 |
return s->dma_ch[2].branch; |
384 |
case FBR3:
|
385 |
return s->dma_ch[3].branch; |
386 |
case FBR4:
|
387 |
return s->dma_ch[4].branch; |
388 |
case FBR5:
|
389 |
return s->dma_ch[5].branch; |
390 |
case FBR6:
|
391 |
return s->dma_ch[6].branch; |
392 |
|
393 |
case BSCNTR:
|
394 |
return s->bscntr;
|
395 |
|
396 |
case PRSR:
|
397 |
return 0; |
398 |
|
399 |
case LCSR0:
|
400 |
return s->status[0]; |
401 |
case LCSR1:
|
402 |
return s->status[1]; |
403 |
case LIIDR:
|
404 |
return s->liidr;
|
405 |
|
406 |
default:
|
407 |
fail:
|
408 |
cpu_abort(cpu_single_env, |
409 |
"%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
410 |
} |
411 |
|
412 |
return 0; |
413 |
} |
414 |
|
415 |
static void pxa2xx_lcdc_write(void *opaque, |
416 |
target_phys_addr_t offset, uint32_t value) |
417 |
{ |
418 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
419 |
int ch;
|
420 |
offset -= s->base; |
421 |
|
422 |
switch (offset) {
|
423 |
case LCCR0:
|
424 |
/* ACK Quick Disable done */
|
425 |
if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB)) |
426 |
s->status[0] |= LCSR0_QD;
|
427 |
|
428 |
if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) |
429 |
printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
|
430 |
|
431 |
if ((s->control[3] & LCCR3_API) && |
432 |
(value & LCCR0_ENB) && !(value & LCCR0_LCDT)) |
433 |
s->status[0] |= LCSR0_ABC;
|
434 |
|
435 |
s->control[0] = value & 0x07ffffff; |
436 |
pxa2xx_lcdc_int_update(s); |
437 |
|
438 |
s->dma_ch[0].up = !!(value & LCCR0_ENB);
|
439 |
s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS); |
440 |
break;
|
441 |
|
442 |
case LCCR1:
|
443 |
s->control[1] = value;
|
444 |
break;
|
445 |
|
446 |
case LCCR2:
|
447 |
s->control[2] = value;
|
448 |
break;
|
449 |
|
450 |
case LCCR3:
|
451 |
s->control[3] = value & 0xefffffff; |
452 |
s->bpp = LCCR3_BPP(value); |
453 |
break;
|
454 |
|
455 |
case LCCR4:
|
456 |
s->control[4] = value & 0x83ff81ff; |
457 |
break;
|
458 |
|
459 |
case LCCR5:
|
460 |
s->control[5] = value & 0x3f3f3f3f; |
461 |
break;
|
462 |
|
463 |
case OVL1C1:
|
464 |
if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
465 |
printf("%s: Overlay 1 not supported\n", __FUNCTION__);
|
466 |
|
467 |
s->ovl1c[0] = value & 0x80ffffff; |
468 |
s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS); |
469 |
break;
|
470 |
|
471 |
case OVL1C2:
|
472 |
s->ovl1c[1] = value & 0x000fffff; |
473 |
break;
|
474 |
|
475 |
case OVL2C1:
|
476 |
if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
477 |
printf("%s: Overlay 2 not supported\n", __FUNCTION__);
|
478 |
|
479 |
s->ovl2c[0] = value & 0x80ffffff; |
480 |
s->dma_ch[2].up = !!(value & OVLC1_EN);
|
481 |
s->dma_ch[3].up = !!(value & OVLC1_EN);
|
482 |
s->dma_ch[4].up = !!(value & OVLC1_EN);
|
483 |
break;
|
484 |
|
485 |
case OVL2C2:
|
486 |
s->ovl2c[1] = value & 0x007fffff; |
487 |
break;
|
488 |
|
489 |
case CCR:
|
490 |
if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
|
491 |
printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
|
492 |
|
493 |
s->ccr = value & 0x81ffffe7;
|
494 |
s->dma_ch[5].up = !!(value & CCR_CEN);
|
495 |
break;
|
496 |
|
497 |
case CMDCR:
|
498 |
s->cmdcr = value & 0xff;
|
499 |
break;
|
500 |
|
501 |
case TRGBR:
|
502 |
s->trgbr = value & 0x00ffffff;
|
503 |
break;
|
504 |
|
505 |
case TCR:
|
506 |
s->tcr = value & 0x7fff;
|
507 |
break;
|
508 |
|
509 |
case 0x200 ... 0x1000: /* DMA per-channel registers */ |
510 |
ch = (offset - 0x200) >> 4; |
511 |
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
512 |
goto fail;
|
513 |
|
514 |
switch (offset & 0xf) { |
515 |
case DMA_FDADR:
|
516 |
s->dma_ch[ch].descriptor = value & 0xfffffff0;
|
517 |
break;
|
518 |
|
519 |
default:
|
520 |
goto fail;
|
521 |
} |
522 |
break;
|
523 |
|
524 |
case FBR0:
|
525 |
s->dma_ch[0].branch = value & 0xfffffff3; |
526 |
break;
|
527 |
case FBR1:
|
528 |
s->dma_ch[1].branch = value & 0xfffffff3; |
529 |
break;
|
530 |
case FBR2:
|
531 |
s->dma_ch[2].branch = value & 0xfffffff3; |
532 |
break;
|
533 |
case FBR3:
|
534 |
s->dma_ch[3].branch = value & 0xfffffff3; |
535 |
break;
|
536 |
case FBR4:
|
537 |
s->dma_ch[4].branch = value & 0xfffffff3; |
538 |
break;
|
539 |
case FBR5:
|
540 |
s->dma_ch[5].branch = value & 0xfffffff3; |
541 |
break;
|
542 |
case FBR6:
|
543 |
s->dma_ch[6].branch = value & 0xfffffff3; |
544 |
break;
|
545 |
|
546 |
case BSCNTR:
|
547 |
s->bscntr = value & 0xf;
|
548 |
break;
|
549 |
|
550 |
case PRSR:
|
551 |
break;
|
552 |
|
553 |
case LCSR0:
|
554 |
s->status[0] &= ~(value & 0xfff); |
555 |
if (value & LCSR0_BER)
|
556 |
s->status[0] &= ~LCSR0_BERCH(7); |
557 |
break;
|
558 |
|
559 |
case LCSR1:
|
560 |
s->status[1] &= ~(value & 0x3e3f3f); |
561 |
break;
|
562 |
|
563 |
default:
|
564 |
fail:
|
565 |
cpu_abort(cpu_single_env, |
566 |
"%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
567 |
} |
568 |
} |
569 |
|
570 |
static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
|
571 |
pxa2xx_lcdc_read, |
572 |
pxa2xx_lcdc_read, |
573 |
pxa2xx_lcdc_read |
574 |
}; |
575 |
|
576 |
static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
|
577 |
pxa2xx_lcdc_write, |
578 |
pxa2xx_lcdc_write, |
579 |
pxa2xx_lcdc_write |
580 |
}; |
581 |
|
582 |
/* Load new palette for a given DMA channel, convert to internal format */
|
583 |
static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp) |
584 |
{ |
585 |
int i, n, format, r, g, b, alpha;
|
586 |
uint32_t *dest, *src; |
587 |
s->pal_for = LCCR4_PALFOR(s->control[4]);
|
588 |
format = s->pal_for; |
589 |
|
590 |
switch (bpp) {
|
591 |
case pxa_lcdc_2bpp:
|
592 |
n = 4;
|
593 |
break;
|
594 |
case pxa_lcdc_4bpp:
|
595 |
n = 16;
|
596 |
break;
|
597 |
case pxa_lcdc_8bpp:
|
598 |
n = 256;
|
599 |
break;
|
600 |
default:
|
601 |
format = 0;
|
602 |
return;
|
603 |
} |
604 |
|
605 |
src = (uint32_t *) s->dma_ch[ch].pbuffer; |
606 |
dest = (uint32_t *) s->dma_ch[ch].palette; |
607 |
alpha = r = g = b = 0;
|
608 |
|
609 |
for (i = 0; i < n; i ++) { |
610 |
switch (format) {
|
611 |
case 0: /* 16 bpp, no transparency */ |
612 |
alpha = 0;
|
613 |
if (s->control[0] & LCCR0_CMS) |
614 |
r = g = b = *src & 0xff;
|
615 |
else {
|
616 |
r = (*src & 0xf800) >> 8; |
617 |
g = (*src & 0x07e0) >> 3; |
618 |
b = (*src & 0x001f) << 3; |
619 |
} |
620 |
break;
|
621 |
case 1: /* 16 bpp plus transparency */ |
622 |
alpha = *src & (1 << 24); |
623 |
if (s->control[0] & LCCR0_CMS) |
624 |
r = g = b = *src & 0xff;
|
625 |
else {
|
626 |
r = (*src & 0xf800) >> 8; |
627 |
g = (*src & 0x07e0) >> 3; |
628 |
b = (*src & 0x001f) << 3; |
629 |
} |
630 |
break;
|
631 |
case 2: /* 18 bpp plus transparency */ |
632 |
alpha = *src & (1 << 24); |
633 |
if (s->control[0] & LCCR0_CMS) |
634 |
r = g = b = *src & 0xff;
|
635 |
else {
|
636 |
r = (*src & 0xf80000) >> 16; |
637 |
g = (*src & 0x00fc00) >> 8; |
638 |
b = (*src & 0x0000f8);
|
639 |
} |
640 |
break;
|
641 |
case 3: /* 24 bpp plus transparency */ |
642 |
alpha = *src & (1 << 24); |
643 |
if (s->control[0] & LCCR0_CMS) |
644 |
r = g = b = *src & 0xff;
|
645 |
else {
|
646 |
r = (*src & 0xff0000) >> 16; |
647 |
g = (*src & 0x00ff00) >> 8; |
648 |
b = (*src & 0x0000ff);
|
649 |
} |
650 |
break;
|
651 |
} |
652 |
switch (s->ds->depth) {
|
653 |
case 8: |
654 |
*dest = rgb_to_pixel8(r, g, b) | alpha; |
655 |
break;
|
656 |
case 15: |
657 |
*dest = rgb_to_pixel15(r, g, b) | alpha; |
658 |
break;
|
659 |
case 16: |
660 |
*dest = rgb_to_pixel16(r, g, b) | alpha; |
661 |
break;
|
662 |
case 24: |
663 |
*dest = rgb_to_pixel24(r, g, b) | alpha; |
664 |
break;
|
665 |
case 32: |
666 |
*dest = rgb_to_pixel32(r, g, b) | alpha; |
667 |
break;
|
668 |
} |
669 |
src ++; |
670 |
dest ++; |
671 |
} |
672 |
} |
673 |
|
674 |
static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s, |
675 |
uint8_t *fb, int *miny, int *maxy) |
676 |
{ |
677 |
int y, src_width, dest_width, dirty[2]; |
678 |
uint8_t *src, *dest; |
679 |
ram_addr_t x, addr, new_addr, start, end; |
680 |
drawfn fn = 0;
|
681 |
if (s->dest_width)
|
682 |
fn = s->line_fn[s->transp][s->bpp]; |
683 |
if (!fn)
|
684 |
return;
|
685 |
|
686 |
src = fb; |
687 |
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
688 |
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
689 |
src_width *= 3;
|
690 |
else if (s->bpp > pxa_lcdc_16bpp) |
691 |
src_width *= 4;
|
692 |
else if (s->bpp > pxa_lcdc_8bpp) |
693 |
src_width *= 2;
|
694 |
|
695 |
dest = s->ds->data; |
696 |
dest_width = s->xres * s->dest_width; |
697 |
|
698 |
addr = (ram_addr_t) (fb - phys_ram_base); |
699 |
start = addr + s->yres * src_width; |
700 |
end = addr; |
701 |
dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG); |
702 |
for (y = 0; y < s->yres; y ++) { |
703 |
new_addr = addr + src_width; |
704 |
for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
|
705 |
x += TARGET_PAGE_SIZE) { |
706 |
dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
|
707 |
dirty[0] |= dirty[1]; |
708 |
} |
709 |
if (dirty[0] || s->invalidated) { |
710 |
fn((uint32_t *) s->dma_ch[0].palette,
|
711 |
dest, src, s->xres, s->dest_width); |
712 |
if (addr < start)
|
713 |
start = addr; |
714 |
end = new_addr; |
715 |
if (y < *miny)
|
716 |
*miny = y; |
717 |
if (y >= *maxy)
|
718 |
*maxy = y + 1;
|
719 |
} |
720 |
addr = new_addr; |
721 |
dirty[0] = dirty[1]; |
722 |
src += src_width; |
723 |
dest += dest_width; |
724 |
} |
725 |
|
726 |
if (end > start)
|
727 |
cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG); |
728 |
} |
729 |
|
730 |
static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s, |
731 |
uint8_t *fb, int *miny, int *maxy) |
732 |
{ |
733 |
int y, src_width, dest_width, dirty[2]; |
734 |
uint8_t *src, *dest; |
735 |
ram_addr_t x, addr, new_addr, start, end; |
736 |
drawfn fn = 0;
|
737 |
if (s->dest_width)
|
738 |
fn = s->line_fn[s->transp][s->bpp]; |
739 |
if (!fn)
|
740 |
return;
|
741 |
|
742 |
src = fb; |
743 |
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
744 |
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
745 |
src_width *= 3;
|
746 |
else if (s->bpp > pxa_lcdc_16bpp) |
747 |
src_width *= 4;
|
748 |
else if (s->bpp > pxa_lcdc_8bpp) |
749 |
src_width *= 2;
|
750 |
|
751 |
dest_width = s->yres * s->dest_width; |
752 |
dest = s->ds->data + dest_width * (s->xres - 1);
|
753 |
|
754 |
addr = (ram_addr_t) (fb - phys_ram_base); |
755 |
start = addr + s->yres * src_width; |
756 |
end = addr; |
757 |
dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG); |
758 |
for (y = 0; y < s->yres; y ++) { |
759 |
new_addr = addr + src_width; |
760 |
for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
|
761 |
x += TARGET_PAGE_SIZE) { |
762 |
dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
|
763 |
dirty[0] |= dirty[1]; |
764 |
} |
765 |
if (dirty[0] || s->invalidated) { |
766 |
fn((uint32_t *) s->dma_ch[0].palette,
|
767 |
dest, src, s->xres, -dest_width); |
768 |
if (addr < start)
|
769 |
start = addr; |
770 |
end = new_addr; |
771 |
if (y < *miny)
|
772 |
*miny = y; |
773 |
if (y >= *maxy)
|
774 |
*maxy = y + 1;
|
775 |
} |
776 |
addr = new_addr; |
777 |
dirty[0] = dirty[1]; |
778 |
src += src_width; |
779 |
dest += s->dest_width; |
780 |
} |
781 |
|
782 |
if (end > start)
|
783 |
cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG); |
784 |
} |
785 |
|
786 |
static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s) |
787 |
{ |
788 |
int width, height;
|
789 |
if (!(s->control[0] & LCCR0_ENB)) |
790 |
return;
|
791 |
|
792 |
width = LCCR1_PPL(s->control[1]) + 1; |
793 |
height = LCCR2_LPP(s->control[2]) + 1; |
794 |
|
795 |
if (width != s->xres || height != s->yres) {
|
796 |
if (s->orientation)
|
797 |
dpy_resize(s->ds, height, width); |
798 |
else
|
799 |
dpy_resize(s->ds, width, height); |
800 |
s->invalidated = 1;
|
801 |
s->xres = width; |
802 |
s->yres = height; |
803 |
} |
804 |
} |
805 |
|
806 |
static void pxa2xx_update_display(void *opaque) |
807 |
{ |
808 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
809 |
uint8_t *fb; |
810 |
target_phys_addr_t fbptr; |
811 |
int miny, maxy;
|
812 |
int ch;
|
813 |
if (!(s->control[0] & LCCR0_ENB)) |
814 |
return;
|
815 |
|
816 |
pxa2xx_descriptor_load(s); |
817 |
|
818 |
pxa2xx_lcdc_resize(s); |
819 |
miny = s->yres; |
820 |
maxy = 0;
|
821 |
s->transp = s->dma_ch[2].up || s->dma_ch[3].up; |
822 |
/* Note: With overlay planes the order depends on LCCR0 bit 25. */
|
823 |
for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++) |
824 |
if (s->dma_ch[ch].up) {
|
825 |
if (!s->dma_ch[ch].source) {
|
826 |
pxa2xx_dma_ber_set(s, ch); |
827 |
continue;
|
828 |
} |
829 |
fbptr = s->dma_ch[ch].source; |
830 |
if (!(fbptr >= PXA2XX_SDRAM_BASE &&
|
831 |
fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) { |
832 |
pxa2xx_dma_ber_set(s, ch); |
833 |
continue;
|
834 |
} |
835 |
fbptr -= PXA2XX_SDRAM_BASE; |
836 |
fb = phys_ram_base + fbptr; |
837 |
|
838 |
if (s->dma_ch[ch].command & LDCMD_PAL) {
|
839 |
memcpy(s->dma_ch[ch].pbuffer, fb, |
840 |
MAX(LDCMD_LENGTH(s->dma_ch[ch].command), |
841 |
sizeof(s->dma_ch[ch].pbuffer)));
|
842 |
pxa2xx_palette_parse(s, ch, s->bpp); |
843 |
} else {
|
844 |
/* Do we need to reparse palette */
|
845 |
if (LCCR4_PALFOR(s->control[4]) != s->pal_for) |
846 |
pxa2xx_palette_parse(s, ch, s->bpp); |
847 |
|
848 |
/* ACK frame start */
|
849 |
pxa2xx_dma_sof_set(s, ch); |
850 |
|
851 |
s->dma_ch[ch].redraw(s, fb, &miny, &maxy); |
852 |
s->invalidated = 0;
|
853 |
|
854 |
/* ACK frame completed */
|
855 |
pxa2xx_dma_eof_set(s, ch); |
856 |
} |
857 |
} |
858 |
|
859 |
if (s->control[0] & LCCR0_DIS) { |
860 |
/* ACK last frame completed */
|
861 |
s->control[0] &= ~LCCR0_ENB;
|
862 |
s->status[0] |= LCSR0_LDD;
|
863 |
} |
864 |
|
865 |
if (s->orientation)
|
866 |
dpy_update(s->ds, miny, 0, maxy, s->xres);
|
867 |
else
|
868 |
dpy_update(s->ds, 0, miny, s->xres, maxy);
|
869 |
pxa2xx_lcdc_int_update(s); |
870 |
|
871 |
qemu_irq_raise(s->vsync_cb); |
872 |
} |
873 |
|
874 |
static void pxa2xx_invalidate_display(void *opaque) |
875 |
{ |
876 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
877 |
s->invalidated = 1;
|
878 |
} |
879 |
|
880 |
static void pxa2xx_screen_dump(void *opaque, const char *filename) |
881 |
{ |
882 |
/* TODO */
|
883 |
} |
884 |
|
885 |
static void pxa2xx_lcdc_orientation(void *opaque, int angle) |
886 |
{ |
887 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
888 |
|
889 |
if (angle) {
|
890 |
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
|
891 |
} else {
|
892 |
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
|
893 |
} |
894 |
|
895 |
s->orientation = angle; |
896 |
s->xres = s->yres = -1;
|
897 |
pxa2xx_lcdc_resize(s); |
898 |
} |
899 |
|
900 |
static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque) |
901 |
{ |
902 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
903 |
int i;
|
904 |
|
905 |
qemu_put_be32(f, s->irqlevel); |
906 |
qemu_put_be32(f, s->transp); |
907 |
|
908 |
for (i = 0; i < 6; i ++) |
909 |
qemu_put_be32s(f, &s->control[i]); |
910 |
for (i = 0; i < 2; i ++) |
911 |
qemu_put_be32s(f, &s->status[i]); |
912 |
for (i = 0; i < 2; i ++) |
913 |
qemu_put_be32s(f, &s->ovl1c[i]); |
914 |
for (i = 0; i < 2; i ++) |
915 |
qemu_put_be32s(f, &s->ovl2c[i]); |
916 |
qemu_put_be32s(f, &s->ccr); |
917 |
qemu_put_be32s(f, &s->cmdcr); |
918 |
qemu_put_be32s(f, &s->trgbr); |
919 |
qemu_put_be32s(f, &s->tcr); |
920 |
qemu_put_be32s(f, &s->liidr); |
921 |
qemu_put_8s(f, &s->bscntr); |
922 |
|
923 |
for (i = 0; i < 7; i ++) { |
924 |
qemu_put_betl(f, s->dma_ch[i].branch); |
925 |
qemu_put_byte(f, s->dma_ch[i].up); |
926 |
qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
|
927 |
|
928 |
qemu_put_betl(f, s->dma_ch[i].descriptor); |
929 |
qemu_put_betl(f, s->dma_ch[i].source); |
930 |
qemu_put_be32s(f, &s->dma_ch[i].id); |
931 |
qemu_put_be32s(f, &s->dma_ch[i].command); |
932 |
} |
933 |
} |
934 |
|
935 |
static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id) |
936 |
{ |
937 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
938 |
int i;
|
939 |
|
940 |
s->irqlevel = qemu_get_be32(f); |
941 |
s->transp = qemu_get_be32(f); |
942 |
|
943 |
for (i = 0; i < 6; i ++) |
944 |
qemu_get_be32s(f, &s->control[i]); |
945 |
for (i = 0; i < 2; i ++) |
946 |
qemu_get_be32s(f, &s->status[i]); |
947 |
for (i = 0; i < 2; i ++) |
948 |
qemu_get_be32s(f, &s->ovl1c[i]); |
949 |
for (i = 0; i < 2; i ++) |
950 |
qemu_get_be32s(f, &s->ovl2c[i]); |
951 |
qemu_get_be32s(f, &s->ccr); |
952 |
qemu_get_be32s(f, &s->cmdcr); |
953 |
qemu_get_be32s(f, &s->trgbr); |
954 |
qemu_get_be32s(f, &s->tcr); |
955 |
qemu_get_be32s(f, &s->liidr); |
956 |
qemu_get_8s(f, &s->bscntr); |
957 |
|
958 |
for (i = 0; i < 7; i ++) { |
959 |
s->dma_ch[i].branch = qemu_get_betl(f); |
960 |
s->dma_ch[i].up = qemu_get_byte(f); |
961 |
qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
|
962 |
|
963 |
s->dma_ch[i].descriptor = qemu_get_betl(f); |
964 |
s->dma_ch[i].source = qemu_get_betl(f); |
965 |
qemu_get_be32s(f, &s->dma_ch[i].id); |
966 |
qemu_get_be32s(f, &s->dma_ch[i].command); |
967 |
} |
968 |
|
969 |
s->bpp = LCCR3_BPP(s->control[3]);
|
970 |
s->xres = s->yres = s->pal_for = -1;
|
971 |
|
972 |
return 0; |
973 |
} |
974 |
|
975 |
#define BITS 8 |
976 |
#include "pxa2xx_template.h" |
977 |
#define BITS 15 |
978 |
#include "pxa2xx_template.h" |
979 |
#define BITS 16 |
980 |
#include "pxa2xx_template.h" |
981 |
#define BITS 24 |
982 |
#include "pxa2xx_template.h" |
983 |
#define BITS 32 |
984 |
#include "pxa2xx_template.h" |
985 |
|
986 |
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
987 |
DisplayState *ds) |
988 |
{ |
989 |
int iomemtype;
|
990 |
struct pxa2xx_lcdc_s *s;
|
991 |
|
992 |
s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s)); |
993 |
s->base = base; |
994 |
s->invalidated = 1;
|
995 |
s->irq = irq; |
996 |
s->ds = ds; |
997 |
|
998 |
pxa2xx_lcdc_orientation(s, graphic_rotate); |
999 |
|
1000 |
iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
|
1001 |
pxa2xx_lcdc_writefn, s); |
1002 |
cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
1003 |
|
1004 |
graphic_console_init(ds, pxa2xx_update_display, |
1005 |
pxa2xx_invalidate_display, pxa2xx_screen_dump, NULL, s);
|
1006 |
|
1007 |
switch (s->ds->depth) {
|
1008 |
case 0: |
1009 |
s->dest_width = 0;
|
1010 |
break;
|
1011 |
case 8: |
1012 |
s->line_fn[0] = pxa2xx_draw_fn_8;
|
1013 |
s->line_fn[1] = pxa2xx_draw_fn_8t;
|
1014 |
s->dest_width = 1;
|
1015 |
break;
|
1016 |
case 15: |
1017 |
s->line_fn[0] = pxa2xx_draw_fn_15;
|
1018 |
s->line_fn[1] = pxa2xx_draw_fn_15t;
|
1019 |
s->dest_width = 2;
|
1020 |
break;
|
1021 |
case 16: |
1022 |
s->line_fn[0] = pxa2xx_draw_fn_16;
|
1023 |
s->line_fn[1] = pxa2xx_draw_fn_16t;
|
1024 |
s->dest_width = 2;
|
1025 |
break;
|
1026 |
case 24: |
1027 |
s->line_fn[0] = pxa2xx_draw_fn_24;
|
1028 |
s->line_fn[1] = pxa2xx_draw_fn_24t;
|
1029 |
s->dest_width = 3;
|
1030 |
break;
|
1031 |
case 32: |
1032 |
s->line_fn[0] = pxa2xx_draw_fn_32;
|
1033 |
s->line_fn[1] = pxa2xx_draw_fn_32t;
|
1034 |
s->dest_width = 4;
|
1035 |
break;
|
1036 |
default:
|
1037 |
fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
|
1038 |
exit(1);
|
1039 |
} |
1040 |
|
1041 |
register_savevm("pxa2xx_lcdc", 0, 0, |
1042 |
pxa2xx_lcdc_save, pxa2xx_lcdc_load, s); |
1043 |
|
1044 |
return s;
|
1045 |
} |
1046 |
|
1047 |
void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler) |
1048 |
{ |
1049 |
s->vsync_cb = handler; |
1050 |
} |